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https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-14 06:43:18 +08:00
Remove unnecessary zeroing
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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ebd5f04e2d
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2601127679
@ -585,7 +585,6 @@ always @* begin
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s_axis_tready_next = 1'b0;
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if (s_axis_tuser[0]) begin
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output_type_next = OUTPUT_TYPE_ERROR;
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frame_ptr_next = 16'd0;
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ifg_count_next = 8'd8;
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state_next = STATE_IFG;
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end else begin
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@ -612,7 +611,6 @@ always @* begin
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end else begin
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// tvalid deassert, fail frame
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output_type_next = OUTPUT_TYPE_ERROR;
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frame_ptr_next = 16'd0;
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ifg_count_next = 8'd8;
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error_underflow_next = 1'b1;
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state_next = STATE_WAIT_END;
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@ -646,8 +644,6 @@ always @* begin
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output_data_next = fcs_output_data_0;
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output_type_next = fcs_output_type_0;
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frame_ptr_next = 16'd0;
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ifg_count_next = (ifg_delay > 8'd12 ? ifg_delay : 8'd12) - ifg_offset + (lanes_swapped ? 8'd4 : 8'd0) + deficit_idle_count_reg;
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if (extra_cycle) begin
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state_next = STATE_FCS_2;
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@ -663,7 +659,6 @@ always @* begin
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output_type_next = fcs_output_type_1;
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reset_crc = 1'b1;
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frame_ptr_next = 16'd0;
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if (ENABLE_DIC) begin
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if (ifg_count_next > 8'd7) begin
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@ -399,7 +399,6 @@ always @* begin
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if (s_axis_tuser[0]) begin
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xgmii_txd_next = {XGMII_TERM, {3{XGMII_ERROR}}};
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xgmii_txc_next = 4'b1111;
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frame_ptr_next = 16'd0;
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ifg_count_next = 8'd10;
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state_next = STATE_IFG;
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end else begin
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@ -427,7 +426,6 @@ always @* begin
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// tvalid deassert, fail frame
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xgmii_txd_next = {XGMII_TERM, {3{XGMII_ERROR}}};
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xgmii_txc_next = 4'b1111;
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frame_ptr_next = 16'd0;
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ifg_count_next = 8'd10;
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error_underflow_next = 1'b1;
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state_next = STATE_WAIT_END;
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@ -461,8 +459,6 @@ always @* begin
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xgmii_txd_next = fcs_output_txd_0;
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xgmii_txc_next = fcs_output_txc_0;
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frame_ptr_next = 16'd0;
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ifg_count_next = (ifg_delay > 8'd12 ? ifg_delay : 8'd12) - ifg_offset + deficit_idle_count_reg;
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state_next = STATE_FCS_2;
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end
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@ -473,8 +469,6 @@ always @* begin
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xgmii_txd_next = fcs_output_txd_1;
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xgmii_txc_next = fcs_output_txc_1;
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frame_ptr_next = 16'd0;
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if (extra_cycle) begin
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state_next = STATE_FCS_3;
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end else begin
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@ -489,7 +483,6 @@ always @* begin
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xgmii_txc_next = 4'b1111;
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reset_crc = 1'b1;
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frame_ptr_next = 16'd0;
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if (ENABLE_DIC) begin
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if (ifg_count_next > 8'd3) begin
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@ -533,7 +533,6 @@ always @* begin
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if (s_axis_tuser[0]) begin
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xgmii_txd_next = {{3{XGMII_IDLE}}, XGMII_TERM, {4{XGMII_ERROR}}};
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xgmii_txc_next = 8'b11111111;
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frame_ptr_next = 16'd0;
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ifg_count_next = 8'd8;
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state_next = STATE_IFG;
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end else begin
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@ -561,7 +560,6 @@ always @* begin
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// tvalid deassert, fail frame
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xgmii_txd_next = {{3{XGMII_IDLE}}, XGMII_TERM, {4{XGMII_ERROR}}};
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xgmii_txc_next = 8'b11111111;
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frame_ptr_next = 16'd0;
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ifg_count_next = 8'd8;
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error_underflow_next = 1'b1;
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state_next = STATE_WAIT_END;
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@ -595,8 +593,6 @@ always @* begin
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xgmii_txd_next = fcs_output_txd_0;
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xgmii_txc_next = fcs_output_txc_0;
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frame_ptr_next = 16'd0;
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ifg_count_next = (ifg_delay > 8'd12 ? ifg_delay : 8'd12) - ifg_offset + (lanes_swapped ? 8'd4 : 8'd0) + deficit_idle_count_reg;
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if (extra_cycle) begin
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state_next = STATE_FCS_2;
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@ -612,7 +608,6 @@ always @* begin
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xgmii_txc_next = fcs_output_txc_1;
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reset_crc = 1'b1;
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frame_ptr_next = 16'd0;
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if (ENABLE_DIC) begin
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if (ifg_count_next > 8'd7) begin
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