FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-14 06:43:18 +08:00
Code Issues Projects Releases Wiki Activity

Add enable signals to xgmii model

Browse Source
This commit is contained in:
Alex Forencich 2018-11-09 16:47:19 -08:00
parent 6b85aed564
commit 261ad46a8a
1 changed files with 4 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
tb/xgmii_ep.py
View File

@ -122,6 +122,7 @@ class XGMIISource(object):
rst,
txd,
txc,
enable=True,
name=None
):
@ -154,7 +155,7 @@ class XGMIISource(object):
ifg_cnt = 0
deficit_idle_cnt = 0
nt = False
else:
elif enable:
if ifg_cnt > bw-1:
ifg_cnt -= bw
txd.next = 0x0707070707070707 if bw == 8 else 0x07070707
@ -258,6 +259,7 @@ class XGMIISink(object):
rst,
rxd,
rxc,
enable=True,
name=None
):
@ -282,7 +284,7 @@ class XGMIISink(object):
frame = None
d = []
c = []
else:
elif enable:
if frame is None:
if rxc & 1 and rxd & 0xff == 0xfb:
# start in lane 0