FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-28 07:03:08 +08:00
Code Issues Projects Releases Wiki Activity

Use common sync_reset module files

Browse Source
This commit is contained in:
Alex Forencich 2020-03-27 18:27:45 -07:00
parent 12083439ac
commit 27ed447005
63 changed files with 118 additions and 1145 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
example/ADM_PCIE_9V3/fpga_10g/fpga/Makefile
View File

@ -8,7 +8,6 @@ FPGA_ARCH = virtexuplus
SYN_FILES = rtl/fpga.v
SYN_FILES += rtl/fpga_core.v
SYN_FILES += rtl/debounce_switch.v
SYN_FILES += rtl/sync_reset.v
SYN_FILES += rtl/sync_signal.v
SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
@ -46,11 +45,13 @@ SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl
# IP
XCI_FILES += ip/gtwizard_ultrascale_0.xci

20
example/ADM_PCIE_9V3/fpga_10g/rtl/fpga.v
View File

@ -190,7 +190,7 @@ sync_reset #(
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.sync_reset_out(rst_125mhz_int)
.out(rst_125mhz_int)
);
// GPIO
@ -385,7 +385,7 @@ sync_reset #(
sync_reset_156mhz_inst (
.clk(clk_156mhz_int),
.rst(~gt_reset_tx_done),
.sync_reset_out(rst_156mhz_int)
.out(rst_156mhz_int)
);
wire [5:0] qsfp_0_gt_txheader_0;
@ -520,7 +520,7 @@ sync_reset #(
qsfp_0_rx_rst_0_reset_sync_inst (
.clk(qsfp_0_rx_clk_0_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp_0_rx_rst_0_int)
.out(qsfp_0_rx_rst_0_int)
);
eth_phy_10g #(
@ -555,7 +555,7 @@ sync_reset #(
qsfp_0_rx_rst_1_reset_sync_inst (
.clk(qsfp_0_rx_clk_1_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp_0_rx_rst_1_int)
.out(qsfp_0_rx_rst_1_int)
);
eth_phy_10g #(
@ -590,7 +590,7 @@ sync_reset #(
qsfp_0_rx_rst_2_reset_sync_inst (
.clk(qsfp_0_rx_clk_2_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp_0_rx_rst_2_int)
.out(qsfp_0_rx_rst_2_int)
);
eth_phy_10g #(
@ -625,7 +625,7 @@ sync_reset #(
qsfp_0_rx_rst_3_reset_sync_inst (
.clk(qsfp_0_rx_clk_3_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp_0_rx_rst_3_int)
.out(qsfp_0_rx_rst_3_int)
);
eth_phy_10g #(
@ -660,7 +660,7 @@ sync_reset #(
qsfp_1_rx_rst_0_reset_sync_inst (
.clk(qsfp_1_rx_clk_0_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp_1_rx_rst_0_int)
.out(qsfp_1_rx_rst_0_int)
);
eth_phy_10g #(
@ -695,7 +695,7 @@ sync_reset #(
qsfp_1_rx_rst_1_reset_sync_inst (
.clk(qsfp_1_rx_clk_1_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp_1_rx_rst_1_int)
.out(qsfp_1_rx_rst_1_int)
);
eth_phy_10g #(
@ -730,7 +730,7 @@ sync_reset #(
qsfp_1_rx_rst_2_reset_sync_inst (
.clk(qsfp_1_rx_clk_2_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp_1_rx_rst_2_int)
.out(qsfp_1_rx_rst_2_int)
);
eth_phy_10g #(
@ -765,7 +765,7 @@ sync_reset #(
qsfp_1_rx_rst_3_reset_sync_inst (
.clk(qsfp_1_rx_clk_3_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp_1_rx_rst_3_int)
.out(qsfp_1_rx_rst_3_int)
);
eth_phy_10g #(

52
example/ADM_PCIE_9V3/fpga_10g/rtl/sync_reset.v
View File

@ -1,52 +0,0 @@
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`timescale 1 ns / 1 ps
/*
* Synchronizes an active-high asynchronous reset signal to a given clock by
* using a pipeline of N registers.
*/
module sync_reset #(
parameter N=2 // depth of synchronizer
)(
input wire clk,
input wire rst,
output wire sync_reset_out
);
reg [N-1:0] sync_reg = {N{1'b1}};
assign sync_reset_out = sync_reg[N-1];
always @(posedge clk or posedge rst) begin
if (rst)
sync_reg <= {N{1'b1}};
else
sync_reg <= {sync_reg[N-2:0], 1'b0};
end
endmodule

3
example/ADM_PCIE_9V3/fpga_25g/fpga/Makefile
View File

@ -8,7 +8,6 @@ FPGA_ARCH = virtexuplus
SYN_FILES = rtl/fpga.v
SYN_FILES += rtl/fpga_core.v
SYN_FILES += rtl/debounce_switch.v
SYN_FILES += rtl/sync_reset.v
SYN_FILES += rtl/sync_signal.v
SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
@ -46,11 +45,13 @@ SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl
# IP
XCI_FILES += ip/gtwizard_ultrascale_0.xci

20
example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
View File

@ -190,7 +190,7 @@ sync_reset #(
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.sync_reset_out(rst_125mhz_int)
.out(rst_125mhz_int)
);
// GPIO
@ -385,7 +385,7 @@ sync_reset #(
sync_reset_156mhz_inst (
.clk(clk_156mhz_int),
.rst(~gt_reset_tx_done),
.sync_reset_out(rst_156mhz_int)
.out(rst_156mhz_int)
);
wire [5:0] qsfp_0_gt_txheader_0;
@ -520,7 +520,7 @@ sync_reset #(
qsfp_0_rx_rst_0_reset_sync_inst (
.clk(qsfp_0_rx_clk_0_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp_0_rx_rst_0_int)
.out(qsfp_0_rx_rst_0_int)
);
eth_phy_10g #(
@ -558,7 +558,7 @@ sync_reset #(
qsfp_0_rx_rst_1_reset_sync_inst (
.clk(qsfp_0_rx_clk_1_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp_0_rx_rst_1_int)
.out(qsfp_0_rx_rst_1_int)
);
eth_phy_10g #(
@ -596,7 +596,7 @@ sync_reset #(
qsfp_0_rx_rst_2_reset_sync_inst (
.clk(qsfp_0_rx_clk_2_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp_0_rx_rst_2_int)
.out(qsfp_0_rx_rst_2_int)
);
eth_phy_10g #(
@ -634,7 +634,7 @@ sync_reset #(
qsfp_0_rx_rst_3_reset_sync_inst (
.clk(qsfp_0_rx_clk_3_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp_0_rx_rst_3_int)
.out(qsfp_0_rx_rst_3_int)
);
eth_phy_10g #(
@ -672,7 +672,7 @@ sync_reset #(
qsfp_1_rx_rst_0_reset_sync_inst (
.clk(qsfp_1_rx_clk_0_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp_1_rx_rst_0_int)
.out(qsfp_1_rx_rst_0_int)
);
eth_phy_10g #(
@ -710,7 +710,7 @@ sync_reset #(
qsfp_1_rx_rst_1_reset_sync_inst (
.clk(qsfp_1_rx_clk_1_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp_1_rx_rst_1_int)
.out(qsfp_1_rx_rst_1_int)
);
eth_phy_10g #(
@ -748,7 +748,7 @@ sync_reset #(
qsfp_1_rx_rst_2_reset_sync_inst (
.clk(qsfp_1_rx_clk_2_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp_1_rx_rst_2_int)
.out(qsfp_1_rx_rst_2_int)
);
eth_phy_10g #(
@ -786,7 +786,7 @@ sync_reset #(
qsfp_1_rx_rst_3_reset_sync_inst (
.clk(qsfp_1_rx_clk_3_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp_1_rx_rst_3_int)
.out(qsfp_1_rx_rst_3_int)
);
eth_phy_10g #(

52
example/ADM_PCIE_9V3/fpga_25g/rtl/sync_reset.v
View File

@ -1,52 +0,0 @@
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`timescale 1 ns / 1 ps
/*
* Synchronizes an active-high asynchronous reset signal to a given clock by
* using a pipeline of N registers.
*/
module sync_reset #(
parameter N=2 // depth of synchronizer
)(
input wire clk,
input wire rst,
output wire sync_reset_out
);
reg [N-1:0] sync_reg = {N{1'b1}};
assign sync_reset_out = sync_reg[N-1];
always @(posedge clk or posedge rst) begin
if (rst)
sync_reg <= {N{1'b1}};
else
sync_reg <= {sync_reg[N-2:0], 1'b0};
end
endmodule

2
example/ATLYS/fpga/fpga/Makefile
View File

@ -12,7 +12,6 @@ FPGA_ARCH = spartan6
SYN_FILES = rtl/fpga.v
SYN_FILES += rtl/fpga_core.v
SYN_FILES += rtl/debounce_switch.v
SYN_FILES += rtl/sync_reset.v
SYN_FILES += rtl/sync_signal.v
SYN_FILES += lib/eth/rtl/iddr.v
SYN_FILES += lib/eth/rtl/oddr.v
@ -47,6 +46,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
#SYN_FILES += coregen/dcm_i100_o125/dcm_i100_o125.v
# UCF files

2
example/ATLYS/fpga/rtl/fpga.v
View File

@ -137,7 +137,7 @@ sync_reset #(
sync_reset_inst (
.clk(clk_int),
.rst(~dcm_locked),
.sync_reset_out(rst_int)
.out(rst_int)
);
// GPIO

52
example/ATLYS/fpga/rtl/sync_reset.v
View File

@ -1,52 +0,0 @@
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`timescale 1 ns / 1 ps
/*
* Synchronizes an active-high asynchronous reset signal to a given clock by
* using a pipeline of N registers.
*/
module sync_reset #(
parameter N=2 // depth of synchronizer
)(
input wire clk,
input wire rst,
output wire sync_reset_out
);
reg [N-1:0] sync_reg = {N{1'b1}};
assign sync_reset_out = sync_reg[N-1];
always @(posedge clk or posedge rst) begin
if (rst)
sync_reg <= {N{1'b1}};
else
sync_reg <= {sync_reg[N-2:0], 1'b0};
end
endmodule

3
example/Arty/fpga/fpga/Makefile
View File

@ -8,7 +8,6 @@ FPGA_ARCH = artix7
SYN_FILES = rtl/fpga.v
SYN_FILES += rtl/fpga_core.v
SYN_FILES += rtl/debounce_switch.v
SYN_FILES += rtl/sync_reset.v
SYN_FILES += rtl/sync_signal.v
SYN_FILES += lib/eth/rtl/ssio_sdr_in.v
SYN_FILES += lib/eth/rtl/mii_phy_if.v
@ -40,12 +39,14 @@ SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += lib/eth/syn/mii_phy_if.tcl
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl
include ../common/vivado.mk

2
example/Arty/fpga/rtl/fpga.v
View File

@ -182,7 +182,7 @@ sync_reset #(
sync_reset_inst (
.clk(clk_int),
.rst(~mmcm_locked),
.sync_reset_out(rst_int)
.out(rst_int)
);
// GPIO

52
example/Arty/fpga/rtl/sync_reset.v
View File

@ -1,52 +0,0 @@
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`timescale 1 ns / 1 ps
/*
* Synchronizes an active-high asynchronous reset signal to a given clock by
* using a pipeline of N registers.
*/
module sync_reset #(
parameter N=2 // depth of synchronizer
)(
input wire clk,
input wire rst,
output wire sync_reset_out
);
reg [N-1:0] sync_reg = {N{1'b1}};
assign sync_reset_out = sync_reg[N-1];
always @(posedge clk or posedge rst) begin
if (rst)
sync_reg <= {N{1'b1}};
else
sync_reg <= {sync_reg[N-2:0], 1'b0};
end
endmodule

2
example/DE5-Net/fpga/fpga/Makefile
View File

@ -8,7 +8,6 @@ FPGA_DEVICE = 5SGXEA7N2F45C2
SYN_FILES = rtl/fpga.v
SYN_FILES += rtl/fpga_core.v
SYN_FILES += rtl/debounce_switch.v
SYN_FILES += rtl/sync_reset.v
SYN_FILES += rtl/sync_signal.v
SYN_FILES += rtl/i2c_master.v
SYN_FILES += rtl/si570_i2c_init.v
@ -41,6 +40,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
SYN_FILES += cores/phy/phy.qip
SYN_FILES += cores/phy_reconfig/phy_reconfig.qip

4
example/DE5-Net/fpga/rtl/fpga.v
View File

@ -121,7 +121,7 @@ sync_reset #(
sync_reset_50mhz_inst (
.clk(clk_50mhz),
.rst(~CPU_RESET_n),
.sync_reset_out(rst_50mhz)
.out(rst_50mhz)
);
wire clk_156mhz;
@ -135,7 +135,7 @@ sync_reset #(
sync_reset_156mhz_inst (
.clk(clk_156mhz),
.rst(rst_50mhz | ~phy_pll_locked),
.sync_reset_out(rst_156mhz)
.out(rst_156mhz)
);
// GPIO

52
example/DE5-Net/fpga/rtl/sync_reset.v
View File

@ -1,52 +0,0 @@
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`timescale 1 ns / 1 ps
/*
* Synchronizes an active-high asynchronous reset signal to a given clock by
* using a pipeline of N registers.
*/
module sync_reset #(
parameter N=2 // depth of synchronizer
)(
input wire clk,
input wire rst,
output wire sync_reset_out
);
reg [N-1:0] sync_reg = {N{1'b1}};
assign sync_reset_out = sync_reg[N-1];
always @(posedge clk or posedge rst) begin
if (rst)
sync_reg <= {N{1'b1}};
else
sync_reg <= {sync_reg[N-2:0], 1'b0};
end
endmodule

3
example/ExaNIC_X10/fpga/fpga/Makefile
View File

@ -7,7 +7,6 @@ FPGA_ARCH = kintexu
# Files for synthesis
SYN_FILES = rtl/fpga.v
SYN_FILES += rtl/fpga_core.v
SYN_FILES += rtl/sync_reset.v
SYN_FILES += rtl/sync_signal.v
SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
@ -45,11 +44,13 @@ SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl
# IP
XCI_FILES = ip/gtwizard_ultrascale_0.xci

8
example/ExaNIC_X10/fpga/rtl/fpga.v
View File

@ -163,7 +163,7 @@ sync_reset #(
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.sync_reset_out(rst_125mhz_int)
.out(rst_125mhz_int)
);
// GPIO
@ -304,7 +304,7 @@ sync_reset #(
sync_reset_156mhz_inst (
.clk(clk_156mhz_int),
.rst(~gt_reset_tx_done),
.sync_reset_out(rst_156mhz_int)
.out(rst_156mhz_int)
);
wire [5:0] sfp_1_gt_txheader;
@ -394,7 +394,7 @@ sync_reset #(
sfp_1_rx_rst_reset_sync_inst (
.clk(sfp_1_rx_clk_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(sfp_1_rx_rst_int)
.out(sfp_1_rx_rst_int)
);
eth_phy_10g #(
@ -429,7 +429,7 @@ sync_reset #(
sfp_2_rx_rst_reset_sync_inst (
.clk(sfp_2_rx_clk_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(sfp_2_rx_rst_int)
.out(sfp_2_rx_rst_int)
);
eth_phy_10g #(

52
example/ExaNIC_X10/fpga/rtl/sync_reset.v
View File

@ -1,52 +0,0 @@
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`timescale 1 ns / 1 ps
/*
* Synchronizes an active-high asynchronous reset signal to a given clock by
* using a pipeline of N registers.
*/
module sync_reset #(
parameter N=2 // depth of synchronizer
)(
input wire clk,
input wire rst,
output wire sync_reset_out
);
reg [N-1:0] sync_reg = {N{1'b1}};
assign sync_reset_out = sync_reg[N-1];
always @(posedge clk or posedge rst) begin
if (rst)
sync_reg <= {N{1'b1}};
else
sync_reg <= {sync_reg[N-2:0], 1'b0};
end
endmodule

3
example/ExaNIC_X25/fpga_10g/fpga/Makefile
View File

@ -7,7 +7,6 @@ FPGA_ARCH = kintexuplus
# Files for synthesis
SYN_FILES = rtl/fpga.v
SYN_FILES += rtl/fpga_core.v
SYN_FILES += rtl/sync_reset.v
SYN_FILES += rtl/sync_signal.v
SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
@ -45,11 +44,13 @@ SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl
# IP
XCI_FILES = ip/gtwizard_ultrascale_0.xci

8
example/ExaNIC_X25/fpga_10g/rtl/fpga.v
View File

@ -148,7 +148,7 @@ sync_reset #(
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.sync_reset_out(rst_125mhz_int)
.out(rst_125mhz_int)
);
// GPIO
@ -283,7 +283,7 @@ sync_reset #(
sync_reset_156mhz_inst (
.clk(clk_156mhz_int),
.rst(~gt_reset_tx_done),
.sync_reset_out(rst_156mhz_int)
.out(rst_156mhz_int)
);
wire [5:0] sfp_1_gt_txheader;
@ -375,7 +375,7 @@ sync_reset #(
sfp_1_rx_rst_reset_sync_inst (
.clk(sfp_1_rx_clk_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(sfp_1_rx_rst_int)
.out(sfp_1_rx_rst_int)
);
eth_phy_10g #(
@ -410,7 +410,7 @@ sync_reset #(
sfp_2_rx_rst_reset_sync_inst (
.clk(sfp_2_rx_clk_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(sfp_2_rx_rst_int)
.out(sfp_2_rx_rst_int)
);
eth_phy_10g #(

52
example/ExaNIC_X25/fpga_10g/rtl/sync_reset.v
View File

@ -1,52 +0,0 @@
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`timescale 1 ns / 1 ps
/*
* Synchronizes an active-high asynchronous reset signal to a given clock by
* using a pipeline of N registers.
*/
module sync_reset #(
parameter N=2 // depth of synchronizer
)(
input wire clk,
input wire rst,
output wire sync_reset_out
);
reg [N-1:0] sync_reg = {N{1'b1}};
assign sync_reset_out = sync_reg[N-1];
always @(posedge clk or posedge rst) begin
if (rst)
sync_reg <= {N{1'b1}};
else
sync_reg <= {sync_reg[N-2:0], 1'b0};
end
endmodule

2
example/HXT100G/fpga/fpga/Makefile
View File

@ -12,7 +12,6 @@ FPGA_ARCH = spartan6
SYN_FILES = rtl/fpga.v
SYN_FILES += rtl/fpga_core.v
SYN_FILES += rtl/debounce_switch.v
SYN_FILES += rtl/sync_reset.v
SYN_FILES += rtl/sync_signal.v
SYN_FILES += rtl/i2c_master.v
SYN_FILES += rtl/gth_i2c_init.v
@ -44,6 +43,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
SYN_FILES += coregen/ten_gig_eth_pcs_pma_v2_6/ten_gig_eth_pcs_pma_v2_6.v
SYN_FILES += coregen/ten_gig_eth_pcs_pma_v2_6/ten_gig_eth_pcs_pma_v2_6/example_design/ten_gig_eth_pcs_pma_v2_6_management_arbiter.v
SYN_FILES += coregen/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper_quad.v

6
example/HXT100G/fpga/rtl/fpga.v
View File

@ -385,7 +385,7 @@ sync_reset #(
sync_reset_inst (
.clk(sys_clk_int),
.rst(~reset_n),
.sync_reset_out(sys_rst)
.out(sys_rst)
);
sync_signal #(
@ -539,7 +539,7 @@ sync_reset #(
sync_reset_gth_inst (
.clk(sys_clk_int),
.rst(sys_rst | ~clk_gth_ready),
.sync_reset_out(gth_reset)
.out(gth_reset)
);
sync_reset #(
@ -548,7 +548,7 @@ sync_reset #(
sync_reset_156mhz_inst (
.clk(clk_156mhz),
.rst(gth_reset | ~gth_reset_done),
.sync_reset_out(rst_156mhz)
.out(rst_156mhz)
);
assign amh_right_phy_rst_n = ~rst_156mhz;

52
example/HXT100G/fpga/rtl/sync_reset.v
View File

@ -1,52 +0,0 @@
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`timescale 1 ns / 1 ps
/*
* Synchronizes an active-high asynchronous reset signal to a given clock by
* using a pipeline of N registers.
*/
module sync_reset #(
parameter N=2 // depth of synchronizer
)(
input wire clk,
input wire rst,
output wire sync_reset_out
);
reg [N-1:0] sync_reg = {N{1'b1}};
assign sync_reset_out = sync_reg[N-1];
always @(posedge clk) begin
if (rst)
sync_reg <= {N{1'b1}};
else
sync_reg <= {sync_reg[N-2:0], 1'b0};
end
endmodule

2
example/HXT100G/fpga_cxpt16/fpga/Makefile
View File

@ -12,7 +12,6 @@ FPGA_ARCH = spartan6
SYN_FILES = rtl/fpga.v
SYN_FILES += rtl/fpga_core.v
SYN_FILES += rtl/debounce_switch.v
SYN_FILES += rtl/sync_reset.v
SYN_FILES += rtl/sync_signal.v
SYN_FILES += rtl/i2c_master.v
SYN_FILES += rtl/gth_i2c_init.v
@ -27,6 +26,7 @@ SYN_FILES += lib/eth/rtl/eth_axis_tx_64.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_crosspoint.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
SYN_FILES += coregen/ten_gig_eth_pcs_pma_v2_6/ten_gig_eth_pcs_pma_v2_6.v
SYN_FILES += coregen/ten_gig_eth_pcs_pma_v2_6/ten_gig_eth_pcs_pma_v2_6/example_design/ten_gig_eth_pcs_pma_v2_6_management_arbiter.v
SYN_FILES += coregen/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper_quad.v

6
example/HXT100G/fpga_cxpt16/rtl/fpga.v
View File

@ -385,7 +385,7 @@ sync_reset #(
sync_reset_inst (
.clk(sys_clk_int),
.rst(~reset_n),
.sync_reset_out(sys_rst)
.out(sys_rst)
);
sync_signal #(
@ -539,7 +539,7 @@ sync_reset #(
sync_reset_gth_inst (
.clk(sys_clk_int),
.rst(sys_rst | ~clk_gth_ready),
.sync_reset_out(gth_reset)
.out(gth_reset)
);
sync_reset #(
@ -548,7 +548,7 @@ sync_reset #(
sync_reset_156mhz_inst (
.clk(clk_156mhz),
.rst(gth_reset | ~gth_reset_done),
.sync_reset_out(rst_156mhz)
.out(rst_156mhz)
);
assign amh_right_phy_rst_n = ~rst_156mhz;

52
example/HXT100G/fpga_cxpt16/rtl/sync_reset.v
View File

@ -1,52 +0,0 @@
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`timescale 1 ns / 1 ps
/*
* Synchronizes an active-high asynchronous reset signal to a given clock by
* using a pipeline of N registers.
*/
module sync_reset #(
parameter N=2 // depth of synchronizer
)(
input wire clk,
input wire rst,
output wire sync_reset_out
);
reg [N-1:0] sync_reg = {N{1'b1}};
assign sync_reset_out = sync_reg[N-1];
always @(posedge clk) begin
if (rst)
sync_reg <= {N{1'b1}};
else
sync_reg <= {sync_reg[N-2:0], 1'b0};
end
endmodule

3
example/KC705/fpga_gmii/fpga/Makefile
View File

@ -8,7 +8,6 @@ FPGA_ARCH = kintex7
SYN_FILES = rtl/fpga.v
SYN_FILES += rtl/fpga_core.v
SYN_FILES += rtl/debounce_switch.v
SYN_FILES += rtl/sync_reset.v
SYN_FILES += rtl/sync_signal.v
SYN_FILES += lib/eth/rtl/oddr.v
SYN_FILES += lib/eth/rtl/ssio_sdr_in.v
@ -42,6 +41,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
# XDC files
XDC_FILES = fpga.xdc
@ -50,6 +50,7 @@ XDC_FILES += lib/eth/syn/gmii_phy_if.tcl
XDC_FILES += lib/eth/syn/eth_mac_1g_gmii.tcl
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl
include ../common/vivado.mk

2
example/KC705/fpga_gmii/rtl/fpga.v
View File

@ -164,7 +164,7 @@ sync_reset #(
sync_reset_inst (
.clk(clk_int),
.rst(~mmcm_locked),
.sync_reset_out(rst_int)
.out(rst_int)
);
// GPIO

52
example/KC705/fpga_gmii/rtl/sync_reset.v
View File

@ -1,52 +0,0 @@
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`timescale 1 ns / 1 ps
/*
* Synchronizes an active-high asynchronous reset signal to a given clock by
* using a pipeline of N registers.
*/
module sync_reset #(
parameter N=2 // depth of synchronizer
)(
input wire clk,
input wire rst,
output wire sync_reset_out
);
reg [N-1:0] sync_reg = {N{1'b1}};
assign sync_reset_out = sync_reg[N-1];
always @(posedge clk or posedge rst) begin
if (rst)
sync_reg <= {N{1'b1}};
else
sync_reg <= {sync_reg[N-2:0], 1'b0};
end
endmodule

2
example/ML605/fpga_gmii/fpga_130t/Makefile
View File

@ -12,7 +12,6 @@ FPGA_ARCH = spartan6
SYN_FILES = rtl/fpga.v
SYN_FILES += rtl/fpga_core.v
SYN_FILES += rtl/debounce_switch.v
SYN_FILES += rtl/sync_reset.v
SYN_FILES += rtl/sync_signal.v
SYN_FILES += lib/eth/rtl/iddr.v
SYN_FILES += lib/eth/rtl/oddr.v
@ -47,6 +46,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
#SYN_FILES += coregen/dcm_i100_o125/dcm_i100_o125.v
# UCF files

2
example/ML605/fpga_gmii/fpga_240t/Makefile
View File

@ -12,7 +12,6 @@ FPGA_ARCH = spartan6
SYN_FILES = rtl/fpga.v
SYN_FILES += rtl/fpga_core.v
SYN_FILES += rtl/debounce_switch.v
SYN_FILES += rtl/sync_reset.v
SYN_FILES += rtl/sync_signal.v
SYN_FILES += lib/eth/rtl/iddr.v
SYN_FILES += lib/eth/rtl/oddr.v
@ -47,6 +46,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
#SYN_FILES += coregen/dcm_i100_o125/dcm_i100_o125.v
# UCF files

2
example/ML605/fpga_gmii/rtl/fpga.v
View File

@ -165,7 +165,7 @@ sync_reset #(
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.sync_reset_out(rst_125mhz_int)
.out(rst_125mhz_int)
);
// GPIO

52
example/ML605/fpga_gmii/rtl/sync_reset.v
View File

@ -1,52 +0,0 @@
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`timescale 1 ns / 1 ps
/*
* Synchronizes an active-high asynchronous reset signal to a given clock by
* using a pipeline of N registers.
*/
module sync_reset #(
parameter N=2 // depth of synchronizer
)(
input wire clk,
input wire rst,
output wire sync_reset_out
);
reg [N-1:0] sync_reg = {N{1'b1}};
assign sync_reset_out = sync_reg[N-1];
always @(posedge clk or posedge rst) begin
if (rst)
sync_reg <= {N{1'b1}};
else
sync_reg <= {sync_reg[N-2:0], 1'b0};
end
endmodule

2
example/ML605/fpga_rgmii/fpga_130t/Makefile
View File

@ -12,7 +12,6 @@ FPGA_ARCH = spartan6
SYN_FILES = rtl/fpga.v
SYN_FILES += rtl/fpga_core.v
SYN_FILES += rtl/debounce_switch.v
SYN_FILES += rtl/sync_reset.v
SYN_FILES += rtl/sync_signal.v
SYN_FILES += lib/eth/rtl/iddr.v
SYN_FILES += lib/eth/rtl/oddr.v
@ -47,6 +46,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
#SYN_FILES += coregen/dcm_i100_o125/dcm_i100_o125.v
# UCF files

2
example/ML605/fpga_rgmii/fpga_240t/Makefile
View File

@ -12,7 +12,6 @@ FPGA_ARCH = spartan6
SYN_FILES = rtl/fpga.v
SYN_FILES += rtl/fpga_core.v
SYN_FILES += rtl/debounce_switch.v
SYN_FILES += rtl/sync_reset.v
SYN_FILES += rtl/sync_signal.v
SYN_FILES += lib/eth/rtl/iddr.v
SYN_FILES += lib/eth/rtl/oddr.v
@ -47,6 +46,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
#SYN_FILES += coregen/dcm_i100_o125/dcm_i100_o125.v
# UCF files

2
example/ML605/fpga_rgmii/rtl/fpga.v
View File

@ -170,7 +170,7 @@ sync_reset #(
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.sync_reset_out(rst_125mhz_int)
.out(rst_125mhz_int)
);
// GPIO

52
example/ML605/fpga_rgmii/rtl/sync_reset.v
View File

@ -1,52 +0,0 @@
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`timescale 1 ns / 1 ps
/*
* Synchronizes an active-high asynchronous reset signal to a given clock by
* using a pipeline of N registers.
*/
module sync_reset #(
parameter N=2 // depth of synchronizer
)(
input wire clk,
input wire rst,
output wire sync_reset_out
);
reg [N-1:0] sync_reg = {N{1'b1}};
assign sync_reset_out = sync_reg[N-1];
always @(posedge clk or posedge rst) begin
if (rst)
sync_reg <= {N{1'b1}};
else
sync_reg <= {sync_reg[N-2:0], 1'b0};
end
endmodule

2
example/ML605/fpga_sgmii/fpga_130t/Makefile
View File

@ -12,7 +12,6 @@ FPGA_ARCH = spartan6
SYN_FILES = rtl/fpga.v
SYN_FILES += rtl/fpga_core.v
SYN_FILES += rtl/debounce_switch.v
SYN_FILES += rtl/sync_reset.v
SYN_FILES += rtl/sync_signal.v
SYN_FILES += lib/eth/rtl/eth_mac_1g_fifo.v
SYN_FILES += lib/eth/rtl/eth_mac_1g.v
@ -41,6 +40,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
SYN_FILES += coregen/gig_eth_pcs_pma_v11_5/gig_eth_pcs_pma_v11_5/example_design/sgmii_adapt/gig_eth_pcs_pma_v11_5_clk_gen.v
SYN_FILES += coregen/gig_eth_pcs_pma_v11_5/gig_eth_pcs_pma_v11_5/example_design/sgmii_adapt/gig_eth_pcs_pma_v11_5_johnson_cntr.v
SYN_FILES += coregen/gig_eth_pcs_pma_v11_5/gig_eth_pcs_pma_v11_5/example_design/sgmii_adapt/gig_eth_pcs_pma_v11_5_rx_rate_adapt.v

2
example/ML605/fpga_sgmii/fpga_240t/Makefile
View File

@ -12,7 +12,6 @@ FPGA_ARCH = spartan6
SYN_FILES = rtl/fpga.v
SYN_FILES += rtl/fpga_core.v
SYN_FILES += rtl/debounce_switch.v
SYN_FILES += rtl/sync_reset.v
SYN_FILES += rtl/sync_signal.v
SYN_FILES += lib/eth/rtl/eth_mac_1g_fifo.v
SYN_FILES += lib/eth/rtl/eth_mac_1g.v
@ -41,6 +40,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
SYN_FILES += coregen/gig_eth_pcs_pma_v11_5/gig_eth_pcs_pma_v11_5/example_design/sgmii_adapt/gig_eth_pcs_pma_v11_5_clk_gen.v
SYN_FILES += coregen/gig_eth_pcs_pma_v11_5/gig_eth_pcs_pma_v11_5/example_design/sgmii_adapt/gig_eth_pcs_pma_v11_5_johnson_cntr.v
SYN_FILES += coregen/gig_eth_pcs_pma_v11_5/gig_eth_pcs_pma_v11_5/example_design/sgmii_adapt/gig_eth_pcs_pma_v11_5_rx_rate_adapt.v

4
example/ML605/fpga_sgmii/rtl/fpga.v
View File

@ -162,7 +162,7 @@ sync_reset #(
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.sync_reset_out(rst_125mhz_int)
.out(rst_125mhz_int)
);
// GPIO
@ -267,7 +267,7 @@ sync_reset #(
sync_reset_pcspma_inst (
.clk(phy_gmii_clk_int),
.rst(rst_125mhz_int),
.sync_reset_out(phy_gmii_rst_int)
.out(phy_gmii_rst_int)
);
wire [15:0] pcspma_status_vector;

52
example/ML605/fpga_sgmii/rtl/sync_reset.v
View File

@ -1,52 +0,0 @@
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`timescale 1 ns / 1 ps
/*
* Synchronizes an active-high asynchronous reset signal to a given clock by
* using a pipeline of N registers.
*/
module sync_reset #(
parameter N=2 // depth of synchronizer
)(
input wire clk,
input wire rst,
output wire sync_reset_out
);
reg [N-1:0] sync_reg = {N{1'b1}};
assign sync_reset_out = sync_reg[N-1];
always @(posedge clk or posedge rst) begin
if (rst)
sync_reg <= {N{1'b1}};
else
sync_reg <= {sync_reg[N-2:0], 1'b0};
end
endmodule

3
example/NexysVideo/fpga/fpga/Makefile
View File

@ -8,7 +8,6 @@ FPGA_ARCH = artix7
SYN_FILES = rtl/fpga.v
SYN_FILES += rtl/fpga_core.v
SYN_FILES += rtl/debounce_switch.v
SYN_FILES += rtl/sync_reset.v
SYN_FILES += rtl/sync_signal.v
SYN_FILES += lib/eth/rtl/iddr.v
SYN_FILES += lib/eth/rtl/oddr.v
@ -43,6 +42,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
# XDC files
XDC_FILES = fpga.xdc
@ -51,6 +51,7 @@ XDC_FILES += lib/eth/syn/rgmii_phy_if.tcl
XDC_FILES += lib/eth/syn/eth_mac_1g_rgmii.tcl
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl
include ../common/vivado.mk

2
example/NexysVideo/fpga/rtl/fpga.v
View File

@ -179,7 +179,7 @@ sync_reset #(
sync_reset_inst (
.clk(clk_int),
.rst(~mmcm_locked),
.sync_reset_out(rst_int)
.out(rst_int)
);
// GPIO

52
example/NexysVideo/fpga/rtl/sync_reset.v
View File

@ -1,52 +0,0 @@
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`timescale 1 ns / 1 ps
/*
* Synchronizes an active-high asynchronous reset signal to a given clock by
* using a pipeline of N registers.
*/
module sync_reset #(
parameter N=2 // depth of synchronizer
)(
input wire clk,
input wire rst,
output wire sync_reset_out
);
reg [N-1:0] sync_reg = {N{1'b1}};
assign sync_reset_out = sync_reg[N-1];
always @(posedge clk or posedge rst) begin
if (rst)
sync_reg <= {N{1'b1}};
else
sync_reg <= {sync_reg[N-2:0], 1'b0};
end
endmodule

3
example/VCU108/fpga_10g/fpga/Makefile
View File

@ -8,7 +8,6 @@ FPGA_ARCH = VirtexUltrascale
SYN_FILES = rtl/fpga.v
SYN_FILES += rtl/fpga_core.v
SYN_FILES += rtl/debounce_switch.v
SYN_FILES += rtl/sync_reset.v
SYN_FILES += rtl/sync_signal.v
SYN_FILES += lib/eth/rtl/eth_mac_1g_fifo.v
SYN_FILES += lib/eth/rtl/eth_mac_1g.v
@ -53,12 +52,14 @@ SYN_FILES += lib/eth/lib/axis/rtl/axis_switch.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_register.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += eth.xdc
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl
# IP
XCI_FILES = ip/gig_ethernet_pcs_pma_0.xci

12
example/VCU108/fpga_10g/rtl/fpga.v
View File

@ -204,7 +204,7 @@ sync_reset #(
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.sync_reset_out(rst_125mhz_int)
.out(rst_125mhz_int)
);
// GPIO
@ -391,7 +391,7 @@ sync_reset #(
sync_reset_156mhz_inst (
.clk(clk_156mhz_int),
.rst(~gt_reset_tx_done),
.sync_reset_out(rst_156mhz_int)
.out(rst_156mhz_int)
);
wire [5:0] qsfp_gt_txheader_1;
@ -494,7 +494,7 @@ sync_reset #(
qsfp_rx_rst_1_reset_sync_inst (
.clk(qsfp_rx_clk_1_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp_rx_rst_1_int)
.out(qsfp_rx_rst_1_int)
);
eth_phy_10g #(
@ -529,7 +529,7 @@ sync_reset #(
qsfp_rx_rst_2_reset_sync_inst (
.clk(qsfp_rx_clk_2_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp_rx_rst_2_int)
.out(qsfp_rx_rst_2_int)
);
eth_phy_10g #(
@ -564,7 +564,7 @@ sync_reset #(
qsfp_rx_rst_3_reset_sync_inst (
.clk(qsfp_rx_clk_3_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp_rx_rst_3_int)
.out(qsfp_rx_rst_3_int)
);
eth_phy_10g #(
@ -599,7 +599,7 @@ sync_reset #(
qsfp_rx_rst_4_reset_sync_inst (
.clk(qsfp_rx_clk_4_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp_rx_rst_4_int)
.out(qsfp_rx_rst_4_int)
);
eth_phy_10g #(

52
example/VCU108/fpga_10g/rtl/sync_reset.v
View File

@ -1,52 +0,0 @@
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`timescale 1 ns / 1 ps
/*
* Synchronizes an active-high asynchronous reset signal to a given clock by
* using a pipeline of N registers.
*/
module sync_reset #(
parameter N=2 // depth of synchronizer
)(
input wire clk,
input wire rst,
output wire sync_reset_out
);
reg [N-1:0] sync_reg = {N{1'b1}};
assign sync_reset_out = sync_reg[N-1];
always @(posedge clk or posedge rst) begin
if (rst)
sync_reg <= {N{1'b1}};
else
sync_reg <= {sync_reg[N-2:0], 1'b0};
end
endmodule

3
example/VCU108/fpga_1g/fpga/Makefile
View File

@ -8,7 +8,6 @@ FPGA_ARCH = VirtexUltrascale
SYN_FILES = rtl/fpga.v
SYN_FILES += rtl/fpga_core.v
SYN_FILES += rtl/debounce_switch.v
SYN_FILES += rtl/sync_reset.v
SYN_FILES += rtl/sync_signal.v
SYN_FILES += lib/eth/rtl/eth_mac_1g_fifo.v
SYN_FILES += lib/eth/rtl/eth_mac_1g.v
@ -37,12 +36,14 @@ SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += eth.xdc
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl
# IP
XCI_FILES = ip/gig_ethernet_pcs_pma_0.xci

2
example/VCU108/fpga_1g/rtl/fpga.v
View File

@ -163,7 +163,7 @@ sync_reset #(
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.sync_reset_out(rst_125mhz_int)
.out(rst_125mhz_int)
);
// GPIO

52
example/VCU108/fpga_1g/rtl/sync_reset.v
View File

@ -1,52 +0,0 @@
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`timescale 1 ns / 1 ps
/*
* Synchronizes an active-high asynchronous reset signal to a given clock by
* using a pipeline of N registers.
*/
module sync_reset #(
parameter N=2 // depth of synchronizer
)(
input wire clk,
input wire rst,
output wire sync_reset_out
);
reg [N-1:0] sync_reg = {N{1'b1}};
assign sync_reset_out = sync_reg[N-1];
always @(posedge clk or posedge rst) begin
if (rst)
sync_reg <= {N{1'b1}};
else
sync_reg <= {sync_reg[N-2:0], 1'b0};
end
endmodule

3
example/VCU118/fpga_10g/fpga/Makefile
View File

@ -8,7 +8,6 @@ FPGA_ARCH = virtexuplus
SYN_FILES = rtl/fpga.v
SYN_FILES += rtl/fpga_core.v
SYN_FILES += rtl/debounce_switch.v
SYN_FILES += rtl/sync_reset.v
SYN_FILES += rtl/sync_signal.v
SYN_FILES += rtl/mdio_master.v
SYN_FILES += lib/eth/rtl/eth_mac_1g_fifo.v
@ -54,11 +53,13 @@ SYN_FILES += lib/eth/lib/axis/rtl/axis_switch.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_register.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl
# IP
XCI_FILES = ip/gig_ethernet_pcs_pma_0.xci

20
example/VCU118/fpga_10g/rtl/fpga.v
View File

@ -234,7 +234,7 @@ sync_reset #(
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.sync_reset_out(rst_125mhz_int)
.out(rst_125mhz_int)
);
// GPIO
@ -463,7 +463,7 @@ sync_reset #(
sync_reset_156mhz_inst (
.clk(clk_156mhz_int),
.rst(~gt_reset_tx_done),
.sync_reset_out(rst_156mhz_int)
.out(rst_156mhz_int)
);
wire [5:0] qsfp1_gt_txheader_1;
@ -598,7 +598,7 @@ sync_reset #(
qsfp1_rx_rst_1_reset_sync_inst (
.clk(qsfp1_rx_clk_1_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp1_rx_rst_1_int)
.out(qsfp1_rx_rst_1_int)
);
eth_phy_10g #(
@ -633,7 +633,7 @@ sync_reset #(
qsfp1_rx_rst_2_reset_sync_inst (
.clk(qsfp1_rx_clk_2_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp1_rx_rst_2_int)
.out(qsfp1_rx_rst_2_int)
);
eth_phy_10g #(
@ -668,7 +668,7 @@ sync_reset #(
qsfp1_rx_rst_3_reset_sync_inst (
.clk(qsfp1_rx_clk_3_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp1_rx_rst_3_int)
.out(qsfp1_rx_rst_3_int)
);
eth_phy_10g #(
@ -703,7 +703,7 @@ sync_reset #(
qsfp1_rx_rst_4_reset_sync_inst (
.clk(qsfp1_rx_clk_4_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp1_rx_rst_4_int)
.out(qsfp1_rx_rst_4_int)
);
eth_phy_10g #(
@ -738,7 +738,7 @@ sync_reset #(
qsfp2_rx_rst_1_reset_sync_inst (
.clk(qsfp2_rx_clk_1_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp2_rx_rst_1_int)
.out(qsfp2_rx_rst_1_int)
);
eth_phy_10g #(
@ -773,7 +773,7 @@ sync_reset #(
qsfp2_rx_rst_2_reset_sync_inst (
.clk(qsfp2_rx_clk_2_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp2_rx_rst_2_int)
.out(qsfp2_rx_rst_2_int)
);
eth_phy_10g #(
@ -808,7 +808,7 @@ sync_reset #(
qsfp2_rx_rst_3_reset_sync_inst (
.clk(qsfp2_rx_clk_3_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp2_rx_rst_3_int)
.out(qsfp2_rx_rst_3_int)
);
eth_phy_10g #(
@ -843,7 +843,7 @@ sync_reset #(
qsfp2_rx_rst_4_reset_sync_inst (
.clk(qsfp2_rx_clk_4_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp2_rx_rst_4_int)
.out(qsfp2_rx_rst_4_int)
);
eth_phy_10g #(

52
example/VCU118/fpga_10g/rtl/sync_reset.v
View File

@ -1,52 +0,0 @@
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`timescale 1 ns / 1 ps
/*
* Synchronizes an active-high asynchronous reset signal to a given clock by
* using a pipeline of N registers.
*/
module sync_reset #(
parameter N=2 // depth of synchronizer
)(
input wire clk,
input wire rst,
output wire sync_reset_out
);
reg [N-1:0] sync_reg = {N{1'b1}};
assign sync_reset_out = sync_reg[N-1];
always @(posedge clk or posedge rst) begin
if (rst)
sync_reg <= {N{1'b1}};
else
sync_reg <= {sync_reg[N-2:0], 1'b0};
end
endmodule

3
example/VCU118/fpga_1g/fpga/Makefile
View File

@ -8,7 +8,6 @@ FPGA_ARCH = virtexuplus
SYN_FILES = rtl/fpga.v
SYN_FILES += rtl/fpga_core.v
SYN_FILES += rtl/debounce_switch.v
SYN_FILES += rtl/sync_reset.v
SYN_FILES += rtl/sync_signal.v
SYN_FILES += rtl/mdio_master.v
SYN_FILES += lib/eth/rtl/eth_mac_1g_fifo.v
@ -38,11 +37,13 @@ SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl
# IP
XCI_FILES = ip/gig_ethernet_pcs_pma_0.xci

2
example/VCU118/fpga_1g/rtl/fpga.v
View File

@ -165,7 +165,7 @@ sync_reset #(
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.sync_reset_out(rst_125mhz_int)
.out(rst_125mhz_int)
);
// GPIO

52
example/VCU118/fpga_1g/rtl/sync_reset.v
View File

@ -1,52 +0,0 @@
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`timescale 1 ns / 1 ps
/*
* Synchronizes an active-high asynchronous reset signal to a given clock by
* using a pipeline of N registers.
*/
module sync_reset #(
parameter N=2 // depth of synchronizer
)(
input wire clk,
input wire rst,
output wire sync_reset_out
);
reg [N-1:0] sync_reg = {N{1'b1}};
assign sync_reset_out = sync_reg[N-1];
always @(posedge clk or posedge rst) begin
if (rst)
sync_reg <= {N{1'b1}};
else
sync_reg <= {sync_reg[N-2:0], 1'b0};
end
endmodule

3
example/VCU118/fpga_25g/fpga/Makefile
View File

@ -8,7 +8,6 @@ FPGA_ARCH = virtexuplus
SYN_FILES = rtl/fpga.v
SYN_FILES += rtl/fpga_core.v
SYN_FILES += rtl/debounce_switch.v
SYN_FILES += rtl/sync_reset.v
SYN_FILES += rtl/sync_signal.v
SYN_FILES += rtl/mdio_master.v
SYN_FILES += lib/eth/rtl/eth_mac_1g_fifo.v
@ -54,11 +53,13 @@ SYN_FILES += lib/eth/lib/axis/rtl/axis_switch.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_register.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl
# IP
XCI_FILES = ip/gig_ethernet_pcs_pma_0.xci

20
example/VCU118/fpga_25g/rtl/fpga.v
View File

@ -234,7 +234,7 @@ sync_reset #(
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.sync_reset_out(rst_125mhz_int)
.out(rst_125mhz_int)
);
// GPIO
@ -463,7 +463,7 @@ sync_reset #(
sync_reset_156mhz_inst (
.clk(clk_156mhz_int),
.rst(~gt_reset_tx_done),
.sync_reset_out(rst_156mhz_int)
.out(rst_156mhz_int)
);
wire [5:0] qsfp1_gt_txheader_1;
@ -598,7 +598,7 @@ sync_reset #(
qsfp1_rx_rst_1_reset_sync_inst (
.clk(qsfp1_rx_clk_1_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp1_rx_rst_1_int)
.out(qsfp1_rx_rst_1_int)
);
eth_phy_10g #(
@ -636,7 +636,7 @@ sync_reset #(
qsfp1_rx_rst_2_reset_sync_inst (
.clk(qsfp1_rx_clk_2_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp1_rx_rst_2_int)
.out(qsfp1_rx_rst_2_int)
);
eth_phy_10g #(
@ -674,7 +674,7 @@ sync_reset #(
qsfp1_rx_rst_3_reset_sync_inst (
.clk(qsfp1_rx_clk_3_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp1_rx_rst_3_int)
.out(qsfp1_rx_rst_3_int)
);
eth_phy_10g #(
@ -712,7 +712,7 @@ sync_reset #(
qsfp1_rx_rst_4_reset_sync_inst (
.clk(qsfp1_rx_clk_4_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp1_rx_rst_4_int)
.out(qsfp1_rx_rst_4_int)
);
eth_phy_10g #(
@ -750,7 +750,7 @@ sync_reset #(
qsfp2_rx_rst_1_reset_sync_inst (
.clk(qsfp2_rx_clk_1_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp2_rx_rst_1_int)
.out(qsfp2_rx_rst_1_int)
);
eth_phy_10g #(
@ -788,7 +788,7 @@ sync_reset #(
qsfp2_rx_rst_2_reset_sync_inst (
.clk(qsfp2_rx_clk_2_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp2_rx_rst_2_int)
.out(qsfp2_rx_rst_2_int)
);
eth_phy_10g #(
@ -826,7 +826,7 @@ sync_reset #(
qsfp2_rx_rst_3_reset_sync_inst (
.clk(qsfp2_rx_clk_3_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp2_rx_rst_3_int)
.out(qsfp2_rx_rst_3_int)
);
eth_phy_10g #(
@ -864,7 +864,7 @@ sync_reset #(
qsfp2_rx_rst_4_reset_sync_inst (
.clk(qsfp2_rx_clk_4_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp2_rx_rst_4_int)
.out(qsfp2_rx_rst_4_int)
);
eth_phy_10g #(

52
example/VCU118/fpga_25g/rtl/sync_reset.v
View File

@ -1,52 +0,0 @@
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`timescale 1 ns / 1 ps
/*
* Synchronizes an active-high asynchronous reset signal to a given clock by
* using a pipeline of N registers.
*/
module sync_reset #(
parameter N=2 // depth of synchronizer
)(
input wire clk,
input wire rst,
output wire sync_reset_out
);
reg [N-1:0] sync_reg = {N{1'b1}};
assign sync_reset_out = sync_reg[N-1];
always @(posedge clk or posedge rst) begin
if (rst)
sync_reg <= {N{1'b1}};
else
sync_reg <= {sync_reg[N-2:0], 1'b0};
end
endmodule

3
example/VCU1525/fpga_10g/fpga/Makefile
View File

@ -8,7 +8,6 @@ FPGA_ARCH = virtexuplus
SYN_FILES = rtl/fpga.v
SYN_FILES += rtl/fpga_core.v
SYN_FILES += rtl/debounce_switch.v
SYN_FILES += rtl/sync_reset.v
SYN_FILES += rtl/sync_signal.v
SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
@ -47,11 +46,13 @@ SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_register.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl
# IP
XCI_FILES = ip/gtwizard_ultrascale_0.xci

20
example/VCU1525/fpga_10g/rtl/fpga.v
View File

@ -203,7 +203,7 @@ sync_reset #(
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.sync_reset_out(rst_125mhz_int)
.out(rst_125mhz_int)
);
// GPIO
@ -493,7 +493,7 @@ sync_reset #(
sync_reset_156mhz_inst (
.clk(clk_156mhz_int),
.rst(~gt_reset_tx_done),
.sync_reset_out(rst_156mhz_int)
.out(rst_156mhz_int)
);
wire [5:0] qsfp0_gt_txheader_1;
@ -628,7 +628,7 @@ sync_reset #(
qsfp0_rx_rst_1_reset_sync_inst (
.clk(qsfp0_rx_clk_1_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp0_rx_rst_1_int)
.out(qsfp0_rx_rst_1_int)
);
eth_phy_10g #(
@ -663,7 +663,7 @@ sync_reset #(
qsfp0_rx_rst_2_reset_sync_inst (
.clk(qsfp0_rx_clk_2_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp0_rx_rst_2_int)
.out(qsfp0_rx_rst_2_int)
);
eth_phy_10g #(
@ -698,7 +698,7 @@ sync_reset #(
qsfp0_rx_rst_3_reset_sync_inst (
.clk(qsfp0_rx_clk_3_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp0_rx_rst_3_int)
.out(qsfp0_rx_rst_3_int)
);
eth_phy_10g #(
@ -733,7 +733,7 @@ sync_reset #(
qsfp0_rx_rst_4_reset_sync_inst (
.clk(qsfp0_rx_clk_4_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp0_rx_rst_4_int)
.out(qsfp0_rx_rst_4_int)
);
eth_phy_10g #(
@ -768,7 +768,7 @@ sync_reset #(
qsfp1_rx_rst_1_reset_sync_inst (
.clk(qsfp1_rx_clk_1_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp1_rx_rst_1_int)
.out(qsfp1_rx_rst_1_int)
);
eth_phy_10g #(
@ -803,7 +803,7 @@ sync_reset #(
qsfp1_rx_rst_2_reset_sync_inst (
.clk(qsfp1_rx_clk_2_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp1_rx_rst_2_int)
.out(qsfp1_rx_rst_2_int)
);
eth_phy_10g #(
@ -838,7 +838,7 @@ sync_reset #(
qsfp1_rx_rst_3_reset_sync_inst (
.clk(qsfp1_rx_clk_3_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp1_rx_rst_3_int)
.out(qsfp1_rx_rst_3_int)
);
eth_phy_10g #(
@ -873,7 +873,7 @@ sync_reset #(
qsfp1_rx_rst_4_reset_sync_inst (
.clk(qsfp1_rx_clk_4_int),
.rst(~gt_reset_rx_done),
.sync_reset_out(qsfp1_rx_rst_4_int)
.out(qsfp1_rx_rst_4_int)
);
eth_phy_10g #(

52
example/VCU1525/fpga_10g/rtl/sync_reset.v
View File

@ -1,52 +0,0 @@
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`timescale 1 ns / 1 ps
/*
* Synchronizes an active-high asynchronous reset signal to a given clock by
* using a pipeline of N registers.
*/
module sync_reset #(
parameter N=2 // depth of synchronizer
)(
input wire clk,
input wire rst,
output wire sync_reset_out
);
reg [N-1:0] sync_reg = {N{1'b1}};
assign sync_reset_out = sync_reg[N-1];
always @(posedge clk or posedge rst) begin
if (rst)
sync_reg <= {N{1'b1}};
else
sync_reg <= {sync_reg[N-2:0], 1'b0};
end
endmodule