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Fix signal name

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This commit is contained in:
Alex Forencich 2019-05-02 20:30:37 -07:00
parent 1d61626785
commit 2abb413854
1 changed files with 1 additions and 1 deletions
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example/KC705/fpga_gmii/rtl/fpga.v
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@ -80,7 +80,7 @@ wire clk_200mhz_bufg;
wire clk_200mhz_mmcm_out;
// Internal 125 MHz clock
wire clk_200mhz_int;
wire clk_int;
wire rst_int;
wire mmcm_rst = reset;