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Properly zero synchronized pointer on one-sided reset

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Alex Forencich 2021-10-17 01:23:02 -07:00
parent 10e24cc5b1
commit 2cd70281ea
1 changed files with 4 additions and 0 deletions
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4
rtl/axis_async_fifo.v
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@ -488,6 +488,10 @@ always @(posedge m_clk) begin
wr_ptr_update_sync2_reg <= wr_ptr_update_sync1_reg;
wr_ptr_update_sync3_reg <= wr_ptr_update_sync2_reg;
if (FRAME_FIFO && m_rst_sync3_reg) begin
wr_ptr_gray_sync1_reg <= {ADDR_WIDTH+1{1'b0}};
end
if (m_rst) begin
wr_ptr_gray_sync1_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_gray_sync2_reg <= {ADDR_WIDTH+1{1'b0}};