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Fix input clock period settings

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This commit is contained in:
Alex Forencich 2019-01-17 19:09:47 -08:00
parent dbbbc28059
commit 2e29aea857
2 changed files with 2 additions and 2 deletions
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2
example/ADM_PCIE_9V3/fpga_10g/rtl/fpga.v
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@ -153,7 +153,7 @@ MMCME3_BASE #(
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(3),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(8.0),
.CLKIN1_PERIOD(3.333),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)

2
example/ExaNIC_X10/fpga/rtl/fpga.v
View File

@ -126,7 +126,7 @@ MMCME3_BASE #(
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(8.0),
.CLKIN1_PERIOD(10.0),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)