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https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-28 07:03:08 +08:00
Fix input clock period settings
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parent
dbbbc28059
commit
2e29aea857
@ -153,7 +153,7 @@ MMCME3_BASE #(
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.CLKFBOUT_PHASE(0),
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.CLKFBOUT_PHASE(0),
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.DIVCLK_DIVIDE(3),
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.DIVCLK_DIVIDE(3),
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.REF_JITTER1(0.010),
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.REF_JITTER1(0.010),
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.CLKIN1_PERIOD(8.0),
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.CLKIN1_PERIOD(3.333),
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.STARTUP_WAIT("FALSE"),
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.STARTUP_WAIT("FALSE"),
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.CLKOUT4_CASCADE("FALSE")
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.CLKOUT4_CASCADE("FALSE")
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)
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)
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@ -126,7 +126,7 @@ MMCME3_BASE #(
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.CLKFBOUT_PHASE(0),
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.CLKFBOUT_PHASE(0),
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.DIVCLK_DIVIDE(1),
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.DIVCLK_DIVIDE(1),
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.REF_JITTER1(0.010),
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.REF_JITTER1(0.010),
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.CLKIN1_PERIOD(8.0),
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.CLKIN1_PERIOD(10.0),
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.STARTUP_WAIT("FALSE"),
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.STARTUP_WAIT("FALSE"),
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.CLKOUT4_CASCADE("FALSE")
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.CLKOUT4_CASCADE("FALSE")
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)
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)
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