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https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-28 07:03:08 +08:00
Be more pythonic
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parent
c5837daa2f
commit
2ebffeb223
@ -261,7 +261,7 @@ class AXIStreamSource(object):
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return len(self.queue)
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def empty(self):
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return self.count() == 0
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return not self.queue
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def create_logic(self,
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clk,
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@ -376,12 +376,12 @@ class AXIStreamSink(object):
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self.read_queue = []
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def recv(self):
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if len(self.queue) > 0:
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if self.queue:
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return self.queue.pop(0)
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return None
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def read(self, count=-1):
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while len(self.queue) > 0:
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while self.queue:
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self.read_queue.extend(self.queue.pop(0).data)
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if count < 0:
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count = len(self.read_queue)
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@ -393,7 +393,7 @@ class AXIStreamSink(object):
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return len(self.queue)
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def empty(self):
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return self.count() == 0
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return not self.queue
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def create_logic(self,
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clk,
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