mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-28 07:03:08 +08:00
Convert async fifo to common reset
This commit is contained in:
Alex Forencich
parent
ca11618e6d
commit
30a35c3d73
@ -35,11 +35,15 @@ module axis_async_fifo #
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parameter DATA_WIDTH = 8
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)
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(
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/*
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* Common asynchronous reset
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*/
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input wire async_rst,
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/*
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* AXI input
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*/
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input wire input_clk,
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input wire input_rst,
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input wire [DATA_WIDTH-1:0] input_axis_tdata,
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input wire input_axis_tvalid,
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output wire input_axis_tready,
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@ -50,7 +54,6 @@ module axis_async_fifo #
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* AXI output
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*/
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input wire output_clk,
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input wire output_rst,
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output wire [DATA_WIDTH-1:0] output_axis_tdata,
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output wire output_axis_tvalid,
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input wire output_axis_tready,
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@ -99,8 +102,8 @@ assign input_axis_tready = ~full;
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assign output_axis_tvalid = output_axis_tvalid_reg;
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// reset synchronization
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always @(posedge input_clk or posedge input_rst or posedge output_rst) begin
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if (input_rst | output_rst) begin
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always @(posedge input_clk or posedge async_rst) begin
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if (async_rst) begin
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input_rst_sync1 <= 1;
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input_rst_sync2 <= 1;
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end else begin
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@ -109,8 +112,8 @@ always @(posedge input_clk or posedge input_rst or posedge output_rst) begin
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end
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end
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always @(posedge output_clk or posedge input_rst or posedge output_rst) begin
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if (input_rst | output_rst) begin
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always @(posedge output_clk or posedge async_rst) begin
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if (async_rst) begin
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output_rst_sync1 <= 1;
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output_rst_sync2 <= 1;
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end else begin
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@ -36,11 +36,15 @@ module axis_async_fifo_64 #
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parameter KEEP_WIDTH = (DATA_WIDTH/8)
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)
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(
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/*
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* Common asynchronous reset
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*/
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input wire async_rst,
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/*
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* AXI input
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*/
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input wire input_clk,
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input wire input_rst,
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input wire [DATA_WIDTH-1:0] input_axis_tdata,
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input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
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input wire input_axis_tvalid,
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@ -52,7 +56,6 @@ module axis_async_fifo_64 #
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* AXI output
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*/
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input wire output_clk,
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input wire output_rst,
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output wire [DATA_WIDTH-1:0] output_axis_tdata,
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output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
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output wire output_axis_tvalid,
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@ -102,8 +105,8 @@ assign input_axis_tready = ~full;
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assign output_axis_tvalid = output_axis_tvalid_reg;
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// reset synchronization
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always @(posedge input_clk or posedge input_rst or posedge output_rst) begin
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if (input_rst | output_rst) begin
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always @(posedge input_clk or posedge async_rst) begin
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if (async_rst) begin
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input_rst_sync1 <= 1;
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input_rst_sync2 <= 1;
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end else begin
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@ -112,8 +115,8 @@ always @(posedge input_clk or posedge input_rst or posedge output_rst) begin
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end
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end
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always @(posedge output_clk or posedge input_rst or posedge output_rst) begin
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if (input_rst | output_rst) begin
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always @(posedge output_clk or posedge async_rst) begin
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if (async_rst) begin
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output_rst_sync1 <= 1;
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output_rst_sync2 <= 1;
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end else begin
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@ -36,11 +36,15 @@ module axis_async_frame_fifo #
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parameter DROP_WHEN_FULL = 0
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)
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(
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/*
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* Common asynchronous reset
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*/
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input wire async_rst,
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/*
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* AXI input
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*/
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input wire input_clk,
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input wire input_rst,
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input wire [DATA_WIDTH-1:0] input_axis_tdata,
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input wire input_axis_tvalid,
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output wire input_axis_tready,
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@ -51,7 +55,6 @@ module axis_async_frame_fifo #
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* AXI output
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*/
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input wire output_clk,
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input wire output_rst,
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output wire [DATA_WIDTH-1:0] output_axis_tdata,
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output wire output_axis_tvalid,
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input wire output_axis_tready,
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@ -119,8 +122,8 @@ assign bad_frame = bad_frame_reg;
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assign good_frame = good_frame_reg;
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// reset synchronization
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always @(posedge input_clk or posedge input_rst or posedge output_rst) begin
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if (input_rst | output_rst) begin
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always @(posedge input_clk or posedge async_rst) begin
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if (async_rst) begin
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input_rst_sync1 <= 1;
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input_rst_sync2 <= 1;
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end else begin
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@ -129,8 +132,8 @@ always @(posedge input_clk or posedge input_rst or posedge output_rst) begin
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end
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end
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always @(posedge output_clk or posedge input_rst or posedge output_rst) begin
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if (input_rst | output_rst) begin
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always @(posedge output_clk or posedge async_rst) begin
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if (async_rst) begin
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output_rst_sync1 <= 1;
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output_rst_sync2 <= 1;
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end else begin
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@ -37,11 +37,15 @@ module axis_async_frame_fifo_64 #
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parameter DROP_WHEN_FULL = 0
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)
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(
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/*
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* Common asynchronous reset
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*/
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input wire async_rst,
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/*
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* AXI input
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*/
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input wire input_clk,
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input wire input_rst,
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input wire [DATA_WIDTH-1:0] input_axis_tdata,
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input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
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input wire input_axis_tvalid,
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@ -53,7 +57,6 @@ module axis_async_frame_fifo_64 #
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* AXI output
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*/
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input wire output_clk,
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input wire output_rst,
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output wire [DATA_WIDTH-1:0] output_axis_tdata,
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output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
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output wire output_axis_tvalid,
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@ -122,8 +125,8 @@ assign bad_frame = bad_frame_reg;
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assign good_frame = good_frame_reg;
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// reset synchronization
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always @(posedge input_clk or posedge input_rst or posedge output_rst) begin
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if (input_rst | output_rst) begin
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always @(posedge input_clk or posedge async_rst) begin
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if (async_rst) begin
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input_rst_sync1 <= 1;
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input_rst_sync2 <= 1;
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end else begin
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@ -132,8 +135,8 @@ always @(posedge input_clk or posedge input_rst or posedge output_rst) begin
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end
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end
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always @(posedge output_clk or posedge input_rst or posedge output_rst) begin
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if (input_rst | output_rst) begin
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always @(posedge output_clk or posedge async_rst) begin
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if (async_rst) begin
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output_rst_sync1 <= 1;
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output_rst_sync2 <= 1;
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end else begin
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@ -44,10 +44,9 @@ src = ' '.join(srcs)
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build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
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def dut_axis_async_fifo(input_clk,
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input_rst,
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def dut_axis_async_fifo(async_rst,
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input_clk,
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output_clk,
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output_rst,
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current_test,
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input_axis_tdata,
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@ -65,10 +64,9 @@ def dut_axis_async_fifo(input_clk,
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if os.system(build_cmd):
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raise Exception("Error running build command")
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return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
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async_rst=async_rst,
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input_clk=input_clk,
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input_rst=input_rst,
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output_clk=output_clk,
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output_rst=output_rst,
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current_test=current_test,
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input_axis_tdata=input_axis_tdata,
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@ -86,10 +84,9 @@ def dut_axis_async_fifo(input_clk,
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def bench():
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# Inputs
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async_rst = Signal(bool(0))
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input_clk = Signal(bool(0))
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input_rst = Signal(bool(0))
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output_clk = Signal(bool(0))
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output_rst = Signal(bool(0))
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current_test = Signal(intbv(0)[8:])
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input_axis_tdata = Signal(intbv(0)[8:])
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@ -112,7 +109,7 @@ def bench():
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sink_pause = Signal(bool(0))
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source = axis_ep.AXIStreamSource(input_clk,
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input_rst,
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async_rst,
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tdata=input_axis_tdata,
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tvalid=input_axis_tvalid,
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tready=input_axis_tready,
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@ -123,7 +120,7 @@ def bench():
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name='source')
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sink = axis_ep.AXIStreamSink(output_clk,
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output_rst,
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async_rst,
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tdata=output_axis_tdata,
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tvalid=output_axis_tvalid,
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tready=output_axis_tready,
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@ -134,10 +131,9 @@ def bench():
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name='sink')
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# DUT
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dut = dut_axis_async_fifo(input_clk,
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input_rst,
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dut = dut_axis_async_fifo(async_rst,
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input_clk,
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output_clk,
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output_rst,
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current_test,
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input_axis_tdata,
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@ -164,13 +160,11 @@ def bench():
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def check():
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yield delay(100)
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yield input_clk.posedge
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input_rst.next = 1
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output_rst.next = 1
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async_rst.next = 1
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yield input_clk.posedge
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yield input_clk.posedge
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yield input_clk.posedge
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input_rst.next = 0
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output_rst.next = 0
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async_rst.next = 0
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yield input_clk.posedge
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yield delay(100)
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yield input_clk.posedge
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@ -428,7 +422,7 @@ def bench():
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yield delay(100)
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yield input_clk.posedge
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print("test 9: initial sink pause, input reset")
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print("test 9: initial sink pause, assert reset")
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current_test.next = 9
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test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
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@ -440,38 +434,9 @@ def bench():
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yield input_clk.posedge
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yield input_clk.posedge
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input_rst.next = 1
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async_rst.next = 1
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yield input_clk.posedge
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input_rst.next = 0
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sink_pause.next = 0
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yield delay(100)
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yield output_clk.posedge
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yield output_clk.posedge
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yield output_clk.posedge
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assert sink_queue.empty()
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yield delay(100)
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yield input_clk.posedge
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print("test 10: initial sink pause, output reset")
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current_test.next = 10
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test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
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sink_pause.next = 1
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source_queue.put(test_frame)
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yield input_clk.posedge
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yield input_clk.posedge
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yield input_clk.posedge
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yield input_clk.posedge
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output_rst.next = 1
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yield output_clk.posedge
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output_rst.next = 0
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async_rst.next = 0
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sink_pause.next = 0
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@ -29,10 +29,9 @@ THE SOFTWARE.
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module test_axis_async_fifo;
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// Inputs
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reg async_rst = 0;
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reg input_clk = 0;
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reg input_rst = 0;
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reg output_clk = 0;
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reg output_rst = 0;
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reg [7:0] current_test = 0;
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reg [7:0] input_axis_tdata = 0;
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@ -50,10 +49,9 @@ wire output_axis_tuser;
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initial begin
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// myhdl integration
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$from_myhdl(input_clk,
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input_rst,
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$from_myhdl(async_rst,
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input_clk,
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output_clk,
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output_rst,
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current_test,
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input_axis_tdata,
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input_axis_tvalid,
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@ -76,9 +74,10 @@ axis_async_fifo #(
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.DATA_WIDTH(8)
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)
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UUT (
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// Common reset
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.async_rst(async_rst),
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// AXI input
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.input_clk(input_clk),
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.input_rst(input_rst),
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.input_axis_tdata(input_axis_tdata),
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.input_axis_tvalid(input_axis_tvalid),
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.input_axis_tready(input_axis_tready),
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@ -86,7 +85,6 @@ UUT (
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.input_axis_tuser(input_axis_tuser),
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// AXI output
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.output_clk(output_clk),
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.output_rst(output_rst),
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.output_axis_tdata(output_axis_tdata),
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.output_axis_tvalid(output_axis_tvalid),
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.output_axis_tready(output_axis_tready),
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@ -44,10 +44,9 @@ src = ' '.join(srcs)
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build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
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def dut_axis_async_fifo_64(input_clk,
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input_rst,
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def dut_axis_async_fifo_64(async_rst,
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input_clk,
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output_clk,
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output_rst,
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current_test,
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input_axis_tdata,
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@ -67,10 +66,9 @@ def dut_axis_async_fifo_64(input_clk,
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if os.system(build_cmd):
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raise Exception("Error running build command")
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return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
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async_rst=async_rst,
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input_clk=input_clk,
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input_rst=input_rst,
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output_clk=output_clk,
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output_rst=output_rst,
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current_test=current_test,
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input_axis_tdata=input_axis_tdata,
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@ -90,10 +88,9 @@ def dut_axis_async_fifo_64(input_clk,
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def bench():
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# Inputs
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async_rst = Signal(bool(0))
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input_clk = Signal(bool(0))
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input_rst = Signal(bool(0))
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output_clk = Signal(bool(0))
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output_rst = Signal(bool(0))
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current_test = Signal(intbv(0)[8:])
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input_axis_tdata = Signal(intbv(0)[64:])
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@ -118,7 +115,7 @@ def bench():
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sink_pause = Signal(bool(0))
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source = axis_ep.AXIStreamSource(input_clk,
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input_rst,
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async_rst,
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tdata=input_axis_tdata,
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tkeep=input_axis_tkeep,
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tvalid=input_axis_tvalid,
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@ -130,7 +127,7 @@ def bench():
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name='source')
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sink = axis_ep.AXIStreamSink(output_clk,
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output_rst,
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async_rst,
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tdata=output_axis_tdata,
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tkeep=output_axis_tkeep,
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tvalid=output_axis_tvalid,
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@ -142,10 +139,9 @@ def bench():
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name='sink')
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# DUT
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dut = dut_axis_async_fifo_64(input_clk,
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input_rst,
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dut = dut_axis_async_fifo_64(async_rst,
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input_clk,
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output_clk,
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output_rst,
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current_test,
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input_axis_tdata,
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@ -174,13 +170,11 @@ def bench():
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def check():
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yield delay(100)
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yield input_clk.posedge
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input_rst.next = 1
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output_rst.next = 1
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async_rst.next = 1
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yield input_clk.posedge
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yield input_clk.posedge
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yield input_clk.posedge
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input_rst.next = 0
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output_rst.next = 0
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async_rst.next = 0
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yield input_clk.posedge
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yield delay(100)
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yield input_clk.posedge
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@ -438,7 +432,7 @@ def bench():
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yield delay(100)
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yield input_clk.posedge
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print("test 9: initial sink pause, input reset")
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print("test 9: initial sink pause, assert reset")
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current_test.next = 9
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test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
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@ -450,38 +444,9 @@ def bench():
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yield input_clk.posedge
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yield input_clk.posedge
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input_rst.next = 1
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async_rst.next = 1
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yield input_clk.posedge
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input_rst.next = 0
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sink_pause.next = 0
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yield delay(100)
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yield output_clk.posedge
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yield output_clk.posedge
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yield output_clk.posedge
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assert sink_queue.empty()
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|
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yield delay(100)
|
||||
|
||||
yield input_clk.posedge
|
||||
print("test 10: initial sink pause, output reset")
|
||||
current_test.next = 10
|
||||
|
||||
test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
|
||||
|
||||
sink_pause.next = 1
|
||||
source_queue.put(test_frame)
|
||||
yield input_clk.posedge
|
||||
yield input_clk.posedge
|
||||
yield input_clk.posedge
|
||||
yield input_clk.posedge
|
||||
|
||||
output_rst.next = 1
|
||||
yield output_clk.posedge
|
||||
output_rst.next = 0
|
||||
async_rst.next = 0
|
||||
|
||||
sink_pause.next = 0
|
||||
|
||||
|
||||
@ -29,10 +29,9 @@ THE SOFTWARE.
|
||||
module test_axis_async_fifo_64;
|
||||
|
||||
// Inputs
|
||||
reg async_rst = 0;
|
||||
reg input_clk = 0;
|
||||
reg input_rst = 0;
|
||||
reg output_clk = 0;
|
||||
reg output_rst = 0;
|
||||
reg [7:0] current_test = 0;
|
||||
|
||||
reg [63:0] input_axis_tdata = 0;
|
||||
@ -52,10 +51,9 @@ wire output_axis_tuser;
|
||||
|
||||
initial begin
|
||||
// myhdl integration
|
||||
$from_myhdl(input_clk,
|
||||
input_rst,
|
||||
$from_myhdl(async_rst,
|
||||
input_clk,
|
||||
output_clk,
|
||||
output_rst,
|
||||
current_test,
|
||||
input_axis_tdata,
|
||||
input_axis_tkeep,
|
||||
@ -80,9 +78,10 @@ axis_async_fifo_64 #(
|
||||
.DATA_WIDTH(64)
|
||||
)
|
||||
UUT (
|
||||
// Common reset
|
||||
.async_rst(async_rst),
|
||||
// AXI input
|
||||
.input_clk(input_clk),
|
||||
.input_rst(input_rst),
|
||||
.input_axis_tdata(input_axis_tdata),
|
||||
.input_axis_tkeep(input_axis_tkeep),
|
||||
.input_axis_tvalid(input_axis_tvalid),
|
||||
@ -91,7 +90,6 @@ UUT (
|
||||
.input_axis_tuser(input_axis_tuser),
|
||||
// AXI output
|
||||
.output_clk(output_clk),
|
||||
.output_rst(output_rst),
|
||||
.output_axis_tdata(output_axis_tdata),
|
||||
.output_axis_tkeep(output_axis_tkeep),
|
||||
.output_axis_tvalid(output_axis_tvalid),
|
||||
|
||||
@ -44,10 +44,9 @@ src = ' '.join(srcs)
|
||||
|
||||
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
|
||||
|
||||
def dut_axis_async_frame_fifo(input_clk,
|
||||
input_rst,
|
||||
def dut_axis_async_frame_fifo(async_rst,
|
||||
input_clk,
|
||||
output_clk,
|
||||
output_rst,
|
||||
current_test,
|
||||
|
||||
input_axis_tdata,
|
||||
@ -68,10 +67,9 @@ def dut_axis_async_frame_fifo(input_clk,
|
||||
if os.system(build_cmd):
|
||||
raise Exception("Error running build command")
|
||||
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
|
||||
async_rst=async_rst,
|
||||
input_clk=input_clk,
|
||||
input_rst=input_rst,
|
||||
output_clk=output_clk,
|
||||
output_rst=output_rst,
|
||||
current_test=current_test,
|
||||
|
||||
input_axis_tdata=input_axis_tdata,
|
||||
@ -92,10 +90,9 @@ def dut_axis_async_frame_fifo(input_clk,
|
||||
def bench():
|
||||
|
||||
# Inputs
|
||||
async_rst = Signal(bool(0))
|
||||
input_clk = Signal(bool(0))
|
||||
input_rst = Signal(bool(0))
|
||||
output_clk = Signal(bool(0))
|
||||
output_rst = Signal(bool(0))
|
||||
current_test = Signal(intbv(0)[8:])
|
||||
|
||||
input_axis_tdata = Signal(intbv(0)[8:])
|
||||
@ -120,7 +117,7 @@ def bench():
|
||||
sink_pause = Signal(bool(0))
|
||||
|
||||
source = axis_ep.AXIStreamSource(input_clk,
|
||||
input_rst,
|
||||
async_rst,
|
||||
tdata=input_axis_tdata,
|
||||
tvalid=input_axis_tvalid,
|
||||
tready=input_axis_tready,
|
||||
@ -131,7 +128,7 @@ def bench():
|
||||
name='source')
|
||||
|
||||
sink = axis_ep.AXIStreamSink(output_clk,
|
||||
output_rst,
|
||||
async_rst,
|
||||
tdata=output_axis_tdata,
|
||||
tvalid=output_axis_tvalid,
|
||||
tready=output_axis_tready,
|
||||
@ -141,10 +138,9 @@ def bench():
|
||||
name='sink')
|
||||
|
||||
# DUT
|
||||
dut = dut_axis_async_frame_fifo(input_clk,
|
||||
input_rst,
|
||||
dut = dut_axis_async_frame_fifo(async_rst,
|
||||
input_clk,
|
||||
output_clk,
|
||||
output_rst,
|
||||
current_test,
|
||||
|
||||
input_axis_tdata,
|
||||
@ -187,13 +183,11 @@ def bench():
|
||||
def check():
|
||||
yield delay(100)
|
||||
yield input_clk.posedge
|
||||
input_rst.next = 1
|
||||
output_rst.next = 1
|
||||
async_rst.next = 1
|
||||
yield input_clk.posedge
|
||||
yield input_clk.posedge
|
||||
yield input_clk.posedge
|
||||
input_rst.next = 0
|
||||
output_rst.next = 0
|
||||
async_rst.next = 0
|
||||
yield input_clk.posedge
|
||||
yield delay(100)
|
||||
yield input_clk.posedge
|
||||
@ -537,7 +531,7 @@ def bench():
|
||||
yield delay(100)
|
||||
|
||||
yield input_clk.posedge
|
||||
print("test 10: initial sink pause, input reset")
|
||||
print("test 10: initial sink pause, assert reset")
|
||||
current_test.next = 10
|
||||
|
||||
test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
|
||||
@ -549,38 +543,9 @@ def bench():
|
||||
yield input_clk.posedge
|
||||
yield input_clk.posedge
|
||||
|
||||
input_rst.next = 1
|
||||
async_rst.next = 1
|
||||
yield input_clk.posedge
|
||||
input_rst.next = 0
|
||||
|
||||
sink_pause.next = 0
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield output_clk.posedge
|
||||
yield output_clk.posedge
|
||||
yield output_clk.posedge
|
||||
|
||||
assert sink_queue.empty()
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield input_clk.posedge
|
||||
print("test 11: initial sink pause, output reset")
|
||||
current_test.next = 11
|
||||
|
||||
test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
|
||||
|
||||
sink_pause.next = 1
|
||||
source_queue.put(test_frame)
|
||||
yield input_clk.posedge
|
||||
yield input_clk.posedge
|
||||
yield input_clk.posedge
|
||||
yield input_clk.posedge
|
||||
|
||||
output_rst.next = 1
|
||||
yield output_clk.posedge
|
||||
output_rst.next = 0
|
||||
async_rst.next = 0
|
||||
|
||||
sink_pause.next = 0
|
||||
|
||||
|
||||
@ -29,10 +29,9 @@ THE SOFTWARE.
|
||||
module test_axis_async_frame_fifo;
|
||||
|
||||
// Inputs
|
||||
reg async_rst = 0;
|
||||
reg input_clk = 0;
|
||||
reg input_rst = 0;
|
||||
reg output_clk = 0;
|
||||
reg output_rst = 0;
|
||||
reg [7:0] current_test = 0;
|
||||
|
||||
reg [7:0] input_axis_tdata = 0;
|
||||
@ -52,10 +51,9 @@ wire good_frame;
|
||||
|
||||
initial begin
|
||||
// myhdl integration
|
||||
$from_myhdl(input_clk,
|
||||
input_rst,
|
||||
$from_myhdl(async_rst,
|
||||
input_clk,
|
||||
output_clk,
|
||||
output_rst,
|
||||
current_test,
|
||||
input_axis_tdata,
|
||||
input_axis_tvalid,
|
||||
@ -81,9 +79,10 @@ axis_async_frame_fifo #(
|
||||
.DROP_WHEN_FULL(0)
|
||||
)
|
||||
UUT (
|
||||
// Common reset
|
||||
.async_rst(async_rst),
|
||||
// AXI input
|
||||
.input_clk(input_clk),
|
||||
.input_rst(input_rst),
|
||||
.input_axis_tdata(input_axis_tdata),
|
||||
.input_axis_tvalid(input_axis_tvalid),
|
||||
.input_axis_tready(input_axis_tready),
|
||||
@ -91,7 +90,6 @@ UUT (
|
||||
.input_axis_tuser(input_axis_tuser),
|
||||
// AXI output
|
||||
.output_clk(output_clk),
|
||||
.output_rst(output_rst),
|
||||
.output_axis_tdata(output_axis_tdata),
|
||||
.output_axis_tvalid(output_axis_tvalid),
|
||||
.output_axis_tready(output_axis_tready),
|
||||
|
||||
@ -44,10 +44,9 @@ src = ' '.join(srcs)
|
||||
|
||||
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
|
||||
|
||||
def dut_axis_async_frame_fifo_64(input_clk,
|
||||
input_rst,
|
||||
def dut_axis_async_frame_fifo_64(async_rst,
|
||||
input_clk,
|
||||
output_clk,
|
||||
output_rst,
|
||||
current_test,
|
||||
|
||||
input_axis_tdata,
|
||||
@ -70,10 +69,9 @@ def dut_axis_async_frame_fifo_64(input_clk,
|
||||
if os.system(build_cmd):
|
||||
raise Exception("Error running build command")
|
||||
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
|
||||
async_rst=async_rst,
|
||||
input_clk=input_clk,
|
||||
input_rst=input_rst,
|
||||
output_clk=output_clk,
|
||||
output_rst=output_rst,
|
||||
current_test=current_test,
|
||||
|
||||
input_axis_tdata=input_axis_tdata,
|
||||
@ -96,10 +94,9 @@ def dut_axis_async_frame_fifo_64(input_clk,
|
||||
def bench():
|
||||
|
||||
# Inputs
|
||||
async_rst = Signal(bool(0))
|
||||
input_clk = Signal(bool(0))
|
||||
input_rst = Signal(bool(0))
|
||||
output_clk = Signal(bool(0))
|
||||
output_rst = Signal(bool(0))
|
||||
current_test = Signal(intbv(0)[8:])
|
||||
|
||||
input_axis_tdata = Signal(intbv(0)[64:])
|
||||
@ -126,7 +123,7 @@ def bench():
|
||||
sink_pause = Signal(bool(0))
|
||||
|
||||
source = axis_ep.AXIStreamSource(input_clk,
|
||||
input_rst,
|
||||
async_rst,
|
||||
tdata=input_axis_tdata,
|
||||
tkeep=input_axis_tkeep,
|
||||
tvalid=input_axis_tvalid,
|
||||
@ -138,7 +135,7 @@ def bench():
|
||||
name='source')
|
||||
|
||||
sink = axis_ep.AXIStreamSink(output_clk,
|
||||
output_rst,
|
||||
async_rst,
|
||||
tdata=output_axis_tdata,
|
||||
tkeep=output_axis_tkeep,
|
||||
tvalid=output_axis_tvalid,
|
||||
@ -149,10 +146,9 @@ def bench():
|
||||
name='sink')
|
||||
|
||||
# DUT
|
||||
dut = dut_axis_async_frame_fifo_64(input_clk,
|
||||
input_rst,
|
||||
dut = dut_axis_async_frame_fifo_64(async_rst,
|
||||
input_clk,
|
||||
output_clk,
|
||||
output_rst,
|
||||
current_test,
|
||||
|
||||
input_axis_tdata,
|
||||
@ -197,13 +193,11 @@ def bench():
|
||||
def check():
|
||||
yield delay(100)
|
||||
yield input_clk.posedge
|
||||
input_rst.next = 1
|
||||
output_rst.next = 1
|
||||
async_rst.next = 1
|
||||
yield input_clk.posedge
|
||||
yield input_clk.posedge
|
||||
yield input_clk.posedge
|
||||
input_rst.next = 0
|
||||
output_rst.next = 0
|
||||
async_rst.next = 0
|
||||
yield input_clk.posedge
|
||||
yield delay(100)
|
||||
yield input_clk.posedge
|
||||
@ -547,7 +541,7 @@ def bench():
|
||||
yield delay(100)
|
||||
|
||||
yield input_clk.posedge
|
||||
print("test 10: initial sink pause, input reset")
|
||||
print("test 10: initial sink pause, assert reset")
|
||||
current_test.next = 10
|
||||
|
||||
test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
|
||||
@ -559,38 +553,9 @@ def bench():
|
||||
yield input_clk.posedge
|
||||
yield input_clk.posedge
|
||||
|
||||
input_rst.next = 1
|
||||
async_rst.next = 1
|
||||
yield input_clk.posedge
|
||||
input_rst.next = 0
|
||||
|
||||
sink_pause.next = 0
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield output_clk.posedge
|
||||
yield output_clk.posedge
|
||||
yield output_clk.posedge
|
||||
|
||||
assert sink_queue.empty()
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield input_clk.posedge
|
||||
print("test 11: initial sink pause, output reset")
|
||||
current_test.next = 11
|
||||
|
||||
test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
|
||||
|
||||
sink_pause.next = 1
|
||||
source_queue.put(test_frame)
|
||||
yield input_clk.posedge
|
||||
yield input_clk.posedge
|
||||
yield input_clk.posedge
|
||||
yield input_clk.posedge
|
||||
|
||||
output_rst.next = 1
|
||||
yield output_clk.posedge
|
||||
output_rst.next = 0
|
||||
async_rst.next = 0
|
||||
|
||||
sink_pause.next = 0
|
||||
|
||||
|
||||
@ -29,10 +29,9 @@ THE SOFTWARE.
|
||||
module test_axis_async_frame_fifo_64;
|
||||
|
||||
// Inputs
|
||||
reg async_rst = 0;
|
||||
reg input_clk = 0;
|
||||
reg input_rst = 0;
|
||||
reg output_clk = 0;
|
||||
reg output_rst = 0;
|
||||
reg [7:0] current_test = 0;
|
||||
|
||||
reg [63:0] input_axis_tdata = 0;
|
||||
@ -54,10 +53,9 @@ wire good_frame;
|
||||
|
||||
initial begin
|
||||
// myhdl integration
|
||||
$from_myhdl(input_clk,
|
||||
input_rst,
|
||||
$from_myhdl(async_rst,
|
||||
input_clk,
|
||||
output_clk,
|
||||
output_rst,
|
||||
current_test,
|
||||
input_axis_tdata,
|
||||
input_axis_tkeep,
|
||||
@ -85,9 +83,10 @@ axis_async_frame_fifo_64 #(
|
||||
.DROP_WHEN_FULL(0)
|
||||
)
|
||||
UUT (
|
||||
// Common reset
|
||||
.async_rst(async_rst),
|
||||
// AXI input
|
||||
.input_clk(input_clk),
|
||||
.input_rst(input_rst),
|
||||
.input_axis_tdata(input_axis_tdata),
|
||||
.input_axis_tkeep(input_axis_tkeep),
|
||||
.input_axis_tvalid(input_axis_tvalid),
|
||||
@ -96,7 +95,6 @@ UUT (
|
||||
.input_axis_tuser(input_axis_tuser),
|
||||
// AXI output
|
||||
.output_clk(output_clk),
|
||||
.output_rst(output_rst),
|
||||
.output_axis_tdata(output_axis_tdata),
|
||||
.output_axis_tkeep(output_axis_tkeep),
|
||||
.output_axis_tvalid(output_axis_tvalid),
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user