diff --git a/rtl/axis_async_fifo.v b/rtl/axis_async_fifo.v index 63ae2816..4dcb2269 100644 --- a/rtl/axis_async_fifo.v +++ b/rtl/axis_async_fifo.v @@ -35,11 +35,15 @@ module axis_async_fifo # parameter DATA_WIDTH = 8 ) ( + /* + * Common asynchronous reset + */ + input wire async_rst, + /* * AXI input */ input wire input_clk, - input wire input_rst, input wire [DATA_WIDTH-1:0] input_axis_tdata, input wire input_axis_tvalid, output wire input_axis_tready, @@ -50,7 +54,6 @@ module axis_async_fifo # * AXI output */ input wire output_clk, - input wire output_rst, output wire [DATA_WIDTH-1:0] output_axis_tdata, output wire output_axis_tvalid, input wire output_axis_tready, @@ -99,8 +102,8 @@ assign input_axis_tready = ~full; assign output_axis_tvalid = output_axis_tvalid_reg; // reset synchronization -always @(posedge input_clk or posedge input_rst or posedge output_rst) begin - if (input_rst | output_rst) begin +always @(posedge input_clk or posedge async_rst) begin + if (async_rst) begin input_rst_sync1 <= 1; input_rst_sync2 <= 1; end else begin @@ -109,8 +112,8 @@ always @(posedge input_clk or posedge input_rst or posedge output_rst) begin end end -always @(posedge output_clk or posedge input_rst or posedge output_rst) begin - if (input_rst | output_rst) begin +always @(posedge output_clk or posedge async_rst) begin + if (async_rst) begin output_rst_sync1 <= 1; output_rst_sync2 <= 1; end else begin diff --git a/rtl/axis_async_fifo_64.v b/rtl/axis_async_fifo_64.v index 9e3dc962..7303b87f 100644 --- a/rtl/axis_async_fifo_64.v +++ b/rtl/axis_async_fifo_64.v @@ -36,11 +36,15 @@ module axis_async_fifo_64 # parameter KEEP_WIDTH = (DATA_WIDTH/8) ) ( + /* + * Common asynchronous reset + */ + input wire async_rst, + /* * AXI input */ input wire input_clk, - input wire input_rst, input wire [DATA_WIDTH-1:0] input_axis_tdata, input wire [KEEP_WIDTH-1:0] input_axis_tkeep, input wire input_axis_tvalid, @@ -52,7 +56,6 @@ module axis_async_fifo_64 # * AXI output */ input wire output_clk, - input wire output_rst, output wire [DATA_WIDTH-1:0] output_axis_tdata, output wire [KEEP_WIDTH-1:0] output_axis_tkeep, output wire output_axis_tvalid, @@ -102,8 +105,8 @@ assign input_axis_tready = ~full; assign output_axis_tvalid = output_axis_tvalid_reg; // reset synchronization -always @(posedge input_clk or posedge input_rst or posedge output_rst) begin - if (input_rst | output_rst) begin +always @(posedge input_clk or posedge async_rst) begin + if (async_rst) begin input_rst_sync1 <= 1; input_rst_sync2 <= 1; end else begin @@ -112,8 +115,8 @@ always @(posedge input_clk or posedge input_rst or posedge output_rst) begin end end -always @(posedge output_clk or posedge input_rst or posedge output_rst) begin - if (input_rst | output_rst) begin +always @(posedge output_clk or posedge async_rst) begin + if (async_rst) begin output_rst_sync1 <= 1; output_rst_sync2 <= 1; end else begin diff --git a/rtl/axis_async_frame_fifo.v b/rtl/axis_async_frame_fifo.v index 8fdcbff8..e0e215ec 100644 --- a/rtl/axis_async_frame_fifo.v +++ b/rtl/axis_async_frame_fifo.v @@ -36,11 +36,15 @@ module axis_async_frame_fifo # parameter DROP_WHEN_FULL = 0 ) ( + /* + * Common asynchronous reset + */ + input wire async_rst, + /* * AXI input */ input wire input_clk, - input wire input_rst, input wire [DATA_WIDTH-1:0] input_axis_tdata, input wire input_axis_tvalid, output wire input_axis_tready, @@ -51,7 +55,6 @@ module axis_async_frame_fifo # * AXI output */ input wire output_clk, - input wire output_rst, output wire [DATA_WIDTH-1:0] output_axis_tdata, output wire output_axis_tvalid, input wire output_axis_tready, @@ -119,8 +122,8 @@ assign bad_frame = bad_frame_reg; assign good_frame = good_frame_reg; // reset synchronization -always @(posedge input_clk or posedge input_rst or posedge output_rst) begin - if (input_rst | output_rst) begin +always @(posedge input_clk or posedge async_rst) begin + if (async_rst) begin input_rst_sync1 <= 1; input_rst_sync2 <= 1; end else begin @@ -129,8 +132,8 @@ always @(posedge input_clk or posedge input_rst or posedge output_rst) begin end end -always @(posedge output_clk or posedge input_rst or posedge output_rst) begin - if (input_rst | output_rst) begin +always @(posedge output_clk or posedge async_rst) begin + if (async_rst) begin output_rst_sync1 <= 1; output_rst_sync2 <= 1; end else begin diff --git a/rtl/axis_async_frame_fifo_64.v b/rtl/axis_async_frame_fifo_64.v index 2a0d88d2..0847cd23 100644 --- a/rtl/axis_async_frame_fifo_64.v +++ b/rtl/axis_async_frame_fifo_64.v @@ -37,11 +37,15 @@ module axis_async_frame_fifo_64 # parameter DROP_WHEN_FULL = 0 ) ( + /* + * Common asynchronous reset + */ + input wire async_rst, + /* * AXI input */ input wire input_clk, - input wire input_rst, input wire [DATA_WIDTH-1:0] input_axis_tdata, input wire [KEEP_WIDTH-1:0] input_axis_tkeep, input wire input_axis_tvalid, @@ -53,7 +57,6 @@ module axis_async_frame_fifo_64 # * AXI output */ input wire output_clk, - input wire output_rst, output wire [DATA_WIDTH-1:0] output_axis_tdata, output wire [KEEP_WIDTH-1:0] output_axis_tkeep, output wire output_axis_tvalid, @@ -122,8 +125,8 @@ assign bad_frame = bad_frame_reg; assign good_frame = good_frame_reg; // reset synchronization -always @(posedge input_clk or posedge input_rst or posedge output_rst) begin - if (input_rst | output_rst) begin +always @(posedge input_clk or posedge async_rst) begin + if (async_rst) begin input_rst_sync1 <= 1; input_rst_sync2 <= 1; end else begin @@ -132,8 +135,8 @@ always @(posedge input_clk or posedge input_rst or posedge output_rst) begin end end -always @(posedge output_clk or posedge input_rst or posedge output_rst) begin - if (input_rst | output_rst) begin +always @(posedge output_clk or posedge async_rst) begin + if (async_rst) begin output_rst_sync1 <= 1; output_rst_sync2 <= 1; end else begin diff --git a/tb/test_axis_async_fifo.py b/tb/test_axis_async_fifo.py index 817887c1..28f759c5 100755 --- a/tb/test_axis_async_fifo.py +++ b/tb/test_axis_async_fifo.py @@ -44,10 +44,9 @@ src = ' '.join(srcs) build_cmd = "iverilog -o test_%s.vvp %s" % (module, src) -def dut_axis_async_fifo(input_clk, - input_rst, +def dut_axis_async_fifo(async_rst, + input_clk, output_clk, - output_rst, current_test, input_axis_tdata, @@ -65,10 +64,9 @@ def dut_axis_async_fifo(input_clk, if os.system(build_cmd): raise Exception("Error running build command") return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module, + async_rst=async_rst, input_clk=input_clk, - input_rst=input_rst, output_clk=output_clk, - output_rst=output_rst, current_test=current_test, input_axis_tdata=input_axis_tdata, @@ -86,10 +84,9 @@ def dut_axis_async_fifo(input_clk, def bench(): # Inputs + async_rst = Signal(bool(0)) input_clk = Signal(bool(0)) - input_rst = Signal(bool(0)) output_clk = Signal(bool(0)) - output_rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) input_axis_tdata = Signal(intbv(0)[8:]) @@ -112,7 +109,7 @@ def bench(): sink_pause = Signal(bool(0)) source = axis_ep.AXIStreamSource(input_clk, - input_rst, + async_rst, tdata=input_axis_tdata, tvalid=input_axis_tvalid, tready=input_axis_tready, @@ -123,7 +120,7 @@ def bench(): name='source') sink = axis_ep.AXIStreamSink(output_clk, - output_rst, + async_rst, tdata=output_axis_tdata, tvalid=output_axis_tvalid, tready=output_axis_tready, @@ -134,10 +131,9 @@ def bench(): name='sink') # DUT - dut = dut_axis_async_fifo(input_clk, - input_rst, + dut = dut_axis_async_fifo(async_rst, + input_clk, output_clk, - output_rst, current_test, input_axis_tdata, @@ -164,13 +160,11 @@ def bench(): def check(): yield delay(100) yield input_clk.posedge - input_rst.next = 1 - output_rst.next = 1 + async_rst.next = 1 yield input_clk.posedge yield input_clk.posedge yield input_clk.posedge - input_rst.next = 0 - output_rst.next = 0 + async_rst.next = 0 yield input_clk.posedge yield delay(100) yield input_clk.posedge @@ -428,7 +422,7 @@ def bench(): yield delay(100) yield input_clk.posedge - print("test 9: initial sink pause, input reset") + print("test 9: initial sink pause, assert reset") current_test.next = 9 test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03') @@ -440,38 +434,9 @@ def bench(): yield input_clk.posedge yield input_clk.posedge - input_rst.next = 1 + async_rst.next = 1 yield input_clk.posedge - input_rst.next = 0 - - sink_pause.next = 0 - - yield delay(100) - - yield output_clk.posedge - yield output_clk.posedge - yield output_clk.posedge - - assert sink_queue.empty() - - yield delay(100) - - yield input_clk.posedge - print("test 10: initial sink pause, output reset") - current_test.next = 10 - - test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03') - - sink_pause.next = 1 - source_queue.put(test_frame) - yield input_clk.posedge - yield input_clk.posedge - yield input_clk.posedge - yield input_clk.posedge - - output_rst.next = 1 - yield output_clk.posedge - output_rst.next = 0 + async_rst.next = 0 sink_pause.next = 0 diff --git a/tb/test_axis_async_fifo.v b/tb/test_axis_async_fifo.v index dbfbdd49..fe91682a 100644 --- a/tb/test_axis_async_fifo.v +++ b/tb/test_axis_async_fifo.v @@ -29,10 +29,9 @@ THE SOFTWARE. module test_axis_async_fifo; // Inputs +reg async_rst = 0; reg input_clk = 0; -reg input_rst = 0; reg output_clk = 0; -reg output_rst = 0; reg [7:0] current_test = 0; reg [7:0] input_axis_tdata = 0; @@ -50,10 +49,9 @@ wire output_axis_tuser; initial begin // myhdl integration - $from_myhdl(input_clk, - input_rst, + $from_myhdl(async_rst, + input_clk, output_clk, - output_rst, current_test, input_axis_tdata, input_axis_tvalid, @@ -76,9 +74,10 @@ axis_async_fifo #( .DATA_WIDTH(8) ) UUT ( + // Common reset + .async_rst(async_rst), // AXI input .input_clk(input_clk), - .input_rst(input_rst), .input_axis_tdata(input_axis_tdata), .input_axis_tvalid(input_axis_tvalid), .input_axis_tready(input_axis_tready), @@ -86,7 +85,6 @@ UUT ( .input_axis_tuser(input_axis_tuser), // AXI output .output_clk(output_clk), - .output_rst(output_rst), .output_axis_tdata(output_axis_tdata), .output_axis_tvalid(output_axis_tvalid), .output_axis_tready(output_axis_tready), diff --git a/tb/test_axis_async_fifo_64.py b/tb/test_axis_async_fifo_64.py index e72c4ebc..a973ecc8 100755 --- a/tb/test_axis_async_fifo_64.py +++ b/tb/test_axis_async_fifo_64.py @@ -44,10 +44,9 @@ src = ' '.join(srcs) build_cmd = "iverilog -o test_%s.vvp %s" % (module, src) -def dut_axis_async_fifo_64(input_clk, - input_rst, +def dut_axis_async_fifo_64(async_rst, + input_clk, output_clk, - output_rst, current_test, input_axis_tdata, @@ -67,10 +66,9 @@ def dut_axis_async_fifo_64(input_clk, if os.system(build_cmd): raise Exception("Error running build command") return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module, + async_rst=async_rst, input_clk=input_clk, - input_rst=input_rst, output_clk=output_clk, - output_rst=output_rst, current_test=current_test, input_axis_tdata=input_axis_tdata, @@ -90,10 +88,9 @@ def dut_axis_async_fifo_64(input_clk, def bench(): # Inputs + async_rst = Signal(bool(0)) input_clk = Signal(bool(0)) - input_rst = Signal(bool(0)) output_clk = Signal(bool(0)) - output_rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) input_axis_tdata = Signal(intbv(0)[64:]) @@ -118,7 +115,7 @@ def bench(): sink_pause = Signal(bool(0)) source = axis_ep.AXIStreamSource(input_clk, - input_rst, + async_rst, tdata=input_axis_tdata, tkeep=input_axis_tkeep, tvalid=input_axis_tvalid, @@ -130,7 +127,7 @@ def bench(): name='source') sink = axis_ep.AXIStreamSink(output_clk, - output_rst, + async_rst, tdata=output_axis_tdata, tkeep=output_axis_tkeep, tvalid=output_axis_tvalid, @@ -142,10 +139,9 @@ def bench(): name='sink') # DUT - dut = dut_axis_async_fifo_64(input_clk, - input_rst, + dut = dut_axis_async_fifo_64(async_rst, + input_clk, output_clk, - output_rst, current_test, input_axis_tdata, @@ -174,13 +170,11 @@ def bench(): def check(): yield delay(100) yield input_clk.posedge - input_rst.next = 1 - output_rst.next = 1 + async_rst.next = 1 yield input_clk.posedge yield input_clk.posedge yield input_clk.posedge - input_rst.next = 0 - output_rst.next = 0 + async_rst.next = 0 yield input_clk.posedge yield delay(100) yield input_clk.posedge @@ -438,7 +432,7 @@ def bench(): yield delay(100) yield input_clk.posedge - print("test 9: initial sink pause, input reset") + print("test 9: initial sink pause, assert reset") current_test.next = 9 test_frame = axis_ep.AXIStreamFrame(bytearray(range(24))) @@ -450,38 +444,9 @@ def bench(): yield input_clk.posedge yield input_clk.posedge - input_rst.next = 1 + async_rst.next = 1 yield input_clk.posedge - input_rst.next = 0 - - sink_pause.next = 0 - - yield delay(100) - - yield output_clk.posedge - yield output_clk.posedge - yield output_clk.posedge - - assert sink_queue.empty() - - yield delay(100) - - yield input_clk.posedge - print("test 10: initial sink pause, output reset") - current_test.next = 10 - - test_frame = axis_ep.AXIStreamFrame(bytearray(range(24))) - - sink_pause.next = 1 - source_queue.put(test_frame) - yield input_clk.posedge - yield input_clk.posedge - yield input_clk.posedge - yield input_clk.posedge - - output_rst.next = 1 - yield output_clk.posedge - output_rst.next = 0 + async_rst.next = 0 sink_pause.next = 0 diff --git a/tb/test_axis_async_fifo_64.v b/tb/test_axis_async_fifo_64.v index 6741debe..bd49f80f 100644 --- a/tb/test_axis_async_fifo_64.v +++ b/tb/test_axis_async_fifo_64.v @@ -29,10 +29,9 @@ THE SOFTWARE. module test_axis_async_fifo_64; // Inputs +reg async_rst = 0; reg input_clk = 0; -reg input_rst = 0; reg output_clk = 0; -reg output_rst = 0; reg [7:0] current_test = 0; reg [63:0] input_axis_tdata = 0; @@ -52,10 +51,9 @@ wire output_axis_tuser; initial begin // myhdl integration - $from_myhdl(input_clk, - input_rst, + $from_myhdl(async_rst, + input_clk, output_clk, - output_rst, current_test, input_axis_tdata, input_axis_tkeep, @@ -80,9 +78,10 @@ axis_async_fifo_64 #( .DATA_WIDTH(64) ) UUT ( + // Common reset + .async_rst(async_rst), // AXI input .input_clk(input_clk), - .input_rst(input_rst), .input_axis_tdata(input_axis_tdata), .input_axis_tkeep(input_axis_tkeep), .input_axis_tvalid(input_axis_tvalid), @@ -91,7 +90,6 @@ UUT ( .input_axis_tuser(input_axis_tuser), // AXI output .output_clk(output_clk), - .output_rst(output_rst), .output_axis_tdata(output_axis_tdata), .output_axis_tkeep(output_axis_tkeep), .output_axis_tvalid(output_axis_tvalid), diff --git a/tb/test_axis_async_frame_fifo.py b/tb/test_axis_async_frame_fifo.py index 77b87f45..6c9226f5 100755 --- a/tb/test_axis_async_frame_fifo.py +++ b/tb/test_axis_async_frame_fifo.py @@ -44,10 +44,9 @@ src = ' '.join(srcs) build_cmd = "iverilog -o test_%s.vvp %s" % (module, src) -def dut_axis_async_frame_fifo(input_clk, - input_rst, +def dut_axis_async_frame_fifo(async_rst, + input_clk, output_clk, - output_rst, current_test, input_axis_tdata, @@ -68,10 +67,9 @@ def dut_axis_async_frame_fifo(input_clk, if os.system(build_cmd): raise Exception("Error running build command") return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module, + async_rst=async_rst, input_clk=input_clk, - input_rst=input_rst, output_clk=output_clk, - output_rst=output_rst, current_test=current_test, input_axis_tdata=input_axis_tdata, @@ -92,10 +90,9 @@ def dut_axis_async_frame_fifo(input_clk, def bench(): # Inputs + async_rst = Signal(bool(0)) input_clk = Signal(bool(0)) - input_rst = Signal(bool(0)) output_clk = Signal(bool(0)) - output_rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) input_axis_tdata = Signal(intbv(0)[8:]) @@ -120,7 +117,7 @@ def bench(): sink_pause = Signal(bool(0)) source = axis_ep.AXIStreamSource(input_clk, - input_rst, + async_rst, tdata=input_axis_tdata, tvalid=input_axis_tvalid, tready=input_axis_tready, @@ -131,7 +128,7 @@ def bench(): name='source') sink = axis_ep.AXIStreamSink(output_clk, - output_rst, + async_rst, tdata=output_axis_tdata, tvalid=output_axis_tvalid, tready=output_axis_tready, @@ -141,10 +138,9 @@ def bench(): name='sink') # DUT - dut = dut_axis_async_frame_fifo(input_clk, - input_rst, + dut = dut_axis_async_frame_fifo(async_rst, + input_clk, output_clk, - output_rst, current_test, input_axis_tdata, @@ -187,13 +183,11 @@ def bench(): def check(): yield delay(100) yield input_clk.posedge - input_rst.next = 1 - output_rst.next = 1 + async_rst.next = 1 yield input_clk.posedge yield input_clk.posedge yield input_clk.posedge - input_rst.next = 0 - output_rst.next = 0 + async_rst.next = 0 yield input_clk.posedge yield delay(100) yield input_clk.posedge @@ -537,7 +531,7 @@ def bench(): yield delay(100) yield input_clk.posedge - print("test 10: initial sink pause, input reset") + print("test 10: initial sink pause, assert reset") current_test.next = 10 test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03') @@ -549,38 +543,9 @@ def bench(): yield input_clk.posedge yield input_clk.posedge - input_rst.next = 1 + async_rst.next = 1 yield input_clk.posedge - input_rst.next = 0 - - sink_pause.next = 0 - - yield delay(100) - - yield output_clk.posedge - yield output_clk.posedge - yield output_clk.posedge - - assert sink_queue.empty() - - yield delay(100) - - yield input_clk.posedge - print("test 11: initial sink pause, output reset") - current_test.next = 11 - - test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03') - - sink_pause.next = 1 - source_queue.put(test_frame) - yield input_clk.posedge - yield input_clk.posedge - yield input_clk.posedge - yield input_clk.posedge - - output_rst.next = 1 - yield output_clk.posedge - output_rst.next = 0 + async_rst.next = 0 sink_pause.next = 0 diff --git a/tb/test_axis_async_frame_fifo.v b/tb/test_axis_async_frame_fifo.v index 2c603d75..7c57a7bc 100644 --- a/tb/test_axis_async_frame_fifo.v +++ b/tb/test_axis_async_frame_fifo.v @@ -29,10 +29,9 @@ THE SOFTWARE. module test_axis_async_frame_fifo; // Inputs +reg async_rst = 0; reg input_clk = 0; -reg input_rst = 0; reg output_clk = 0; -reg output_rst = 0; reg [7:0] current_test = 0; reg [7:0] input_axis_tdata = 0; @@ -52,10 +51,9 @@ wire good_frame; initial begin // myhdl integration - $from_myhdl(input_clk, - input_rst, + $from_myhdl(async_rst, + input_clk, output_clk, - output_rst, current_test, input_axis_tdata, input_axis_tvalid, @@ -81,9 +79,10 @@ axis_async_frame_fifo #( .DROP_WHEN_FULL(0) ) UUT ( + // Common reset + .async_rst(async_rst), // AXI input .input_clk(input_clk), - .input_rst(input_rst), .input_axis_tdata(input_axis_tdata), .input_axis_tvalid(input_axis_tvalid), .input_axis_tready(input_axis_tready), @@ -91,7 +90,6 @@ UUT ( .input_axis_tuser(input_axis_tuser), // AXI output .output_clk(output_clk), - .output_rst(output_rst), .output_axis_tdata(output_axis_tdata), .output_axis_tvalid(output_axis_tvalid), .output_axis_tready(output_axis_tready), diff --git a/tb/test_axis_async_frame_fifo_64.py b/tb/test_axis_async_frame_fifo_64.py index 5c5cb6ad..c01d651e 100755 --- a/tb/test_axis_async_frame_fifo_64.py +++ b/tb/test_axis_async_frame_fifo_64.py @@ -44,10 +44,9 @@ src = ' '.join(srcs) build_cmd = "iverilog -o test_%s.vvp %s" % (module, src) -def dut_axis_async_frame_fifo_64(input_clk, - input_rst, +def dut_axis_async_frame_fifo_64(async_rst, + input_clk, output_clk, - output_rst, current_test, input_axis_tdata, @@ -70,10 +69,9 @@ def dut_axis_async_frame_fifo_64(input_clk, if os.system(build_cmd): raise Exception("Error running build command") return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module, + async_rst=async_rst, input_clk=input_clk, - input_rst=input_rst, output_clk=output_clk, - output_rst=output_rst, current_test=current_test, input_axis_tdata=input_axis_tdata, @@ -96,10 +94,9 @@ def dut_axis_async_frame_fifo_64(input_clk, def bench(): # Inputs + async_rst = Signal(bool(0)) input_clk = Signal(bool(0)) - input_rst = Signal(bool(0)) output_clk = Signal(bool(0)) - output_rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) input_axis_tdata = Signal(intbv(0)[64:]) @@ -126,7 +123,7 @@ def bench(): sink_pause = Signal(bool(0)) source = axis_ep.AXIStreamSource(input_clk, - input_rst, + async_rst, tdata=input_axis_tdata, tkeep=input_axis_tkeep, tvalid=input_axis_tvalid, @@ -138,7 +135,7 @@ def bench(): name='source') sink = axis_ep.AXIStreamSink(output_clk, - output_rst, + async_rst, tdata=output_axis_tdata, tkeep=output_axis_tkeep, tvalid=output_axis_tvalid, @@ -149,10 +146,9 @@ def bench(): name='sink') # DUT - dut = dut_axis_async_frame_fifo_64(input_clk, - input_rst, + dut = dut_axis_async_frame_fifo_64(async_rst, + input_clk, output_clk, - output_rst, current_test, input_axis_tdata, @@ -197,13 +193,11 @@ def bench(): def check(): yield delay(100) yield input_clk.posedge - input_rst.next = 1 - output_rst.next = 1 + async_rst.next = 1 yield input_clk.posedge yield input_clk.posedge yield input_clk.posedge - input_rst.next = 0 - output_rst.next = 0 + async_rst.next = 0 yield input_clk.posedge yield delay(100) yield input_clk.posedge @@ -547,7 +541,7 @@ def bench(): yield delay(100) yield input_clk.posedge - print("test 10: initial sink pause, input reset") + print("test 10: initial sink pause, assert reset") current_test.next = 10 test_frame = axis_ep.AXIStreamFrame(bytearray(range(24))) @@ -559,38 +553,9 @@ def bench(): yield input_clk.posedge yield input_clk.posedge - input_rst.next = 1 + async_rst.next = 1 yield input_clk.posedge - input_rst.next = 0 - - sink_pause.next = 0 - - yield delay(100) - - yield output_clk.posedge - yield output_clk.posedge - yield output_clk.posedge - - assert sink_queue.empty() - - yield delay(100) - - yield input_clk.posedge - print("test 11: initial sink pause, output reset") - current_test.next = 11 - - test_frame = axis_ep.AXIStreamFrame(bytearray(range(24))) - - sink_pause.next = 1 - source_queue.put(test_frame) - yield input_clk.posedge - yield input_clk.posedge - yield input_clk.posedge - yield input_clk.posedge - - output_rst.next = 1 - yield output_clk.posedge - output_rst.next = 0 + async_rst.next = 0 sink_pause.next = 0 diff --git a/tb/test_axis_async_frame_fifo_64.v b/tb/test_axis_async_frame_fifo_64.v index 6ba39b21..27759a6c 100644 --- a/tb/test_axis_async_frame_fifo_64.v +++ b/tb/test_axis_async_frame_fifo_64.v @@ -29,10 +29,9 @@ THE SOFTWARE. module test_axis_async_frame_fifo_64; // Inputs +reg async_rst = 0; reg input_clk = 0; -reg input_rst = 0; reg output_clk = 0; -reg output_rst = 0; reg [7:0] current_test = 0; reg [63:0] input_axis_tdata = 0; @@ -54,10 +53,9 @@ wire good_frame; initial begin // myhdl integration - $from_myhdl(input_clk, - input_rst, + $from_myhdl(async_rst, + input_clk, output_clk, - output_rst, current_test, input_axis_tdata, input_axis_tkeep, @@ -85,9 +83,10 @@ axis_async_frame_fifo_64 #( .DROP_WHEN_FULL(0) ) UUT ( + // Common reset + .async_rst(async_rst), // AXI input .input_clk(input_clk), - .input_rst(input_rst), .input_axis_tdata(input_axis_tdata), .input_axis_tkeep(input_axis_tkeep), .input_axis_tvalid(input_axis_tvalid), @@ -96,7 +95,6 @@ UUT ( .input_axis_tuser(input_axis_tuser), // AXI output .output_clk(output_clk), - .output_rst(output_rst), .output_axis_tdata(output_axis_tdata), .output_axis_tkeep(output_axis_tkeep), .output_axis_tvalid(output_axis_tvalid),