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Remove redundant code

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This commit is contained in:
Alex Forencich 2016-08-23 09:25:19 -07:00
parent e989f15ff4
commit 3207a2b7d2
4 changed files with 10 additions and 136 deletions
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16
rtl/axis_switch.py
View File

@ -174,20 +174,6 @@ wire output_{{p}}_axis_tready_int_early;
assign input_{{p}}_axis_tready = input_{{p}}_axis_tready_reg;
{%- endfor %}
// mux for start of packet detection
{%- for p in range(n) %}
reg selected_input_{{p}}_axis_tvalid;
always @* begin
case (grant_encoded_{{p}})
{%- for q in range(m) %}
{{cm}}'d{{q}}: selected_input_{{p}}_axis_tvalid = input_{{q}}_axis_tvalid;
{%- endfor %}
default: selected_input_{{p}}_axis_tvalid = 1'b0;
endcase
end
{% endfor %}
// mux for incoming packet
{% for p in range(n) %}
reg [DATA_WIDTH-1:0] current_input_{{p}}_axis_tdata;
@ -306,7 +292,7 @@ always @* begin
if (current_input_{{p}}_axis_tvalid & current_input_{{p}}_axis_tready) begin
enable_{{p}}_next = ~current_input_{{p}}_axis_tlast;
end
end else if (grant_valid_{{p}} & selected_input_{{p}}_axis_tvalid) begin
end else if (grant_valid_{{p}}) begin
enable_{{p}}_next = 1'b1;
select_{{p}}_next = grant_encoded_{{p}};
end

57
rtl/axis_switch_4x4.v
View File

@ -220,55 +220,6 @@ assign input_1_axis_tready = input_1_axis_tready_reg;
assign input_2_axis_tready = input_2_axis_tready_reg;
assign input_3_axis_tready = input_3_axis_tready_reg;
// mux for start of packet detection
reg selected_input_0_axis_tvalid;
always @* begin
case (grant_encoded_0)
2'd0: selected_input_0_axis_tvalid = input_0_axis_tvalid;
2'd1: selected_input_0_axis_tvalid = input_1_axis_tvalid;
2'd2: selected_input_0_axis_tvalid = input_2_axis_tvalid;
2'd3: selected_input_0_axis_tvalid = input_3_axis_tvalid;
default: selected_input_0_axis_tvalid = 1'b0;
endcase
end
reg selected_input_1_axis_tvalid;
always @* begin
case (grant_encoded_1)
2'd0: selected_input_1_axis_tvalid = input_0_axis_tvalid;
2'd1: selected_input_1_axis_tvalid = input_1_axis_tvalid;
2'd2: selected_input_1_axis_tvalid = input_2_axis_tvalid;
2'd3: selected_input_1_axis_tvalid = input_3_axis_tvalid;
default: selected_input_1_axis_tvalid = 1'b0;
endcase
end
reg selected_input_2_axis_tvalid;
always @* begin
case (grant_encoded_2)
2'd0: selected_input_2_axis_tvalid = input_0_axis_tvalid;
2'd1: selected_input_2_axis_tvalid = input_1_axis_tvalid;
2'd2: selected_input_2_axis_tvalid = input_2_axis_tvalid;
2'd3: selected_input_2_axis_tvalid = input_3_axis_tvalid;
default: selected_input_2_axis_tvalid = 1'b0;
endcase
end
reg selected_input_3_axis_tvalid;
always @* begin
case (grant_encoded_3)
2'd0: selected_input_3_axis_tvalid = input_0_axis_tvalid;
2'd1: selected_input_3_axis_tvalid = input_1_axis_tvalid;
2'd2: selected_input_3_axis_tvalid = input_2_axis_tvalid;
2'd3: selected_input_3_axis_tvalid = input_3_axis_tvalid;
default: selected_input_3_axis_tvalid = 1'b0;
endcase
end
// mux for incoming packet
reg [DATA_WIDTH-1:0] current_input_0_axis_tdata;
@ -751,7 +702,7 @@ always @* begin
if (current_input_0_axis_tvalid & current_input_0_axis_tready) begin
enable_0_next = ~current_input_0_axis_tlast;
end
end else if (grant_valid_0 & selected_input_0_axis_tvalid) begin
end else if (grant_valid_0) begin
enable_0_next = 1'b1;
select_0_next = grant_encoded_0;
end
@ -760,7 +711,7 @@ always @* begin
if (current_input_1_axis_tvalid & current_input_1_axis_tready) begin
enable_1_next = ~current_input_1_axis_tlast;
end
end else if (grant_valid_1 & selected_input_1_axis_tvalid) begin
end else if (grant_valid_1) begin
enable_1_next = 1'b1;
select_1_next = grant_encoded_1;
end
@ -769,7 +720,7 @@ always @* begin
if (current_input_2_axis_tvalid & current_input_2_axis_tready) begin
enable_2_next = ~current_input_2_axis_tlast;
end
end else if (grant_valid_2 & selected_input_2_axis_tvalid) begin
end else if (grant_valid_2) begin
enable_2_next = 1'b1;
select_2_next = grant_encoded_2;
end
@ -778,7 +729,7 @@ always @* begin
if (current_input_3_axis_tvalid & current_input_3_axis_tready) begin
enable_3_next = ~current_input_3_axis_tlast;
end
end else if (grant_valid_3 & selected_input_3_axis_tvalid) begin
end else if (grant_valid_3) begin
enable_3_next = 1'b1;
select_3_next = grant_encoded_3;
end

16
rtl/axis_switch_64.py
View File

@ -178,20 +178,6 @@ wire output_{{p}}_axis_tready_int_early;
assign input_{{p}}_axis_tready = input_{{p}}_axis_tready_reg;
{%- endfor %}
// mux for start of packet detection
{%- for p in range(n) %}
reg selected_input_{{p}}_axis_tvalid;
always @* begin
case (grant_encoded_{{p}})
{%- for q in range(m) %}
{{cm}}'d{{q}}: selected_input_{{p}}_axis_tvalid = input_{{q}}_axis_tvalid;
{%- endfor %}
default: selected_input_{{p}}_axis_tvalid = 1'b0;
endcase
end
{% endfor %}
// mux for incoming packet
{% for p in range(n) %}
reg [DATA_WIDTH-1:0] current_input_{{p}}_axis_tdata;
@ -314,7 +300,7 @@ always @* begin
if (current_input_{{p}}_axis_tvalid & current_input_{{p}}_axis_tready) begin
enable_{{p}}_next = ~current_input_{{p}}_axis_tlast;
end
end else if (grant_valid_{{p}} & selected_input_{{p}}_axis_tvalid) begin
end else if (grant_valid_{{p}}) begin
enable_{{p}}_next = 1'b1;
select_{{p}}_next = grant_encoded_{{p}};
end

57
rtl/axis_switch_64_4x4.v
View File

@ -233,55 +233,6 @@ assign input_1_axis_tready = input_1_axis_tready_reg;
assign input_2_axis_tready = input_2_axis_tready_reg;
assign input_3_axis_tready = input_3_axis_tready_reg;
// mux for start of packet detection
reg selected_input_0_axis_tvalid;
always @* begin
case (grant_encoded_0)
2'd0: selected_input_0_axis_tvalid = input_0_axis_tvalid;
2'd1: selected_input_0_axis_tvalid = input_1_axis_tvalid;
2'd2: selected_input_0_axis_tvalid = input_2_axis_tvalid;
2'd3: selected_input_0_axis_tvalid = input_3_axis_tvalid;
default: selected_input_0_axis_tvalid = 1'b0;
endcase
end
reg selected_input_1_axis_tvalid;
always @* begin
case (grant_encoded_1)
2'd0: selected_input_1_axis_tvalid = input_0_axis_tvalid;
2'd1: selected_input_1_axis_tvalid = input_1_axis_tvalid;
2'd2: selected_input_1_axis_tvalid = input_2_axis_tvalid;
2'd3: selected_input_1_axis_tvalid = input_3_axis_tvalid;
default: selected_input_1_axis_tvalid = 1'b0;
endcase
end
reg selected_input_2_axis_tvalid;
always @* begin
case (grant_encoded_2)
2'd0: selected_input_2_axis_tvalid = input_0_axis_tvalid;
2'd1: selected_input_2_axis_tvalid = input_1_axis_tvalid;
2'd2: selected_input_2_axis_tvalid = input_2_axis_tvalid;
2'd3: selected_input_2_axis_tvalid = input_3_axis_tvalid;
default: selected_input_2_axis_tvalid = 1'b0;
endcase
end
reg selected_input_3_axis_tvalid;
always @* begin
case (grant_encoded_3)
2'd0: selected_input_3_axis_tvalid = input_0_axis_tvalid;
2'd1: selected_input_3_axis_tvalid = input_1_axis_tvalid;
2'd2: selected_input_3_axis_tvalid = input_2_axis_tvalid;
2'd3: selected_input_3_axis_tvalid = input_3_axis_tvalid;
default: selected_input_3_axis_tvalid = 1'b0;
endcase
end
// mux for incoming packet
reg [DATA_WIDTH-1:0] current_input_0_axis_tdata;
@ -792,7 +743,7 @@ always @* begin
if (current_input_0_axis_tvalid & current_input_0_axis_tready) begin
enable_0_next = ~current_input_0_axis_tlast;
end
end else if (grant_valid_0 & selected_input_0_axis_tvalid) begin
end else if (grant_valid_0) begin
enable_0_next = 1'b1;
select_0_next = grant_encoded_0;
end
@ -801,7 +752,7 @@ always @* begin
if (current_input_1_axis_tvalid & current_input_1_axis_tready) begin
enable_1_next = ~current_input_1_axis_tlast;
end
end else if (grant_valid_1 & selected_input_1_axis_tvalid) begin
end else if (grant_valid_1) begin
enable_1_next = 1'b1;
select_1_next = grant_encoded_1;
end
@ -810,7 +761,7 @@ always @* begin
if (current_input_2_axis_tvalid & current_input_2_axis_tready) begin
enable_2_next = ~current_input_2_axis_tlast;
end
end else if (grant_valid_2 & selected_input_2_axis_tvalid) begin
end else if (grant_valid_2) begin
enable_2_next = 1'b1;
select_2_next = grant_encoded_2;
end
@ -819,7 +770,7 @@ always @* begin
if (current_input_3_axis_tvalid & current_input_3_axis_tready) begin
enable_3_next = ~current_input_3_axis_tlast;
end
end else if (grant_valid_3 & selected_input_3_axis_tvalid) begin
end else if (grant_valid_3) begin
enable_3_next = 1'b1;
select_3_next = grant_encoded_3;
end