Synchronize status signals for both clock domains in async frame FIFO

This commit is contained in:
Alex Forencich 2015-10-09 15:14:54 -07:00
parent 382226ad59
commit 364b537312
6 changed files with 442 additions and 172 deletions

View File

@ -63,9 +63,12 @@ module axis_async_frame_fifo #
/*
* Status
*/
output wire overflow,
output wire bad_frame,
output wire good_frame
output wire input_status_overflow,
output wire input_status_bad_frame,
output wire input_status_good_frame,
output wire output_status_overflow,
output wire output_status_bad_frame,
output wire output_status_good_frame
);
reg [ADDR_WIDTH:0] wr_ptr = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
@ -91,6 +94,19 @@ reg overflow_reg = 1'b0;
reg bad_frame_reg = 1'b0;
reg good_frame_reg = 1'b0;
reg overflow_sync1 = 1'b0;
reg overflow_sync2 = 1'b0;
reg overflow_sync3 = 1'b0;
reg overflow_sync4 = 1'b0;
reg bad_frame_sync1 = 1'b0;
reg bad_frame_sync2 = 1'b0;
reg bad_frame_sync3 = 1'b0;
reg bad_frame_sync4 = 1'b0;
reg good_frame_sync1 = 1'b0;
reg good_frame_sync2 = 1'b0;
reg good_frame_sync3 = 1'b0;
reg good_frame_sync4 = 1'b0;
reg [DATA_WIDTH+2-1:0] data_out_reg = {1'b0, {DATA_WIDTH{1'b0}}};
//(* RAM_STYLE="BLOCK" *)
@ -119,9 +135,13 @@ assign {output_axis_tlast, output_axis_tdata} = data_out_reg;
assign input_axis_tready = (~full | DROP_WHEN_FULL) & ~input_rst_sync3;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign overflow = overflow_reg;
assign bad_frame = bad_frame_reg;
assign good_frame = good_frame_reg;
assign input_status_overflow = overflow_reg;
assign input_status_bad_frame = bad_frame_reg;
assign input_status_good_frame = good_frame_reg;
assign output_status_overflow = overflow_sync3 ^ overflow_sync4;
assign output_status_bad_frame = bad_frame_sync3 ^ bad_frame_sync4;
assign output_status_good_frame = good_frame_sync3 ^ good_frame_sync4;
// reset synchronization
always @(posedge input_clk or posedge async_rst) begin
@ -240,4 +260,38 @@ always @(posedge output_clk) begin
end
end
// status synchronization
always @(posedge input_clk) begin
if (input_rst_sync3) begin
overflow_sync1 <= 1'b0;
bad_frame_sync1 <= 1'b0;
good_frame_sync1 <= 1'b0;
end else begin
overflow_sync1 <= overflow_sync1 ^ overflow_reg;
bad_frame_sync1 <= bad_frame_sync1 ^ bad_frame_reg;
good_frame_sync1 <= good_frame_sync1 ^ good_frame_reg;
end
end
always @(posedge output_clk) begin
if (output_rst_sync3) begin
overflow_sync2 <= 1'b0;
overflow_sync3 <= 1'b0;
bad_frame_sync2 <= 1'b0;
bad_frame_sync3 <= 1'b0;
good_frame_sync2 <= 1'b0;
good_frame_sync3 <= 1'b0;
end else begin
overflow_sync2 <= overflow_sync1;
overflow_sync3 <= overflow_sync2;
overflow_sync4 <= overflow_sync3;
bad_frame_sync2 <= bad_frame_sync1;
bad_frame_sync3 <= bad_frame_sync2;
bad_frame_sync4 <= bad_frame_sync3;
good_frame_sync2 <= good_frame_sync1;
good_frame_sync3 <= good_frame_sync2;
good_frame_sync4 <= good_frame_sync3;
end
end
endmodule

View File

@ -66,9 +66,12 @@ module axis_async_frame_fifo_64 #
/*
* Status
*/
output wire overflow,
output wire bad_frame,
output wire good_frame
output wire input_status_overflow,
output wire input_status_bad_frame,
output wire input_status_good_frame,
output wire output_status_overflow,
output wire output_status_bad_frame,
output wire output_status_good_frame
);
reg [ADDR_WIDTH:0] wr_ptr = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
@ -94,6 +97,19 @@ reg overflow_reg = 1'b0;
reg bad_frame_reg = 1'b0;
reg good_frame_reg = 1'b0;
reg overflow_sync1 = 1'b0;
reg overflow_sync2 = 1'b0;
reg overflow_sync3 = 1'b0;
reg overflow_sync4 = 1'b0;
reg bad_frame_sync1 = 1'b0;
reg bad_frame_sync2 = 1'b0;
reg bad_frame_sync3 = 1'b0;
reg bad_frame_sync4 = 1'b0;
reg good_frame_sync1 = 1'b0;
reg good_frame_sync2 = 1'b0;
reg good_frame_sync3 = 1'b0;
reg good_frame_sync4 = 1'b0;
reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] data_out_reg = {1'b0, {KEEP_WIDTH{1'b0}}, {DATA_WIDTH{1'b0}}};
//(* RAM_STYLE="BLOCK" *)
@ -122,9 +138,13 @@ assign {output_axis_tlast, output_axis_tkeep, output_axis_tdata} = data_out_reg;
assign input_axis_tready = (~full | DROP_WHEN_FULL) & ~input_rst_sync3;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign overflow = overflow_reg;
assign bad_frame = bad_frame_reg;
assign good_frame = good_frame_reg;
assign input_status_overflow = overflow_reg;
assign input_status_bad_frame = bad_frame_reg;
assign input_status_good_frame = good_frame_reg;
assign output_status_overflow = overflow_sync3 ^ overflow_sync4;
assign output_status_bad_frame = bad_frame_sync3 ^ bad_frame_sync4;
assign output_status_good_frame = good_frame_sync3 ^ good_frame_sync4;
// reset synchronization
always @(posedge input_clk or posedge async_rst) begin
@ -243,4 +263,38 @@ always @(posedge output_clk) begin
end
end
// status synchronization
always @(posedge input_clk) begin
if (input_rst_sync3) begin
overflow_sync1 <= 1'b0;
bad_frame_sync1 <= 1'b0;
good_frame_sync1 <= 1'b0;
end else begin
overflow_sync1 <= overflow_sync1 ^ overflow_reg;
bad_frame_sync1 <= bad_frame_sync1 ^ bad_frame_reg;
good_frame_sync1 <= good_frame_sync1 ^ good_frame_reg;
end
end
always @(posedge output_clk) begin
if (output_rst_sync3) begin
overflow_sync2 <= 1'b0;
overflow_sync3 <= 1'b0;
bad_frame_sync2 <= 1'b0;
bad_frame_sync3 <= 1'b0;
good_frame_sync2 <= 1'b0;
good_frame_sync3 <= 1'b0;
end else begin
overflow_sync2 <= overflow_sync1;
overflow_sync3 <= overflow_sync2;
overflow_sync4 <= overflow_sync3;
bad_frame_sync2 <= bad_frame_sync1;
bad_frame_sync3 <= bad_frame_sync2;
bad_frame_sync4 <= bad_frame_sync3;
good_frame_sync2 <= good_frame_sync1;
good_frame_sync3 <= good_frame_sync2;
good_frame_sync4 <= good_frame_sync3;
end
end
endmodule

View File

@ -60,9 +60,12 @@ def dut_axis_async_frame_fifo(async_rst,
output_axis_tready,
output_axis_tlast,
overflow,
bad_frame,
good_frame):
input_status_overflow,
input_status_bad_frame,
input_status_good_frame,
output_status_overflow,
output_status_bad_frame,
output_status_good_frame):
if os.system(build_cmd):
raise Exception("Error running build command")
@ -83,9 +86,12 @@ def dut_axis_async_frame_fifo(async_rst,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
overflow=overflow,
bad_frame=bad_frame,
good_frame=good_frame)
input_status_overflow=input_status_overflow,
input_status_bad_frame=input_status_bad_frame,
input_status_good_frame=input_status_good_frame,
output_status_overflow=output_status_overflow,
output_status_bad_frame=output_status_bad_frame,
output_status_good_frame=output_status_good_frame)
def bench():
@ -106,9 +112,12 @@ def bench():
output_axis_tdata = Signal(intbv(0)[8:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
overflow = Signal(bool(0))
bad_frame = Signal(bool(0))
good_frame = Signal(bool(0))
input_status_overflow = Signal(bool(0))
input_status_bad_frame = Signal(bool(0))
input_status_good_frame = Signal(bool(0))
output_status_overflow = Signal(bool(0))
output_status_bad_frame = Signal(bool(0))
output_status_good_frame = Signal(bool(0))
# sources and sinks
source_queue = Queue()
@ -154,9 +163,12 @@ def bench():
output_axis_tready,
output_axis_tlast,
overflow,
bad_frame,
good_frame)
input_status_overflow,
input_status_bad_frame,
input_status_good_frame,
output_status_overflow,
output_status_bad_frame,
output_status_good_frame)
@always(delay(4))
def input_clkgen():
@ -166,18 +178,30 @@ def bench():
def output_clkgen():
output_clk.next = not output_clk
overflow_asserted = Signal(bool(0))
bad_frame_asserted = Signal(bool(0))
good_frame_asserted = Signal(bool(0))
input_status_overflow_asserted = Signal(bool(0))
input_status_bad_frame_asserted = Signal(bool(0))
input_status_good_frame_asserted = Signal(bool(0))
output_status_overflow_asserted = Signal(bool(0))
output_status_bad_frame_asserted = Signal(bool(0))
output_status_good_frame_asserted = Signal(bool(0))
@always(input_clk.posedge)
def monitor():
if (overflow):
overflow_asserted.next = 1
if (bad_frame):
bad_frame_asserted.next = 1
if (good_frame):
good_frame_asserted.next = 1
def monitor_1():
if (input_status_overflow):
input_status_overflow_asserted.next = 1
if (input_status_bad_frame):
input_status_bad_frame_asserted.next = 1
if (input_status_good_frame):
input_status_good_frame_asserted.next = 1
@always(output_clk.posedge)
def monitor_2():
if (output_status_overflow):
output_status_overflow_asserted.next = 1
if (output_status_bad_frame):
output_status_bad_frame_asserted.next = 1
if (output_status_good_frame):
output_status_good_frame_asserted.next = 1
@instance
def check():
@ -203,9 +227,12 @@ def bench():
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
overflow_asserted.next = 0
bad_frame_asserted.next = 0
good_frame_asserted.next = 0
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source_queue.put(test_frame)
yield input_clk.posedge
@ -220,9 +247,12 @@ def bench():
assert rx_frame == test_frame
assert not overflow_asserted
assert not bad_frame_asserted
assert good_frame_asserted
assert not input_status_overflow_asserted
assert not input_status_bad_frame_asserted
assert input_status_good_frame_asserted
assert not output_status_overflow_asserted
assert not output_status_bad_frame_asserted
assert output_status_good_frame_asserted
yield delay(100)
@ -235,9 +265,12 @@ def bench():
b'\x80\x00' +
bytearray(range(256)))
overflow_asserted.next = 0
bad_frame_asserted.next = 0
good_frame_asserted.next = 0
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source_queue.put(test_frame)
yield input_clk.posedge
@ -252,9 +285,12 @@ def bench():
assert rx_frame == test_frame
assert not overflow_asserted
assert not bad_frame_asserted
assert good_frame_asserted
assert not input_status_overflow_asserted
assert not input_status_bad_frame_asserted
assert input_status_good_frame_asserted
assert not output_status_overflow_asserted
assert not output_status_bad_frame_asserted
assert output_status_good_frame_asserted
yield input_clk.posedge
print("test 3: test packet with pauses")
@ -265,9 +301,12 @@ def bench():
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
overflow_asserted.next = 0
bad_frame_asserted.next = 0
good_frame_asserted.next = 0
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source_queue.put(test_frame)
yield input_clk.posedge
@ -296,9 +335,12 @@ def bench():
assert rx_frame == test_frame
assert not overflow_asserted
assert not bad_frame_asserted
assert good_frame_asserted
assert not input_status_overflow_asserted
assert not input_status_bad_frame_asserted
assert input_status_good_frame_asserted
assert not output_status_overflow_asserted
assert not output_status_bad_frame_asserted
assert output_status_good_frame_asserted
yield delay(100)
@ -315,9 +357,12 @@ def bench():
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
overflow_asserted.next = 0
bad_frame_asserted.next = 0
good_frame_asserted.next = 0
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source_queue.put(test_frame1)
source_queue.put(test_frame2)
@ -341,9 +386,12 @@ def bench():
assert rx_frame == test_frame2
assert not overflow_asserted
assert not bad_frame_asserted
assert good_frame_asserted
assert not input_status_overflow_asserted
assert not input_status_bad_frame_asserted
assert input_status_good_frame_asserted
assert not output_status_overflow_asserted
assert not output_status_bad_frame_asserted
assert output_status_good_frame_asserted
yield delay(100)
@ -360,9 +408,12 @@ def bench():
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
overflow_asserted.next = 0
bad_frame_asserted.next = 0
good_frame_asserted.next = 0
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source_queue.put(test_frame1)
source_queue.put(test_frame2)
@ -395,9 +446,12 @@ def bench():
assert rx_frame == test_frame2
assert not overflow_asserted
assert not bad_frame_asserted
assert good_frame_asserted
assert not input_status_overflow_asserted
assert not input_status_bad_frame_asserted
assert input_status_good_frame_asserted
assert not output_status_overflow_asserted
assert not output_status_bad_frame_asserted
assert output_status_good_frame_asserted
yield delay(100)
@ -414,9 +468,12 @@ def bench():
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
overflow_asserted.next = 0
bad_frame_asserted.next = 0
good_frame_asserted.next = 0
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source_queue.put(test_frame1)
source_queue.put(test_frame2)
@ -445,9 +502,12 @@ def bench():
assert rx_frame == test_frame2
assert not overflow_asserted
assert not bad_frame_asserted
assert good_frame_asserted
assert not input_status_overflow_asserted
assert not input_status_bad_frame_asserted
assert input_status_good_frame_asserted
assert not output_status_overflow_asserted
assert not output_status_bad_frame_asserted
assert output_status_good_frame_asserted
yield delay(100)
@ -461,9 +521,12 @@ def bench():
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame.user = 1
overflow_asserted.next = 0
bad_frame_asserted.next = 0
good_frame_asserted.next = 0
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source_queue.put(test_frame)
yield input_clk.posedge
@ -472,9 +535,12 @@ def bench():
assert sink_queue.empty()
assert not overflow_asserted
assert bad_frame_asserted
assert not good_frame_asserted
assert not input_status_overflow_asserted
assert input_status_bad_frame_asserted
assert not input_status_good_frame_asserted
assert not output_status_overflow_asserted
assert output_status_bad_frame_asserted
assert not output_status_good_frame_asserted
yield delay(100)
@ -487,9 +553,12 @@ def bench():
b'\x80\x00' +
bytearray(range(256))*2)
overflow_asserted.next = 0
bad_frame_asserted.next = 0
good_frame_asserted.next = 0
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source_queue.put(test_frame)
yield input_clk.posedge
@ -498,9 +567,12 @@ def bench():
assert sink_queue.empty()
assert overflow_asserted
assert not bad_frame_asserted
assert not good_frame_asserted
assert input_status_overflow_asserted
assert not input_status_bad_frame_asserted
assert not input_status_good_frame_asserted
assert output_status_overflow_asserted
assert not output_status_bad_frame_asserted
assert not output_status_good_frame_asserted
yield delay(100)
@ -561,7 +633,7 @@ def bench():
raise StopSimulation
return dut, monitor, source, sink, input_clkgen, output_clkgen, check
return dut, monitor_1, monitor_2, source, sink, input_clkgen, output_clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))

View File

@ -45,9 +45,12 @@ wire input_axis_tready;
wire [7:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
wire overflow;
wire bad_frame;
wire good_frame;
wire input_status_overflow;
wire input_status_bad_frame;
wire input_status_good_frame;
wire output_status_overflow;
wire output_status_bad_frame;
wire output_status_good_frame;
initial begin
// myhdl integration
@ -64,9 +67,12 @@ initial begin
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
overflow,
bad_frame,
good_frame);
input_status_overflow,
input_status_bad_frame,
input_status_good_frame,
output_status_overflow,
output_status_bad_frame,
output_status_good_frame);
// dump file
$dumpfile("test_axis_async_frame_fifo.lxt");
@ -95,9 +101,12 @@ UUT (
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
// Status
.overflow(overflow),
.bad_frame(bad_frame),
.good_frame(good_frame)
.input_status_overflow(input_status_overflow),
.input_status_bad_frame(input_status_bad_frame),
.input_status_good_frame(input_status_good_frame),
.output_status_overflow(output_status_overflow),
.output_status_bad_frame(output_status_bad_frame),
.output_status_good_frame(output_status_good_frame)
);
endmodule

View File

@ -62,9 +62,12 @@ def dut_axis_async_frame_fifo_64(async_rst,
output_axis_tready,
output_axis_tlast,
overflow,
bad_frame,
good_frame):
input_status_overflow,
input_status_bad_frame,
input_status_good_frame,
output_status_overflow,
output_status_bad_frame,
output_status_good_frame):
if os.system(build_cmd):
raise Exception("Error running build command")
@ -87,9 +90,12 @@ def dut_axis_async_frame_fifo_64(async_rst,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
overflow=overflow,
bad_frame=bad_frame,
good_frame=good_frame)
input_status_overflow=input_status_overflow,
input_status_bad_frame=input_status_bad_frame,
input_status_good_frame=input_status_good_frame,
output_status_overflow=output_status_overflow,
output_status_bad_frame=output_status_bad_frame,
output_status_good_frame=output_status_good_frame)
def bench():
@ -112,9 +118,12 @@ def bench():
output_axis_tkeep = Signal(intbv(0)[8:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
overflow = Signal(bool(0))
bad_frame = Signal(bool(0))
good_frame = Signal(bool(0))
input_status_overflow = Signal(bool(0))
input_status_bad_frame = Signal(bool(0))
input_status_good_frame = Signal(bool(0))
output_status_overflow = Signal(bool(0))
output_status_bad_frame = Signal(bool(0))
output_status_good_frame = Signal(bool(0))
# sources and sinks
source_queue = Queue()
@ -164,9 +173,12 @@ def bench():
output_axis_tready,
output_axis_tlast,
overflow,
bad_frame,
good_frame)
input_status_overflow,
input_status_bad_frame,
input_status_good_frame,
output_status_overflow,
output_status_bad_frame,
output_status_good_frame)
@always(delay(4))
def input_clkgen():
@ -176,18 +188,30 @@ def bench():
def output_clkgen():
output_clk.next = not output_clk
overflow_asserted = Signal(bool(0))
bad_frame_asserted = Signal(bool(0))
good_frame_asserted = Signal(bool(0))
input_status_overflow_asserted = Signal(bool(0))
input_status_bad_frame_asserted = Signal(bool(0))
input_status_good_frame_asserted = Signal(bool(0))
output_status_overflow_asserted = Signal(bool(0))
output_status_bad_frame_asserted = Signal(bool(0))
output_status_good_frame_asserted = Signal(bool(0))
@always(input_clk.posedge)
def monitor():
if (overflow):
overflow_asserted.next = 1
if (bad_frame):
bad_frame_asserted.next = 1
if (good_frame):
good_frame_asserted.next = 1
def monitor_1():
if (input_status_overflow):
input_status_overflow_asserted.next = 1
if (input_status_bad_frame):
input_status_bad_frame_asserted.next = 1
if (input_status_good_frame):
input_status_good_frame_asserted.next = 1
@always(output_clk.posedge)
def monitor_2():
if (output_status_overflow):
output_status_overflow_asserted.next = 1
if (output_status_bad_frame):
output_status_bad_frame_asserted.next = 1
if (output_status_good_frame):
output_status_good_frame_asserted.next = 1
@instance
def check():
@ -213,9 +237,12 @@ def bench():
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
overflow_asserted.next = 0
bad_frame_asserted.next = 0
good_frame_asserted.next = 0
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source_queue.put(test_frame)
yield input_clk.posedge
@ -230,9 +257,12 @@ def bench():
assert rx_frame == test_frame
assert not overflow_asserted
assert not bad_frame_asserted
assert good_frame_asserted
assert not input_status_overflow_asserted
assert not input_status_bad_frame_asserted
assert input_status_good_frame_asserted
assert not output_status_overflow_asserted
assert not output_status_bad_frame_asserted
assert output_status_good_frame_asserted
yield delay(100)
@ -245,9 +275,12 @@ def bench():
b'\x80\x00' +
bytearray(range(256)))
overflow_asserted.next = 0
bad_frame_asserted.next = 0
good_frame_asserted.next = 0
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source_queue.put(test_frame)
yield input_clk.posedge
@ -262,9 +295,12 @@ def bench():
assert rx_frame == test_frame
assert not overflow_asserted
assert not bad_frame_asserted
assert good_frame_asserted
assert not input_status_overflow_asserted
assert not input_status_bad_frame_asserted
assert input_status_good_frame_asserted
assert not output_status_overflow_asserted
assert not output_status_bad_frame_asserted
assert output_status_good_frame_asserted
yield input_clk.posedge
print("test 3: test packet with pauses")
@ -275,9 +311,12 @@ def bench():
b'\x80\x00' +
bytearray(range(256)))
overflow_asserted.next = 0
bad_frame_asserted.next = 0
good_frame_asserted.next = 0
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source_queue.put(test_frame)
yield input_clk.posedge
@ -306,9 +345,12 @@ def bench():
assert rx_frame == test_frame
assert not overflow_asserted
assert not bad_frame_asserted
assert good_frame_asserted
assert not input_status_overflow_asserted
assert not input_status_bad_frame_asserted
assert input_status_good_frame_asserted
assert not output_status_overflow_asserted
assert not output_status_bad_frame_asserted
assert output_status_good_frame_asserted
yield delay(100)
@ -325,9 +367,12 @@ def bench():
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
overflow_asserted.next = 0
bad_frame_asserted.next = 0
good_frame_asserted.next = 0
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source_queue.put(test_frame1)
source_queue.put(test_frame2)
@ -351,9 +396,12 @@ def bench():
assert rx_frame == test_frame2
assert not overflow_asserted
assert not bad_frame_asserted
assert good_frame_asserted
assert not input_status_overflow_asserted
assert not input_status_bad_frame_asserted
assert input_status_good_frame_asserted
assert not output_status_overflow_asserted
assert not output_status_bad_frame_asserted
assert output_status_good_frame_asserted
yield delay(100)
@ -370,9 +418,12 @@ def bench():
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
overflow_asserted.next = 0
bad_frame_asserted.next = 0
good_frame_asserted.next = 0
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source_queue.put(test_frame1)
source_queue.put(test_frame2)
@ -405,9 +456,12 @@ def bench():
assert rx_frame == test_frame2
assert not overflow_asserted
assert not bad_frame_asserted
assert good_frame_asserted
assert not input_status_overflow_asserted
assert not input_status_bad_frame_asserted
assert input_status_good_frame_asserted
assert not output_status_overflow_asserted
assert not output_status_bad_frame_asserted
assert output_status_good_frame_asserted
yield delay(100)
@ -424,9 +478,12 @@ def bench():
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
overflow_asserted.next = 0
bad_frame_asserted.next = 0
good_frame_asserted.next = 0
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source_queue.put(test_frame1)
source_queue.put(test_frame2)
@ -455,9 +512,12 @@ def bench():
assert rx_frame == test_frame2
assert not overflow_asserted
assert not bad_frame_asserted
assert good_frame_asserted
assert not input_status_overflow_asserted
assert not input_status_bad_frame_asserted
assert input_status_good_frame_asserted
assert not output_status_overflow_asserted
assert not output_status_bad_frame_asserted
assert output_status_good_frame_asserted
yield delay(100)
@ -471,9 +531,12 @@ def bench():
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame.user = 1
overflow_asserted.next = 0
bad_frame_asserted.next = 0
good_frame_asserted.next = 0
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source_queue.put(test_frame)
yield input_clk.posedge
@ -482,9 +545,12 @@ def bench():
assert sink_queue.empty()
assert not overflow_asserted
assert bad_frame_asserted
assert not good_frame_asserted
assert not input_status_overflow_asserted
assert input_status_bad_frame_asserted
assert not input_status_good_frame_asserted
assert not output_status_overflow_asserted
assert output_status_bad_frame_asserted
assert not output_status_good_frame_asserted
yield delay(100)
@ -497,9 +563,12 @@ def bench():
b'\x80\x00' +
bytearray(range(256))*2)
overflow_asserted.next = 0
bad_frame_asserted.next = 0
good_frame_asserted.next = 0
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source_queue.put(test_frame)
yield input_clk.posedge
@ -508,9 +577,12 @@ def bench():
assert sink_queue.empty()
assert overflow_asserted
assert not bad_frame_asserted
assert not good_frame_asserted
assert input_status_overflow_asserted
assert not input_status_bad_frame_asserted
assert not input_status_good_frame_asserted
assert output_status_overflow_asserted
assert not output_status_bad_frame_asserted
assert not output_status_good_frame_asserted
yield delay(100)
@ -571,7 +643,7 @@ def bench():
raise StopSimulation
return dut, monitor, source, sink, input_clkgen, output_clkgen, check
return dut, monitor_1, monitor_2, source, sink, input_clkgen, output_clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))

View File

@ -47,9 +47,12 @@ wire [63:0] output_axis_tdata;
wire [7:0] output_axis_tkeep;
wire output_axis_tvalid;
wire output_axis_tlast;
wire overflow;
wire bad_frame;
wire good_frame;
wire input_status_overflow;
wire input_status_bad_frame;
wire input_status_good_frame;
wire output_status_overflow;
wire output_status_bad_frame;
wire output_status_good_frame;
initial begin
// myhdl integration
@ -68,9 +71,12 @@ initial begin
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
overflow,
bad_frame,
good_frame);
input_status_overflow,
input_status_bad_frame,
input_status_good_frame,
output_status_overflow,
output_status_bad_frame,
output_status_good_frame);
// dump file
$dumpfile("test_axis_async_frame_fifo_64.lxt");
@ -101,9 +107,12 @@ UUT (
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
// Status
.overflow(overflow),
.bad_frame(bad_frame),
.good_frame(good_frame)
.input_status_overflow(input_status_overflow),
.input_status_bad_frame(input_status_bad_frame),
.input_status_good_frame(input_status_good_frame),
.output_status_overflow(output_status_overflow),
.output_status_bad_frame(output_status_bad_frame),
.output_status_good_frame(output_status_good_frame)
);
endmodule