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Fix Vivado block RAM inference

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This commit is contained in:
Alex Forencich 2016-06-27 12:10:36 -07:00
parent 4f66059d21
commit 385c9cc90a
8 changed files with 56 additions and 64 deletions
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15
rtl/axis_async_fifo.v
View File

@ -79,11 +79,10 @@ reg output_rst_sync2_reg = 1'b1;
reg output_rst_sync3_reg = 1'b1;
reg [DATA_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0];
reg [DATA_WIDTH+2-1:0] mem_read_data_reg = {DATA_WIDTH+2{1'b0}};
wire [DATA_WIDTH+2-1:0] mem_write_data;
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
reg output_axis_tlast_reg = 1'b0;
reg output_axis_tuser_reg = 1'b0;
// full when first TWO MSBs do NOT match, but rest matches
// (gray code equivalent of first MSB different but rest same)
@ -99,10 +98,10 @@ reg read;
assign input_axis_tready = ~full & ~input_rst_sync3_reg;
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg;
assign output_axis_tuser = output_axis_tuser_reg;
assign mem_write_data = {input_axis_tlast, input_axis_tuser, input_axis_tdata};
assign {output_axis_tlast, output_axis_tuser, output_axis_tdata} = mem_read_data_reg;
// reset synchronization
always @(posedge input_clk or posedge async_rst) begin
@ -157,7 +156,7 @@ always @(posedge input_clk) begin
end
if (write) begin
mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= {input_axis_tlast, input_axis_tuser, input_axis_tdata};
mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= mem_write_data;
end
end
@ -217,7 +216,7 @@ always @(posedge output_clk) begin
end
if (read) begin
{output_axis_tlast_reg, output_axis_tuser_reg, output_axis_tdata_reg} <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]];
mem_read_data_reg <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]];
end
end

17
rtl/axis_async_fifo_64.v
View File

@ -82,12 +82,10 @@ reg output_rst_sync2_reg = 1'b1;
reg output_rst_sync3_reg = 1'b1;
reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0];
reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] mem_read_data_reg = {DATA_WIDTH+2{1'b0}};
wire [DATA_WIDTH+KEEP_WIDTH+2-1:0] mem_write_data;
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
reg output_axis_tlast_reg = 1'b0;
reg output_axis_tuser_reg = 1'b0;
// full when first TWO MSBs do NOT match, but rest matches
// (gray code equivalent of first MSB different but rest same)
@ -103,11 +101,10 @@ reg read;
assign input_axis_tready = ~full & ~input_rst_sync3_reg;
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tkeep = output_axis_tkeep_reg;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg;
assign output_axis_tuser = output_axis_tuser_reg;
assign mem_write_data = {input_axis_tlast, input_axis_tuser, input_axis_tkeep, input_axis_tdata};
assign {output_axis_tlast, output_axis_tuser, output_axis_tkeep, output_axis_tdata} = mem_read_data_reg;
// reset synchronization
always @(posedge input_clk or posedge async_rst) begin
@ -162,7 +159,7 @@ always @(posedge input_clk) begin
end
if (write) begin
mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= {input_axis_tlast, input_axis_tuser, input_axis_tkeep, input_axis_tdata};
mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= mem_write_data;
end
end
@ -222,7 +219,7 @@ always @(posedge output_clk) begin
end
if (read) begin
{output_axis_tlast_reg, output_axis_tuser_reg, output_axis_tkeep_reg, output_axis_tdata_reg} <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]];
mem_read_data_reg <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]];
end
end

13
rtl/axis_async_frame_fifo.v
View File

@ -90,10 +90,10 @@ reg output_rst_sync2_reg = 1'b1;
reg output_rst_sync3_reg = 1'b1;
reg [DATA_WIDTH+1-1:0] mem[(2**ADDR_WIDTH)-1:0];
reg [DATA_WIDTH+1-1:0] mem_read_data_reg = {DATA_WIDTH+2{1'b0}};
wire [DATA_WIDTH+1-1:0] mem_write_data;
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
reg output_axis_tlast_reg = 1'b0;
// full when first TWO MSBs do NOT match, but rest matches
// (gray code equivalent of first MSB different but rest same)
@ -130,9 +130,10 @@ reg good_frame_sync4_reg = 1'b0;
assign input_axis_tready = (~full | DROP_WHEN_FULL) & ~input_rst_sync3_reg;
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg;
assign mem_write_data = {input_axis_tlast, input_axis_tdata};
assign {output_axis_tlast, output_axis_tdata} = mem_read_data_reg;
assign input_status_overflow = overflow_reg;
assign input_status_bad_frame = bad_frame_reg;
@ -237,7 +238,7 @@ always @(posedge input_clk) begin
end
if (write) begin
mem[wr_ptr_cur_reg[ADDR_WIDTH-1:0]] <= {input_axis_tlast, input_axis_tdata};
mem[wr_ptr_cur_reg[ADDR_WIDTH-1:0]] <= mem_write_data;
end
end
@ -331,7 +332,7 @@ always @(posedge output_clk) begin
end
if (read) begin
{output_axis_tlast_reg, output_axis_tdata_reg} <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]];
mem_read_data_reg <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]];
end
end

15
rtl/axis_async_frame_fifo_64.v
View File

@ -93,11 +93,10 @@ reg output_rst_sync2_reg = 1'b1;
reg output_rst_sync3_reg = 1'b1;
reg [DATA_WIDTH+KEEP_WIDTH+1-1:0] mem[(2**ADDR_WIDTH)-1:0];
reg [DATA_WIDTH+KEEP_WIDTH+1-1:0] mem_read_data_reg = {DATA_WIDTH+2{1'b0}};
wire [DATA_WIDTH+KEEP_WIDTH+1-1:0] mem_write_data;
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
reg output_axis_tlast_reg = 1'b0;
// full when first TWO MSBs do NOT match, but rest matches
// (gray code equivalent of first MSB different but rest same)
@ -134,10 +133,10 @@ reg good_frame_sync4_reg = 1'b0;
assign input_axis_tready = (~full | DROP_WHEN_FULL) & ~input_rst_sync3_reg;
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tkeep = output_axis_tkeep_reg;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg;
assign mem_write_data = {input_axis_tlast, input_axis_tkeep, input_axis_tdata};
assign {output_axis_tlast, output_axis_tkeep, output_axis_tdata} = mem_read_data_reg;
assign input_status_overflow = overflow_reg;
assign input_status_bad_frame = bad_frame_reg;
@ -242,7 +241,7 @@ always @(posedge input_clk) begin
end
if (write) begin
mem[wr_ptr_cur_reg[ADDR_WIDTH-1:0]] <= {input_axis_tlast, input_axis_tkeep, input_axis_tdata};
mem[wr_ptr_cur_reg[ADDR_WIDTH-1:0]] <= mem_write_data;
end
end
@ -336,7 +335,7 @@ always @(posedge output_clk) begin
end
if (read) begin
{output_axis_tlast_reg, output_axis_tkeep_reg, output_axis_tdata_reg} <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]];
mem_read_data_reg <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]];
end
end

15
rtl/axis_fifo.v
View File

@ -61,11 +61,10 @@ reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next;
reg [DATA_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0];
reg [DATA_WIDTH+2-1:0] mem_read_data_reg = {DATA_WIDTH+2{1'b0}};
wire [DATA_WIDTH+2-1:0] mem_write_data;
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
reg output_axis_tlast_reg = 1'b0;
reg output_axis_tuser_reg = 1'b0;
// full when first MSB different but rest same
wire full = ((wr_ptr_reg[ADDR_WIDTH] != rd_ptr_reg[ADDR_WIDTH]) &&
@ -79,10 +78,10 @@ reg read;
assign input_axis_tready = ~full;
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg;
assign output_axis_tuser = output_axis_tuser_reg;
assign mem_write_data = {input_axis_tlast, input_axis_tuser, input_axis_tdata};
assign {output_axis_tlast, output_axis_tuser, output_axis_tdata} = mem_read_data_reg;
// Write logic
always @* begin
@ -108,7 +107,7 @@ always @(posedge clk) begin
end
if (write) begin
mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= {input_axis_tlast, input_axis_tuser, input_axis_tdata};
mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= mem_write_data;
end
end
@ -143,7 +142,7 @@ always @(posedge clk) begin
end
if (read) begin
{output_axis_tlast_reg, output_axis_tuser_reg, output_axis_tdata_reg} <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]];
mem_read_data_reg <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]];
end
end

17
rtl/axis_fifo_64.v
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@ -64,12 +64,10 @@ reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next;
reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0];
reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] mem_read_data_reg = {DATA_WIDTH+2{1'b0}};
wire [DATA_WIDTH+KEEP_WIDTH+2-1:0] mem_write_data;
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
reg output_axis_tlast_reg = 1'b0;
reg output_axis_tuser_reg = 1'b0;
// full when first MSB different but rest same
wire full = ((wr_ptr_reg[ADDR_WIDTH] != rd_ptr_reg[ADDR_WIDTH]) &&
@ -83,11 +81,10 @@ reg read;
assign input_axis_tready = ~full;
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tkeep = output_axis_tkeep_reg;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg;
assign output_axis_tuser = output_axis_tuser_reg;
assign mem_write_data = {input_axis_tlast, input_axis_tuser, input_axis_tkeep, input_axis_tdata};
assign {output_axis_tlast, output_axis_tuser, output_axis_tkeep, output_axis_tdata} = mem_read_data_reg;
// FIFO write logic
always @* begin
@ -113,7 +110,7 @@ always @(posedge clk) begin
end
if (write) begin
mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= {input_axis_tlast, input_axis_tuser, input_axis_tkeep, input_axis_tdata};
mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= mem_write_data;
end
end
@ -149,7 +146,7 @@ always @(posedge clk) begin
end
if (read) begin
{output_axis_tlast_reg, output_axis_tuser_reg, output_axis_tkeep_reg, output_axis_tdata_reg} <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]];
mem_read_data_reg <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]];
end
end

13
rtl/axis_frame_fifo.v
View File

@ -69,10 +69,10 @@ reg [ADDR_WIDTH:0] wr_ptr_cur_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_cur_next;
reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next;
reg [DATA_WIDTH+1-1:0] mem[(2**ADDR_WIDTH)-1:0];
reg [DATA_WIDTH+1-1:0] mem_read_data_reg = {DATA_WIDTH+2{1'b0}};
wire [DATA_WIDTH+1-1:0] mem_write_data;
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
reg output_axis_tlast_reg = 1'b0;
// full when first MSB different but rest same
wire full = ((wr_ptr_reg[ADDR_WIDTH] != rd_ptr_reg[ADDR_WIDTH]) &&
@ -94,9 +94,10 @@ reg good_frame_reg = 1'b0, good_frame_next;
assign input_axis_tready = (~full | DROP_WHEN_FULL);
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg;
assign mem_write_data = {input_axis_tlast, input_axis_tdata};
assign {output_axis_tlast, output_axis_tdata} = mem_read_data_reg;
assign overflow = overflow_reg;
assign bad_frame = bad_frame_reg;
@ -168,7 +169,7 @@ always @(posedge clk) begin
end
if (write) begin
mem[wr_ptr_cur_reg[ADDR_WIDTH-1:0]] <= {input_axis_tlast, input_axis_tdata};
mem[wr_ptr_cur_reg[ADDR_WIDTH-1:0]] <= mem_write_data;
end
end
@ -204,7 +205,7 @@ always @(posedge clk) begin
end
if (read) begin
{output_axis_tlast_reg, output_axis_tdata_reg} <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]];
mem_read_data_reg <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]];
end
end

15
rtl/axis_frame_fifo_64.v
View File

@ -72,11 +72,10 @@ reg [ADDR_WIDTH:0] wr_ptr_cur_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_cur_next;
reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next;
reg [DATA_WIDTH+KEEP_WIDTH+1-1:0] mem[(2**ADDR_WIDTH)-1:0];
reg [DATA_WIDTH+KEEP_WIDTH+1-1:0] mem_read_data_reg = {DATA_WIDTH+2{1'b0}};
wire [DATA_WIDTH+KEEP_WIDTH+1-1:0] mem_write_data;
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
reg output_axis_tlast_reg = 1'b0;
// full when first MSB different but rest same
wire full = ((wr_ptr_reg[ADDR_WIDTH] != rd_ptr_reg[ADDR_WIDTH]) &&
@ -98,10 +97,10 @@ reg good_frame_reg = 1'b0, good_frame_next;
assign input_axis_tready = (~full | DROP_WHEN_FULL);
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tkeep = output_axis_tkeep_reg;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg;
assign mem_write_data = {input_axis_tlast, input_axis_tkeep, input_axis_tdata};
assign {output_axis_tlast, output_axis_tkeep, output_axis_tdata} = mem_read_data_reg;
assign overflow = overflow_reg;
assign bad_frame = bad_frame_reg;
@ -173,7 +172,7 @@ always @(posedge clk) begin
end
if (write) begin
mem[wr_ptr_cur_reg[ADDR_WIDTH-1:0]] <= {input_axis_tlast, input_axis_tkeep, input_axis_tdata};
mem[wr_ptr_cur_reg[ADDR_WIDTH-1:0]] <= mem_write_data;
end
end
@ -208,7 +207,7 @@ always @(posedge clk) begin
end
if (read) begin
{output_axis_tlast_reg, output_axis_tkeep_reg, output_axis_tdata_reg} <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]];
mem_read_data_reg <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]];
end
end