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https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-14 06:43:18 +08:00
Add short packet tests
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88badf13f0
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@ -500,6 +500,27 @@ def bench():
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yield delay(100)
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yield s_clk.posedge
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print("test 11: many small packets")
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current_test.next = 11
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test_frame = axis_ep.AXIStreamFrame(
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b'\xAA',
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id=11,
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dest=1
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)
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for k in range(64):
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source.send(test_frame)
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for k in range(64):
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yield sink.wait()
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rx_frame = sink.recv()
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assert rx_frame == test_frame
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yield delay(100)
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raise StopSimulation
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return instances()
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@ -500,6 +500,27 @@ def bench():
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yield delay(100)
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yield s_clk.posedge
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print("test 11: many small packets")
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current_test.next = 11
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test_frame = axis_ep.AXIStreamFrame(
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b'\xAA',
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id=11,
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dest=1
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)
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for k in range(64):
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source.send(test_frame)
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for k in range(64):
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yield sink.wait()
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rx_frame = sink.recv()
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assert rx_frame == test_frame
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yield delay(100)
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raise StopSimulation
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return instances()
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@ -668,6 +668,27 @@ def bench():
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yield delay(100)
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yield s_clk.posedge
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print("test 12: many small packets")
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current_test.next = 12
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test_frame = axis_ep.AXIStreamFrame(
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b'\xAA',
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id=12,
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dest=1
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)
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for k in range(64):
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source.send(test_frame)
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for k in range(64):
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yield sink.wait()
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rx_frame = sink.recv()
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assert rx_frame == test_frame
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yield delay(100)
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raise StopSimulation
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return instances()
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@ -668,6 +668,27 @@ def bench():
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yield delay(100)
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yield s_clk.posedge
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print("test 12: many small packets")
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current_test.next = 12
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test_frame = axis_ep.AXIStreamFrame(
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b'\xAA',
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id=12,
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dest=1
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)
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for k in range(64):
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source.send(test_frame)
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for k in range(64):
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yield sink.wait()
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rx_frame = sink.recv()
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assert rx_frame == test_frame
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yield delay(100)
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raise StopSimulation
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return instances()
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@ -489,6 +489,27 @@ def bench():
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yield delay(100)
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yield clk.posedge
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print("test 11: many small packets")
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current_test.next = 11
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test_frame = axis_ep.AXIStreamFrame(
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b'\xAA',
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id=11,
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dest=1
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)
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for k in range(64):
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source.send(test_frame)
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for k in range(64):
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yield sink.wait()
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rx_frame = sink.recv()
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assert rx_frame == test_frame
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yield delay(100)
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raise StopSimulation
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return instances()
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@ -489,6 +489,27 @@ def bench():
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yield delay(100)
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yield clk.posedge
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print("test 11: many small packets")
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current_test.next = 11
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test_frame = axis_ep.AXIStreamFrame(
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b'\xAA',
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id=11,
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dest=1
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)
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for k in range(64):
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source.send(test_frame)
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for k in range(64):
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yield sink.wait()
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rx_frame = sink.recv()
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assert rx_frame == test_frame
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yield delay(100)
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raise StopSimulation
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return instances()
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@ -594,6 +594,27 @@ def bench():
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yield delay(100)
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yield clk.posedge
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print("test 12: many small packets")
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current_test.next = 12
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test_frame = axis_ep.AXIStreamFrame(
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b'\xAA',
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id=12,
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dest=1
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)
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for k in range(64):
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source.send(test_frame)
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for k in range(64):
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yield sink.wait()
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rx_frame = sink.recv()
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assert rx_frame == test_frame
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yield delay(100)
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raise StopSimulation
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return instances()
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@ -594,6 +594,27 @@ def bench():
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yield delay(100)
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yield clk.posedge
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print("test 12: many small packets")
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current_test.next = 12
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test_frame = axis_ep.AXIStreamFrame(
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b'\xAA',
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id=12,
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dest=1
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)
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for k in range(64):
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source.send(test_frame)
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for k in range(64):
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yield sink.wait()
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rx_frame = sink.recv()
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assert rx_frame == test_frame
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yield delay(100)
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raise StopSimulation
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return instances()
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