From 3bd7be44fa6775151c038e6aebf3f03e043e5254 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Thu, 18 Jul 2019 16:25:49 -0700 Subject: [PATCH] Update FIFO instances and update MACs to use combined FIFO adapter module --- rtl/eth_mac_10g_fifo.v | 110 +++++++++++++++------------- rtl/eth_mac_1g_fifo.v | 117 +++++++++++++++-------------- rtl/eth_mac_1g_gmii_fifo.v | 113 +++++++++++++++------------- rtl/eth_mac_1g_rgmii_fifo.v | 109 ++++++++++++++------------- rtl/eth_mac_mii_fifo.v | 107 ++++++++++++++------------- rtl/eth_mac_phy_10g_fifo.v | 122 ++++++++++++++++--------------- rtl/udp.v | 8 +- rtl/udp_64.v | 8 +- rtl/udp_checksum_gen.v | 8 +- rtl/udp_checksum_gen_64.v | 8 +- rtl/udp_complete.v | 8 +- rtl/udp_complete_64.v | 8 +- tb/test_eth_mac_10g_fifo_32.py | 23 ++++-- tb/test_eth_mac_10g_fifo_32.v | 36 ++++++--- tb/test_eth_mac_10g_fifo_64.py | 23 ++++-- tb/test_eth_mac_10g_fifo_64.v | 36 ++++++--- tb/test_eth_mac_1g_fifo.py | 26 +++++-- tb/test_eth_mac_1g_fifo.v | 36 +++++++-- tb/test_eth_mac_1g_gmii_fifo.py | 26 +++++-- tb/test_eth_mac_1g_gmii_fifo.v | 36 +++++++-- tb/test_eth_mac_1g_rgmii_fifo.py | 22 +++++- tb/test_eth_mac_1g_rgmii_fifo.v | 36 +++++++-- tb/test_eth_mac_mii_fifo.py | 26 +++++-- tb/test_eth_mac_mii_fifo.v | 36 +++++++-- tb/test_eth_mac_phy_10g_fifo.py | 22 +++--- tb/test_eth_mac_phy_10g_fifo.v | 26 ++++--- tb/test_udp.py | 4 + tb/test_udp.v | 8 +- tb/test_udp_64.py | 4 + tb/test_udp_64.v | 8 +- tb/test_udp_checksum_gen.py | 4 +- tb/test_udp_checksum_gen.v | 8 +- tb/test_udp_checksum_gen_64.py | 4 +- tb/test_udp_checksum_gen_64.v | 8 +- tb/test_udp_complete.py | 9 +++ tb/test_udp_complete.v | 8 +- tb/test_udp_complete_64.py | 9 +++ tb/test_udp_complete_64.v | 8 +- 38 files changed, 759 insertions(+), 459 deletions(-) diff --git a/rtl/eth_mac_10g_fifo.v b/rtl/eth_mac_10g_fifo.v index 66f812a9..77461072 100644 --- a/rtl/eth_mac_10g_fifo.v +++ b/rtl/eth_mac_10g_fifo.v @@ -32,75 +32,79 @@ THE SOFTWARE. module eth_mac_10g_fifo # ( parameter DATA_WIDTH = 64, - parameter KEEP_WIDTH = (DATA_WIDTH/8), parameter CTRL_WIDTH = (DATA_WIDTH/8), + parameter AXIS_DATA_WIDTH = DATA_WIDTH, + parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8), + parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8), parameter ENABLE_PADDING = 1, parameter ENABLE_DIC = 1, parameter MIN_FRAME_LENGTH = 64, - parameter TX_FIFO_ADDR_WIDTH = 12-$clog2(KEEP_WIDTH), + parameter TX_FIFO_DEPTH = 4096, parameter TX_FRAME_FIFO = 1, parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO, parameter TX_DROP_WHEN_FULL = 0, - parameter RX_FIFO_ADDR_WIDTH = 12-$clog2(KEEP_WIDTH), + parameter RX_FIFO_DEPTH = 4096, parameter RX_FRAME_FIFO = 1, parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO, parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO ) ( - input wire rx_clk, - input wire rx_rst, - input wire tx_clk, - input wire tx_rst, - input wire logic_clk, - input wire logic_rst, + input wire rx_clk, + input wire rx_rst, + input wire tx_clk, + input wire tx_rst, + input wire logic_clk, + input wire logic_rst, /* * AXI input */ - input wire [DATA_WIDTH-1:0] tx_axis_tdata, - input wire [KEEP_WIDTH-1:0] tx_axis_tkeep, - input wire tx_axis_tvalid, - output wire tx_axis_tready, - input wire tx_axis_tlast, - input wire tx_axis_tuser, + input wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata, + input wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep, + input wire tx_axis_tvalid, + output wire tx_axis_tready, + input wire tx_axis_tlast, + input wire tx_axis_tuser, /* * AXI output */ - output wire [DATA_WIDTH-1:0] rx_axis_tdata, - output wire [KEEP_WIDTH-1:0] rx_axis_tkeep, - output wire rx_axis_tvalid, - input wire rx_axis_tready, - output wire rx_axis_tlast, - output wire rx_axis_tuser, + output wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata, + output wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep, + output wire rx_axis_tvalid, + input wire rx_axis_tready, + output wire rx_axis_tlast, + output wire rx_axis_tuser, /* * XGMII interface */ - input wire [DATA_WIDTH-1:0] xgmii_rxd, - input wire [CTRL_WIDTH-1:0] xgmii_rxc, - output wire [DATA_WIDTH-1:0] xgmii_txd, - output wire [CTRL_WIDTH-1:0] xgmii_txc, + input wire [DATA_WIDTH-1:0] xgmii_rxd, + input wire [CTRL_WIDTH-1:0] xgmii_rxc, + output wire [DATA_WIDTH-1:0] xgmii_txd, + output wire [CTRL_WIDTH-1:0] xgmii_txc, /* * Status */ - output wire tx_error_underflow, - output wire tx_fifo_overflow, - output wire tx_fifo_bad_frame, - output wire tx_fifo_good_frame, - output wire rx_error_bad_frame, - output wire rx_error_bad_fcs, - output wire rx_fifo_overflow, - output wire rx_fifo_bad_frame, - output wire rx_fifo_good_frame, + output wire tx_error_underflow, + output wire tx_fifo_overflow, + output wire tx_fifo_bad_frame, + output wire tx_fifo_good_frame, + output wire rx_error_bad_frame, + output wire rx_error_bad_fcs, + output wire rx_fifo_overflow, + output wire rx_fifo_bad_frame, + output wire rx_fifo_good_frame, /* * Configuration */ - input wire [7:0] ifg_delay + input wire [7:0] ifg_delay ); +parameter KEEP_WIDTH = DATA_WIDTH/8; + wire [DATA_WIDTH-1:0] tx_fifo_axis_tdata; wire [KEEP_WIDTH-1:0] tx_fifo_axis_tkeep; wire tx_fifo_axis_tvalid; @@ -209,12 +213,14 @@ eth_mac_10g_inst ( .ifg_delay(ifg_delay) ); -axis_async_fifo #( - .ADDR_WIDTH(TX_FIFO_ADDR_WIDTH), - .DATA_WIDTH(DATA_WIDTH), - .KEEP_ENABLE(1), - .KEEP_WIDTH(KEEP_WIDTH), - .LAST_ENABLE(1), +axis_async_fifo_adapter #( + .DEPTH(TX_FIFO_DEPTH), + .S_DATA_WIDTH(AXIS_DATA_WIDTH), + .S_KEEP_ENABLE(AXIS_KEEP_ENABLE), + .S_KEEP_WIDTH(AXIS_KEEP_WIDTH), + .M_DATA_WIDTH(DATA_WIDTH), + .M_KEEP_ENABLE(1), + .M_KEEP_WIDTH(KEEP_WIDTH), .ID_ENABLE(0), .DEST_ENABLE(0), .USER_ENABLE(1), @@ -226,10 +232,9 @@ axis_async_fifo #( .DROP_WHEN_FULL(TX_DROP_WHEN_FULL) ) tx_fifo ( - // Common reset - .async_rst(logic_rst | tx_rst), // AXI input .s_clk(logic_clk), + .s_rst(logic_rst), .s_axis_tdata(tx_axis_tdata), .s_axis_tkeep(tx_axis_tkeep), .s_axis_tvalid(tx_axis_tvalid), @@ -240,6 +245,7 @@ tx_fifo ( .s_axis_tuser(tx_axis_tuser), // AXI output .m_clk(tx_clk), + .m_rst(tx_rst), .m_axis_tdata(tx_fifo_axis_tdata), .m_axis_tkeep(tx_fifo_axis_tkeep), .m_axis_tvalid(tx_fifo_axis_tvalid), @@ -257,12 +263,14 @@ tx_fifo ( .m_status_good_frame() ); -axis_async_fifo #( - .ADDR_WIDTH(RX_FIFO_ADDR_WIDTH), - .DATA_WIDTH(DATA_WIDTH), - .KEEP_ENABLE(1), - .KEEP_WIDTH(KEEP_WIDTH), - .LAST_ENABLE(1), +axis_async_fifo_adapter #( + .DEPTH(RX_FIFO_DEPTH), + .S_DATA_WIDTH(DATA_WIDTH), + .S_KEEP_ENABLE(1), + .S_KEEP_WIDTH(KEEP_WIDTH), + .M_DATA_WIDTH(AXIS_DATA_WIDTH), + .M_KEEP_ENABLE(AXIS_KEEP_ENABLE), + .M_KEEP_WIDTH(AXIS_KEEP_WIDTH), .ID_ENABLE(0), .DEST_ENABLE(0), .USER_ENABLE(1), @@ -274,10 +282,9 @@ axis_async_fifo #( .DROP_WHEN_FULL(RX_DROP_WHEN_FULL) ) rx_fifo ( - // Common reset - .async_rst(rx_rst | logic_rst), // AXI input .s_clk(rx_clk), + .s_rst(rx_rst), .s_axis_tdata(rx_fifo_axis_tdata), .s_axis_tkeep(rx_fifo_axis_tkeep), .s_axis_tvalid(rx_fifo_axis_tvalid), @@ -288,6 +295,7 @@ rx_fifo ( .s_axis_tuser(rx_fifo_axis_tuser), // AXI output .m_clk(logic_clk), + .m_rst(logic_rst), .m_axis_tdata(rx_axis_tdata), .m_axis_tkeep(rx_axis_tkeep), .m_axis_tvalid(rx_axis_tvalid), diff --git a/rtl/eth_mac_1g_fifo.v b/rtl/eth_mac_1g_fifo.v index b96c5a86..0110bbdd 100644 --- a/rtl/eth_mac_1g_fifo.v +++ b/rtl/eth_mac_1g_fifo.v @@ -31,78 +31,83 @@ THE SOFTWARE. */ module eth_mac_1g_fifo # ( + parameter AXIS_DATA_WIDTH = 8, + parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8), + parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8), parameter ENABLE_PADDING = 1, parameter MIN_FRAME_LENGTH = 64, - parameter TX_FIFO_ADDR_WIDTH = 12, + parameter TX_FIFO_DEPTH = 4096, parameter TX_FRAME_FIFO = 1, parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO, parameter TX_DROP_WHEN_FULL = 0, - parameter RX_FIFO_ADDR_WIDTH = 12, + parameter RX_FIFO_DEPTH = 4096, parameter RX_FRAME_FIFO = 1, parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO, parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO ) ( - input wire rx_clk, - input wire rx_rst, - input wire tx_clk, - input wire tx_rst, - input wire logic_clk, - input wire logic_rst, + input wire rx_clk, + input wire rx_rst, + input wire tx_clk, + input wire tx_rst, + input wire logic_clk, + input wire logic_rst, /* * AXI input */ - input wire [7:0] tx_axis_tdata, - input wire tx_axis_tvalid, - output wire tx_axis_tready, - input wire tx_axis_tlast, - input wire tx_axis_tuser, + input wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata, + input wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep, + input wire tx_axis_tvalid, + output wire tx_axis_tready, + input wire tx_axis_tlast, + input wire tx_axis_tuser, /* * AXI output */ - output wire [7:0] rx_axis_tdata, - output wire rx_axis_tvalid, - input wire rx_axis_tready, - output wire rx_axis_tlast, - output wire rx_axis_tuser, + output wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata, + output wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep, + output wire rx_axis_tvalid, + input wire rx_axis_tready, + output wire rx_axis_tlast, + output wire rx_axis_tuser, /* * GMII interface */ - input wire [7:0] gmii_rxd, - input wire gmii_rx_dv, - input wire gmii_rx_er, - output wire [7:0] gmii_txd, - output wire gmii_tx_en, - output wire gmii_tx_er, + input wire [7:0] gmii_rxd, + input wire gmii_rx_dv, + input wire gmii_rx_er, + output wire [7:0] gmii_txd, + output wire gmii_tx_en, + output wire gmii_tx_er, /* * Control */ - input wire rx_clk_enable, - input wire tx_clk_enable, - input wire rx_mii_select, - input wire tx_mii_select, + input wire rx_clk_enable, + input wire tx_clk_enable, + input wire rx_mii_select, + input wire tx_mii_select, /* * Status */ - output wire tx_error_underflow, - output wire tx_fifo_overflow, - output wire tx_fifo_bad_frame, - output wire tx_fifo_good_frame, - output wire rx_error_bad_frame, - output wire rx_error_bad_fcs, - output wire rx_fifo_overflow, - output wire rx_fifo_bad_frame, - output wire rx_fifo_good_frame, + output wire tx_error_underflow, + output wire tx_fifo_overflow, + output wire tx_fifo_bad_frame, + output wire tx_fifo_good_frame, + output wire rx_error_bad_frame, + output wire rx_error_bad_fcs, + output wire rx_fifo_overflow, + output wire rx_fifo_bad_frame, + output wire rx_fifo_good_frame, /* * Configuration */ - input wire [7:0] ifg_delay + input wire [7:0] ifg_delay ); wire [7:0] tx_fifo_axis_tdata; @@ -211,11 +216,13 @@ eth_mac_1g_inst ( .ifg_delay(ifg_delay) ); -axis_async_fifo #( - .ADDR_WIDTH(TX_FIFO_ADDR_WIDTH), - .DATA_WIDTH(8), - .KEEP_ENABLE(0), - .LAST_ENABLE(1), +axis_async_fifo_adapter #( + .DEPTH(TX_FIFO_DEPTH), + .S_DATA_WIDTH(AXIS_DATA_WIDTH), + .S_KEEP_ENABLE(AXIS_KEEP_ENABLE), + .S_KEEP_WIDTH(AXIS_KEEP_WIDTH), + .M_DATA_WIDTH(8), + .M_KEEP_ENABLE(0), .ID_ENABLE(0), .DEST_ENABLE(0), .USER_ENABLE(1), @@ -227,12 +234,11 @@ axis_async_fifo #( .DROP_WHEN_FULL(TX_DROP_WHEN_FULL) ) tx_fifo ( - // Common reset - .async_rst(logic_rst | tx_rst), // AXI input .s_clk(logic_clk), + .s_rst(logic_rst), .s_axis_tdata(tx_axis_tdata), - .s_axis_tkeep(0), + .s_axis_tkeep(tx_axis_tkeep), .s_axis_tvalid(tx_axis_tvalid), .s_axis_tready(tx_axis_tready), .s_axis_tlast(tx_axis_tlast), @@ -241,6 +247,7 @@ tx_fifo ( .s_axis_tuser(tx_axis_tuser), // AXI output .m_clk(tx_clk), + .m_rst(tx_rst), .m_axis_tdata(tx_fifo_axis_tdata), .m_axis_tkeep(), .m_axis_tvalid(tx_fifo_axis_tvalid), @@ -258,11 +265,13 @@ tx_fifo ( .m_status_good_frame() ); -axis_async_fifo #( - .ADDR_WIDTH(RX_FIFO_ADDR_WIDTH), - .DATA_WIDTH(8), - .KEEP_ENABLE(0), - .LAST_ENABLE(1), +axis_async_fifo_adapter #( + .DEPTH(RX_FIFO_DEPTH), + .S_DATA_WIDTH(8), + .S_KEEP_ENABLE(0), + .M_DATA_WIDTH(AXIS_DATA_WIDTH), + .M_KEEP_ENABLE(AXIS_KEEP_ENABLE), + .M_KEEP_WIDTH(AXIS_KEEP_WIDTH), .ID_ENABLE(0), .DEST_ENABLE(0), .USER_ENABLE(1), @@ -274,10 +283,9 @@ axis_async_fifo #( .DROP_WHEN_FULL(TX_DROP_WHEN_FULL) ) rx_fifo ( - // Common reset - .async_rst(rx_rst | logic_rst), // AXI input .s_clk(rx_clk), + .s_rst(rx_rst), .s_axis_tdata(rx_fifo_axis_tdata), .s_axis_tkeep(0), .s_axis_tvalid(rx_fifo_axis_tvalid), @@ -288,8 +296,9 @@ rx_fifo ( .s_axis_tuser(rx_fifo_axis_tuser), // AXI output .m_clk(logic_clk), + .m_rst(logic_rst), .m_axis_tdata(rx_axis_tdata), - .m_axis_tkeep(), + .m_axis_tkeep(rx_axis_tkeep), .m_axis_tvalid(rx_axis_tvalid), .m_axis_tready(rx_axis_tready), .m_axis_tlast(rx_axis_tlast), diff --git a/rtl/eth_mac_1g_gmii_fifo.v b/rtl/eth_mac_1g_gmii_fifo.v index dc853732..845aad57 100644 --- a/rtl/eth_mac_1g_gmii_fifo.v +++ b/rtl/eth_mac_1g_gmii_fifo.v @@ -42,72 +42,77 @@ module eth_mac_1g_gmii_fifo # // Use BUFG for Ultrascale // Use BUFIO2 for Spartan-6 parameter CLOCK_INPUT_STYLE = "BUFIO2", + parameter AXIS_DATA_WIDTH = 8, + parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8), + parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8), parameter ENABLE_PADDING = 1, parameter MIN_FRAME_LENGTH = 64, - parameter TX_FIFO_ADDR_WIDTH = 12, + parameter TX_FIFO_DEPTH = 4096, parameter TX_FRAME_FIFO = 1, parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO, parameter TX_DROP_WHEN_FULL = 0, - parameter RX_FIFO_ADDR_WIDTH = 12, + parameter RX_FIFO_DEPTH = 4096, parameter RX_FRAME_FIFO = 1, parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO, parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO ) ( - input wire gtx_clk, - input wire gtx_rst, - input wire logic_clk, - input wire logic_rst, + input wire gtx_clk, + input wire gtx_rst, + input wire logic_clk, + input wire logic_rst, /* * AXI input */ - input wire [7:0] tx_axis_tdata, - input wire tx_axis_tvalid, - output wire tx_axis_tready, - input wire tx_axis_tlast, - input wire tx_axis_tuser, + input wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata, + input wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep, + input wire tx_axis_tvalid, + output wire tx_axis_tready, + input wire tx_axis_tlast, + input wire tx_axis_tuser, /* * AXI output */ - output wire [7:0] rx_axis_tdata, - output wire rx_axis_tvalid, - input wire rx_axis_tready, - output wire rx_axis_tlast, - output wire rx_axis_tuser, + output wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata, + output wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep, + output wire rx_axis_tvalid, + input wire rx_axis_tready, + output wire rx_axis_tlast, + output wire rx_axis_tuser, /* * GMII interface */ - input wire gmii_rx_clk, - input wire [7:0] gmii_rxd, - input wire gmii_rx_dv, - input wire gmii_rx_er, - input wire mii_tx_clk, - output wire gmii_tx_clk, - output wire [7:0] gmii_txd, - output wire gmii_tx_en, - output wire gmii_tx_er, + input wire gmii_rx_clk, + input wire [7:0] gmii_rxd, + input wire gmii_rx_dv, + input wire gmii_rx_er, + input wire mii_tx_clk, + output wire gmii_tx_clk, + output wire [7:0] gmii_txd, + output wire gmii_tx_en, + output wire gmii_tx_er, /* * Status */ - output wire tx_error_underflow, - output wire tx_fifo_overflow, - output wire tx_fifo_bad_frame, - output wire tx_fifo_good_frame, - output wire rx_error_bad_frame, - output wire rx_error_bad_fcs, - output wire rx_fifo_overflow, - output wire rx_fifo_bad_frame, - output wire rx_fifo_good_frame, - output wire [1:0] speed, + output wire tx_error_underflow, + output wire tx_fifo_overflow, + output wire tx_fifo_bad_frame, + output wire tx_fifo_good_frame, + output wire rx_error_bad_frame, + output wire rx_error_bad_fcs, + output wire rx_fifo_overflow, + output wire rx_fifo_bad_frame, + output wire rx_fifo_good_frame, + output wire [1:0] speed, /* * Configuration */ - input wire [7:0] ifg_delay + input wire [7:0] ifg_delay ); wire tx_clk; @@ -238,11 +243,13 @@ eth_mac_1g_gmii_inst ( .ifg_delay(ifg_delay) ); -axis_async_fifo #( - .ADDR_WIDTH(TX_FIFO_ADDR_WIDTH), - .DATA_WIDTH(8), - .KEEP_ENABLE(0), - .LAST_ENABLE(1), +axis_async_fifo_adapter #( + .DEPTH(TX_FIFO_DEPTH), + .S_DATA_WIDTH(AXIS_DATA_WIDTH), + .S_KEEP_ENABLE(AXIS_KEEP_ENABLE), + .S_KEEP_WIDTH(AXIS_KEEP_WIDTH), + .M_DATA_WIDTH(8), + .M_KEEP_ENABLE(0), .ID_ENABLE(0), .DEST_ENABLE(0), .USER_ENABLE(1), @@ -254,12 +261,11 @@ axis_async_fifo #( .DROP_WHEN_FULL(TX_DROP_WHEN_FULL) ) tx_fifo ( - // Common reset - .async_rst(logic_rst | tx_rst), // AXI input .s_clk(logic_clk), + .s_rst(logic_rst), .s_axis_tdata(tx_axis_tdata), - .s_axis_tkeep(0), + .s_axis_tkeep(tx_axis_tkeep), .s_axis_tvalid(tx_axis_tvalid), .s_axis_tready(tx_axis_tready), .s_axis_tlast(tx_axis_tlast), @@ -268,6 +274,7 @@ tx_fifo ( .s_axis_tuser(tx_axis_tuser), // AXI output .m_clk(tx_clk), + .m_rst(tx_rst), .m_axis_tdata(tx_fifo_axis_tdata), .m_axis_tkeep(), .m_axis_tvalid(tx_fifo_axis_tvalid), @@ -285,11 +292,13 @@ tx_fifo ( .m_status_good_frame() ); -axis_async_fifo #( - .ADDR_WIDTH(RX_FIFO_ADDR_WIDTH), - .DATA_WIDTH(8), - .KEEP_ENABLE(0), - .LAST_ENABLE(1), +axis_async_fifo_adapter #( + .DEPTH(RX_FIFO_DEPTH), + .S_DATA_WIDTH(8), + .S_KEEP_ENABLE(0), + .M_DATA_WIDTH(AXIS_DATA_WIDTH), + .M_KEEP_ENABLE(AXIS_KEEP_ENABLE), + .M_KEEP_WIDTH(AXIS_KEEP_WIDTH), .ID_ENABLE(0), .DEST_ENABLE(0), .USER_ENABLE(1), @@ -301,10 +310,9 @@ axis_async_fifo #( .DROP_WHEN_FULL(TX_DROP_WHEN_FULL) ) rx_fifo ( - // Common reset - .async_rst(rx_rst | logic_rst), // AXI input .s_clk(rx_clk), + .s_rst(rx_rst), .s_axis_tdata(rx_fifo_axis_tdata), .s_axis_tkeep(0), .s_axis_tvalid(rx_fifo_axis_tvalid), @@ -315,8 +323,9 @@ rx_fifo ( .s_axis_tuser(rx_fifo_axis_tuser), // AXI output .m_clk(logic_clk), + .m_rst(logic_rst), .m_axis_tdata(rx_axis_tdata), - .m_axis_tkeep(), + .m_axis_tkeep(rx_axis_tkeep), .m_axis_tvalid(rx_axis_tvalid), .m_axis_tready(rx_axis_tready), .m_axis_tlast(rx_axis_tlast), diff --git a/rtl/eth_mac_1g_rgmii_fifo.v b/rtl/eth_mac_1g_rgmii_fifo.v index ce7b8574..640dbe62 100644 --- a/rtl/eth_mac_1g_rgmii_fifo.v +++ b/rtl/eth_mac_1g_rgmii_fifo.v @@ -44,70 +44,75 @@ module eth_mac_1g_rgmii_fifo # parameter CLOCK_INPUT_STYLE = "BUFIO2", // Use 90 degree clock for RGMII transmit ("TRUE", "FALSE") parameter USE_CLK90 = "TRUE", + parameter AXIS_DATA_WIDTH = 8, + parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8), + parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8), parameter ENABLE_PADDING = 1, parameter MIN_FRAME_LENGTH = 64, - parameter TX_FIFO_ADDR_WIDTH = 12, + parameter TX_FIFO_DEPTH = 4096, parameter TX_FRAME_FIFO = 1, parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO, parameter TX_DROP_WHEN_FULL = 0, - parameter RX_FIFO_ADDR_WIDTH = 12, + parameter RX_FIFO_DEPTH = 4096, parameter RX_FRAME_FIFO = 1, parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO, parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO ) ( - input wire gtx_clk, - input wire gtx_clk90, - input wire gtx_rst, - input wire logic_clk, - input wire logic_rst, + input wire gtx_clk, + input wire gtx_clk90, + input wire gtx_rst, + input wire logic_clk, + input wire logic_rst, /* * AXI input */ - input wire [7:0] tx_axis_tdata, - input wire tx_axis_tvalid, - output wire tx_axis_tready, - input wire tx_axis_tlast, - input wire tx_axis_tuser, + input wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata, + input wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep, + input wire tx_axis_tvalid, + output wire tx_axis_tready, + input wire tx_axis_tlast, + input wire tx_axis_tuser, /* * AXI output */ - output wire [7:0] rx_axis_tdata, - output wire rx_axis_tvalid, - input wire rx_axis_tready, - output wire rx_axis_tlast, - output wire rx_axis_tuser, + output wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata, + output wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep, + output wire rx_axis_tvalid, + input wire rx_axis_tready, + output wire rx_axis_tlast, + output wire rx_axis_tuser, /* * RGMII interface */ - input wire rgmii_rx_clk, - input wire [3:0] rgmii_rxd, - input wire rgmii_rx_ctl, - output wire rgmii_tx_clk, - output wire [3:0] rgmii_txd, - output wire rgmii_tx_ctl, + input wire rgmii_rx_clk, + input wire [3:0] rgmii_rxd, + input wire rgmii_rx_ctl, + output wire rgmii_tx_clk, + output wire [3:0] rgmii_txd, + output wire rgmii_tx_ctl, /* * Status */ - output wire tx_error_underflow, - output wire tx_fifo_overflow, - output wire tx_fifo_bad_frame, - output wire tx_fifo_good_frame, - output wire rx_error_bad_frame, - output wire rx_error_bad_fcs, - output wire rx_fifo_overflow, - output wire rx_fifo_bad_frame, - output wire rx_fifo_good_frame, - output wire [1:0] speed, + output wire tx_error_underflow, + output wire tx_fifo_overflow, + output wire tx_fifo_bad_frame, + output wire tx_fifo_good_frame, + output wire rx_error_bad_frame, + output wire rx_error_bad_fcs, + output wire rx_fifo_overflow, + output wire rx_fifo_bad_frame, + output wire rx_fifo_good_frame, + output wire [1:0] speed, /* * Configuration */ - input wire [7:0] ifg_delay + input wire [7:0] ifg_delay ); wire tx_clk; @@ -237,11 +242,13 @@ eth_mac_1g_rgmii_inst ( .ifg_delay(ifg_delay) ); -axis_async_fifo #( - .ADDR_WIDTH(TX_FIFO_ADDR_WIDTH), - .DATA_WIDTH(8), - .KEEP_ENABLE(0), - .LAST_ENABLE(1), +axis_async_fifo_adapter #( + .DEPTH(TX_FIFO_DEPTH), + .S_DATA_WIDTH(AXIS_DATA_WIDTH), + .S_KEEP_ENABLE(AXIS_KEEP_ENABLE), + .S_KEEP_WIDTH(AXIS_KEEP_WIDTH), + .M_DATA_WIDTH(8), + .M_KEEP_ENABLE(0), .ID_ENABLE(0), .DEST_ENABLE(0), .USER_ENABLE(1), @@ -253,12 +260,11 @@ axis_async_fifo #( .DROP_WHEN_FULL(TX_DROP_WHEN_FULL) ) tx_fifo ( - // Common reset - .async_rst(logic_rst | tx_rst), // AXI input .s_clk(logic_clk), + .s_rst(logic_rst), .s_axis_tdata(tx_axis_tdata), - .s_axis_tkeep(0), + .s_axis_tkeep(tx_axis_tkeep), .s_axis_tvalid(tx_axis_tvalid), .s_axis_tready(tx_axis_tready), .s_axis_tlast(tx_axis_tlast), @@ -267,6 +273,7 @@ tx_fifo ( .s_axis_tuser(tx_axis_tuser), // AXI output .m_clk(tx_clk), + .m_rst(tx_rst), .m_axis_tdata(tx_fifo_axis_tdata), .m_axis_tkeep(), .m_axis_tvalid(tx_fifo_axis_tvalid), @@ -284,11 +291,13 @@ tx_fifo ( .m_status_good_frame() ); -axis_async_fifo #( - .ADDR_WIDTH(RX_FIFO_ADDR_WIDTH), - .DATA_WIDTH(8), - .KEEP_ENABLE(0), - .LAST_ENABLE(1), +axis_async_fifo_adapter #( + .DEPTH(RX_FIFO_DEPTH), + .S_DATA_WIDTH(8), + .S_KEEP_ENABLE(0), + .M_DATA_WIDTH(AXIS_DATA_WIDTH), + .M_KEEP_ENABLE(AXIS_KEEP_ENABLE), + .M_KEEP_WIDTH(AXIS_KEEP_WIDTH), .ID_ENABLE(0), .DEST_ENABLE(0), .USER_ENABLE(1), @@ -300,10 +309,9 @@ axis_async_fifo #( .DROP_WHEN_FULL(TX_DROP_WHEN_FULL) ) rx_fifo ( - // Common reset - .async_rst(rx_rst | logic_rst), // AXI input .s_clk(rx_clk), + .s_rst(rx_rst), .s_axis_tdata(rx_fifo_axis_tdata), .s_axis_tkeep(0), .s_axis_tvalid(rx_fifo_axis_tvalid), @@ -314,8 +322,9 @@ rx_fifo ( .s_axis_tuser(rx_fifo_axis_tuser), // AXI output .m_clk(logic_clk), + .m_rst(logic_rst), .m_axis_tdata(rx_axis_tdata), - .m_axis_tkeep(), + .m_axis_tkeep(rx_axis_tkeep), .m_axis_tvalid(rx_axis_tvalid), .m_axis_tready(rx_axis_tready), .m_axis_tlast(rx_axis_tlast), diff --git a/rtl/eth_mac_mii_fifo.v b/rtl/eth_mac_mii_fifo.v index 56dd9ae9..5f33c240 100644 --- a/rtl/eth_mac_mii_fifo.v +++ b/rtl/eth_mac_mii_fifo.v @@ -38,69 +38,74 @@ module eth_mac_mii_fifo # // Use BUFG for Ultrascale // Use BUFIO2 for Spartan-6 parameter CLOCK_INPUT_STYLE = "BUFIO2", + parameter AXIS_DATA_WIDTH = 8, + parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8), + parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8), parameter ENABLE_PADDING = 1, parameter MIN_FRAME_LENGTH = 64, - parameter TX_FIFO_ADDR_WIDTH = 12, + parameter TX_FIFO_DEPTH = 4096, parameter TX_FRAME_FIFO = 1, parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO, parameter TX_DROP_WHEN_FULL = 0, - parameter RX_FIFO_ADDR_WIDTH = 12, + parameter RX_FIFO_DEPTH = 4096, parameter RX_FRAME_FIFO = 1, parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO, parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO ) ( - input wire rst, - input wire logic_clk, - input wire logic_rst, + input wire rst, + input wire logic_clk, + input wire logic_rst, /* * AXI input */ - input wire [7:0] tx_axis_tdata, - input wire tx_axis_tvalid, - output wire tx_axis_tready, - input wire tx_axis_tlast, - input wire tx_axis_tuser, + input wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata, + input wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep, + input wire tx_axis_tvalid, + output wire tx_axis_tready, + input wire tx_axis_tlast, + input wire tx_axis_tuser, /* * AXI output */ - output wire [7:0] rx_axis_tdata, - output wire rx_axis_tvalid, - input wire rx_axis_tready, - output wire rx_axis_tlast, - output wire rx_axis_tuser, + output wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata, + output wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep, + output wire rx_axis_tvalid, + input wire rx_axis_tready, + output wire rx_axis_tlast, + output wire rx_axis_tuser, /* * MII interface */ - input wire mii_rx_clk, - input wire [3:0] mii_rxd, - input wire mii_rx_dv, - input wire mii_rx_er, - input wire mii_tx_clk, - output wire [3:0] mii_txd, - output wire mii_tx_en, - output wire mii_tx_er, + input wire mii_rx_clk, + input wire [3:0] mii_rxd, + input wire mii_rx_dv, + input wire mii_rx_er, + input wire mii_tx_clk, + output wire [3:0] mii_txd, + output wire mii_tx_en, + output wire mii_tx_er, /* * Status */ - output wire tx_error_underflow, - output wire tx_fifo_overflow, - output wire tx_fifo_bad_frame, - output wire tx_fifo_good_frame, - output wire rx_error_bad_frame, - output wire rx_error_bad_fcs, - output wire rx_fifo_overflow, - output wire rx_fifo_bad_frame, - output wire rx_fifo_good_frame, + output wire tx_error_underflow, + output wire tx_fifo_overflow, + output wire tx_fifo_bad_frame, + output wire tx_fifo_good_frame, + output wire rx_error_bad_frame, + output wire rx_error_bad_fcs, + output wire rx_fifo_overflow, + output wire rx_fifo_bad_frame, + output wire rx_fifo_good_frame, /* * Configuration */ - input wire [7:0] ifg_delay + input wire [7:0] ifg_delay ); wire tx_clk; @@ -215,11 +220,13 @@ eth_mac_1g_mii_inst ( .ifg_delay(ifg_delay) ); -axis_async_fifo #( - .ADDR_WIDTH(TX_FIFO_ADDR_WIDTH), - .DATA_WIDTH(8), - .KEEP_ENABLE(0), - .LAST_ENABLE(1), +axis_async_fifo_adapter #( + .DEPTH(TX_FIFO_DEPTH), + .S_DATA_WIDTH(AXIS_DATA_WIDTH), + .S_KEEP_ENABLE(AXIS_KEEP_ENABLE), + .S_KEEP_WIDTH(AXIS_KEEP_WIDTH), + .M_DATA_WIDTH(8), + .M_KEEP_ENABLE(0), .ID_ENABLE(0), .DEST_ENABLE(0), .USER_ENABLE(1), @@ -231,12 +238,11 @@ axis_async_fifo #( .DROP_WHEN_FULL(TX_DROP_WHEN_FULL) ) tx_fifo ( - // Common reset - .async_rst(logic_rst | tx_rst), // AXI input .s_clk(logic_clk), + .s_rst(logic_rst), .s_axis_tdata(tx_axis_tdata), - .s_axis_tkeep(0), + .s_axis_tkeep(tx_axis_tkeep), .s_axis_tvalid(tx_axis_tvalid), .s_axis_tready(tx_axis_tready), .s_axis_tlast(tx_axis_tlast), @@ -245,6 +251,7 @@ tx_fifo ( .s_axis_tuser(tx_axis_tuser), // AXI output .m_clk(tx_clk), + .m_rst(tx_rst), .m_axis_tdata(tx_fifo_axis_tdata), .m_axis_tkeep(), .m_axis_tvalid(tx_fifo_axis_tvalid), @@ -262,11 +269,13 @@ tx_fifo ( .m_status_good_frame() ); -axis_async_fifo #( - .ADDR_WIDTH(RX_FIFO_ADDR_WIDTH), - .DATA_WIDTH(8), - .KEEP_ENABLE(0), - .LAST_ENABLE(1), +axis_async_fifo_adapter #( + .DEPTH(RX_FIFO_DEPTH), + .S_DATA_WIDTH(8), + .S_KEEP_ENABLE(0), + .M_DATA_WIDTH(AXIS_DATA_WIDTH), + .M_KEEP_ENABLE(AXIS_KEEP_ENABLE), + .M_KEEP_WIDTH(AXIS_KEEP_WIDTH), .ID_ENABLE(0), .DEST_ENABLE(0), .USER_ENABLE(1), @@ -278,10 +287,9 @@ axis_async_fifo #( .DROP_WHEN_FULL(TX_DROP_WHEN_FULL) ) rx_fifo ( - // Common reset - .async_rst(rx_rst | logic_rst), // AXI input .s_clk(rx_clk), + .s_rst(rx_rst), .s_axis_tdata(rx_fifo_axis_tdata), .s_axis_tkeep(0), .s_axis_tvalid(rx_fifo_axis_tvalid), @@ -292,8 +300,9 @@ rx_fifo ( .s_axis_tuser(rx_fifo_axis_tuser), // AXI output .m_clk(logic_clk), + .m_rst(logic_rst), .m_axis_tdata(rx_axis_tdata), - .m_axis_tkeep(), + .m_axis_tkeep(rx_axis_tkeep), .m_axis_tvalid(rx_axis_tvalid), .m_axis_tready(rx_axis_tready), .m_axis_tlast(rx_axis_tlast), diff --git a/rtl/eth_mac_phy_10g_fifo.v b/rtl/eth_mac_phy_10g_fifo.v index 405ae374..3a4dffe8 100644 --- a/rtl/eth_mac_phy_10g_fifo.v +++ b/rtl/eth_mac_phy_10g_fifo.v @@ -32,9 +32,11 @@ THE SOFTWARE. module eth_mac_phy_10g_fifo # ( parameter DATA_WIDTH = 64, - parameter KEEP_WIDTH = (DATA_WIDTH/8), parameter CTRL_WIDTH = (DATA_WIDTH/8), parameter HDR_WIDTH = (DATA_WIDTH/32), + parameter AXIS_DATA_WIDTH = DATA_WIDTH, + parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8), + parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8), parameter ENABLE_PADDING = 1, parameter ENABLE_DIC = 1, parameter MIN_FRAME_LENGTH = 64, @@ -45,76 +47,78 @@ module eth_mac_phy_10g_fifo # parameter RX_SERDES_PIPELINE = 0, parameter SLIP_COUNT_WIDTH = 3, parameter COUNT_125US = 125000/6.4, - parameter TX_FIFO_ADDR_WIDTH = 12-$clog2(KEEP_WIDTH), + parameter TX_FIFO_DEPTH = 4096, parameter TX_FRAME_FIFO = 1, parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO, parameter TX_DROP_WHEN_FULL = 0, - parameter RX_FIFO_ADDR_WIDTH = 12-$clog2(KEEP_WIDTH), + parameter RX_FIFO_DEPTH = 4096, parameter RX_FRAME_FIFO = 1, parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO, parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO ) ( - input wire rx_clk, - input wire rx_rst, - input wire tx_clk, - input wire tx_rst, - input wire logic_clk, - input wire logic_rst, + input wire rx_clk, + input wire rx_rst, + input wire tx_clk, + input wire tx_rst, + input wire logic_clk, + input wire logic_rst, /* * AXI input */ - input wire [DATA_WIDTH-1:0] tx_axis_tdata, - input wire [KEEP_WIDTH-1:0] tx_axis_tkeep, - input wire tx_axis_tvalid, - output wire tx_axis_tready, - input wire tx_axis_tlast, - input wire tx_axis_tuser, + input wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata, + input wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep, + input wire tx_axis_tvalid, + output wire tx_axis_tready, + input wire tx_axis_tlast, + input wire tx_axis_tuser, /* * AXI output */ - output wire [DATA_WIDTH-1:0] rx_axis_tdata, - output wire [KEEP_WIDTH-1:0] rx_axis_tkeep, - output wire rx_axis_tvalid, - input wire rx_axis_tready, - output wire rx_axis_tlast, - output wire rx_axis_tuser, + output wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata, + output wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep, + output wire rx_axis_tvalid, + input wire rx_axis_tready, + output wire rx_axis_tlast, + output wire rx_axis_tuser, /* * SERDES interface */ - output wire [DATA_WIDTH-1:0] serdes_tx_data, - output wire [HDR_WIDTH-1:0] serdes_tx_hdr, - input wire [DATA_WIDTH-1:0] serdes_rx_data, - input wire [HDR_WIDTH-1:0] serdes_rx_hdr, - output wire serdes_rx_bitslip, + output wire [DATA_WIDTH-1:0] serdes_tx_data, + output wire [HDR_WIDTH-1:0] serdes_tx_hdr, + input wire [DATA_WIDTH-1:0] serdes_rx_data, + input wire [HDR_WIDTH-1:0] serdes_rx_hdr, + output wire serdes_rx_bitslip, /* * Status */ - output wire tx_error_underflow, - output wire tx_fifo_overflow, - output wire tx_fifo_bad_frame, - output wire tx_fifo_good_frame, - output wire rx_error_bad_frame, - output wire rx_error_bad_fcs, - output wire rx_bad_block, - output wire rx_block_lock, - output wire rx_high_ber, - output wire rx_fifo_overflow, - output wire rx_fifo_bad_frame, - output wire rx_fifo_good_frame, + output wire tx_error_underflow, + output wire tx_fifo_overflow, + output wire tx_fifo_bad_frame, + output wire tx_fifo_good_frame, + output wire rx_error_bad_frame, + output wire rx_error_bad_fcs, + output wire rx_bad_block, + output wire rx_block_lock, + output wire rx_high_ber, + output wire rx_fifo_overflow, + output wire rx_fifo_bad_frame, + output wire rx_fifo_good_frame, /* * Configuration */ - input wire [7:0] ifg_delay, - input wire tx_prbs31_enable, - input wire rx_prbs31_enable + input wire [7:0] ifg_delay, + input wire tx_prbs31_enable, + input wire rx_prbs31_enable ); +parameter KEEP_WIDTH = DATA_WIDTH/8; + wire [DATA_WIDTH-1:0] tx_fifo_axis_tdata; wire [KEEP_WIDTH-1:0] tx_fifo_axis_tkeep; wire tx_fifo_axis_tvalid; @@ -240,12 +244,14 @@ eth_mac_phy_10g_inst ( .rx_prbs31_enable(rx_prbs31_enable) ); -axis_async_fifo #( - .ADDR_WIDTH(TX_FIFO_ADDR_WIDTH), - .DATA_WIDTH(DATA_WIDTH), - .KEEP_ENABLE(1), - .KEEP_WIDTH(KEEP_WIDTH), - .LAST_ENABLE(1), +axis_async_fifo_adapter #( + .DEPTH(TX_FIFO_DEPTH), + .S_DATA_WIDTH(AXIS_DATA_WIDTH), + .S_KEEP_ENABLE(AXIS_KEEP_ENABLE), + .S_KEEP_WIDTH(AXIS_KEEP_WIDTH), + .M_DATA_WIDTH(DATA_WIDTH), + .M_KEEP_ENABLE(1), + .M_KEEP_WIDTH(KEEP_WIDTH), .ID_ENABLE(0), .DEST_ENABLE(0), .USER_ENABLE(1), @@ -257,10 +263,9 @@ axis_async_fifo #( .DROP_WHEN_FULL(TX_DROP_WHEN_FULL) ) tx_fifo ( - // Common reset - .async_rst(logic_rst | tx_rst), // AXI input .s_clk(logic_clk), + .s_rst(logic_rst), .s_axis_tdata(tx_axis_tdata), .s_axis_tkeep(tx_axis_tkeep), .s_axis_tvalid(tx_axis_tvalid), @@ -271,6 +276,7 @@ tx_fifo ( .s_axis_tuser(tx_axis_tuser), // AXI output .m_clk(tx_clk), + .m_rst(tx_rst), .m_axis_tdata(tx_fifo_axis_tdata), .m_axis_tkeep(tx_fifo_axis_tkeep), .m_axis_tvalid(tx_fifo_axis_tvalid), @@ -288,12 +294,14 @@ tx_fifo ( .m_status_good_frame() ); -axis_async_fifo #( - .ADDR_WIDTH(RX_FIFO_ADDR_WIDTH), - .DATA_WIDTH(DATA_WIDTH), - .KEEP_ENABLE(1), - .KEEP_WIDTH(KEEP_WIDTH), - .LAST_ENABLE(1), +axis_async_fifo_adapter #( + .DEPTH(RX_FIFO_DEPTH), + .S_DATA_WIDTH(DATA_WIDTH), + .S_KEEP_ENABLE(1), + .S_KEEP_WIDTH(KEEP_WIDTH), + .M_DATA_WIDTH(AXIS_DATA_WIDTH), + .M_KEEP_ENABLE(AXIS_KEEP_ENABLE), + .M_KEEP_WIDTH(AXIS_KEEP_WIDTH), .ID_ENABLE(0), .DEST_ENABLE(0), .USER_ENABLE(1), @@ -305,10 +313,9 @@ axis_async_fifo #( .DROP_WHEN_FULL(RX_DROP_WHEN_FULL) ) rx_fifo ( - // Common reset - .async_rst(rx_rst | logic_rst), // AXI input .s_clk(rx_clk), + .s_rst(rx_rst), .s_axis_tdata(rx_fifo_axis_tdata), .s_axis_tkeep(rx_fifo_axis_tkeep), .s_axis_tvalid(rx_fifo_axis_tvalid), @@ -319,6 +326,7 @@ rx_fifo ( .s_axis_tuser(rx_fifo_axis_tuser), // AXI output .m_clk(logic_clk), + .m_rst(logic_rst), .m_axis_tdata(rx_axis_tdata), .m_axis_tkeep(rx_axis_tkeep), .m_axis_tvalid(rx_axis_tvalid), diff --git a/rtl/udp.v b/rtl/udp.v index 94e6ad61..bca73aa4 100644 --- a/rtl/udp.v +++ b/rtl/udp.v @@ -32,8 +32,8 @@ THE SOFTWARE. module udp # ( parameter CHECKSUM_GEN_ENABLE = 1, - parameter CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH = 11, - parameter CHECKSUM_HEADER_FIFO_ADDR_WIDTH = 3 + parameter CHECKSUM_PAYLOAD_FIFO_DEPTH = 2048, + parameter CHECKSUM_HEADER_FIFO_DEPTH = 8 ) ( input wire clk, @@ -256,8 +256,8 @@ generate if (CHECKSUM_GEN_ENABLE) begin udp_checksum_gen #( - .PAYLOAD_FIFO_ADDR_WIDTH(CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH), - .HEADER_FIFO_ADDR_WIDTH(CHECKSUM_HEADER_FIFO_ADDR_WIDTH) + .PAYLOAD_FIFO_DEPTH(CHECKSUM_PAYLOAD_FIFO_DEPTH), + .HEADER_FIFO_DEPTH(CHECKSUM_HEADER_FIFO_DEPTH) ) udp_checksum_gen_inst ( .clk(clk), diff --git a/rtl/udp_64.v b/rtl/udp_64.v index 2feaff94..25393dae 100644 --- a/rtl/udp_64.v +++ b/rtl/udp_64.v @@ -32,8 +32,8 @@ THE SOFTWARE. module udp_64 # ( parameter CHECKSUM_GEN_ENABLE = 1, - parameter CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH = 11, - parameter CHECKSUM_HEADER_FIFO_ADDR_WIDTH = 3 + parameter CHECKSUM_PAYLOAD_FIFO_DEPTH = 2048, + parameter CHECKSUM_HEADER_FIFO_DEPTH = 8 ) ( input wire clk, @@ -263,8 +263,8 @@ generate if (CHECKSUM_GEN_ENABLE) begin udp_checksum_gen_64 #( - .PAYLOAD_FIFO_ADDR_WIDTH(CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH), - .HEADER_FIFO_ADDR_WIDTH(CHECKSUM_HEADER_FIFO_ADDR_WIDTH) + .PAYLOAD_FIFO_DEPTH(CHECKSUM_PAYLOAD_FIFO_DEPTH), + .HEADER_FIFO_DEPTH(CHECKSUM_HEADER_FIFO_DEPTH) ) udp_checksum_gen_64_inst ( .clk(clk), diff --git a/rtl/udp_checksum_gen.v b/rtl/udp_checksum_gen.v index 41c5f159..e6e474ca 100644 --- a/rtl/udp_checksum_gen.v +++ b/rtl/udp_checksum_gen.v @@ -31,8 +31,8 @@ THE SOFTWARE. */ module udp_checksum_gen # ( - parameter PAYLOAD_FIFO_ADDR_WIDTH = 11, - parameter HEADER_FIFO_ADDR_WIDTH = 3 + parameter PAYLOAD_FIFO_DEPTH = 2048, + parameter HEADER_FIFO_DEPTH = 8 ) ( input wire clk, @@ -138,6 +138,8 @@ header fields in parallel along with the UDP payload in a separate AXI stream. */ +parameter HEADER_FIFO_ADDR_WIDTH = $clog2(HEADER_FIFO_DEPTH); + localparam [2:0] STATE_IDLE = 3'd0, STATE_SUM_HEADER_1 = 3'd1, @@ -197,7 +199,7 @@ wire m_udp_payload_fifo_tlast; wire m_udp_payload_fifo_tuser; axis_fifo #( - .ADDR_WIDTH(PAYLOAD_FIFO_ADDR_WIDTH), + .DEPTH(PAYLOAD_FIFO_DEPTH), .DATA_WIDTH(8), .KEEP_ENABLE(0), .LAST_ENABLE(1), diff --git a/rtl/udp_checksum_gen_64.v b/rtl/udp_checksum_gen_64.v index 756c6030..9cc7b94c 100644 --- a/rtl/udp_checksum_gen_64.v +++ b/rtl/udp_checksum_gen_64.v @@ -31,8 +31,8 @@ THE SOFTWARE. */ module udp_checksum_gen_64 # ( - parameter PAYLOAD_FIFO_ADDR_WIDTH = 8, - parameter HEADER_FIFO_ADDR_WIDTH = 3 + parameter PAYLOAD_FIFO_DEPTH = 2048, + parameter HEADER_FIFO_DEPTH = 8 ) ( input wire clk, @@ -140,6 +140,8 @@ header fields in parallel along with the UDP payload in a separate AXI stream. */ +parameter HEADER_FIFO_ADDR_WIDTH = $clog2(HEADER_FIFO_DEPTH); + localparam [2:0] STATE_IDLE = 3'd0, STATE_SUM_HEADER = 3'd1, @@ -202,7 +204,7 @@ wire m_udp_payload_fifo_tlast; wire m_udp_payload_fifo_tuser; axis_fifo #( - .ADDR_WIDTH(PAYLOAD_FIFO_ADDR_WIDTH), + .DEPTH(PAYLOAD_FIFO_DEPTH), .DATA_WIDTH(64), .KEEP_ENABLE(1), .KEEP_WIDTH(8), diff --git a/rtl/udp_complete.v b/rtl/udp_complete.v index 3ff5816c..4432c909 100644 --- a/rtl/udp_complete.v +++ b/rtl/udp_complete.v @@ -35,8 +35,8 @@ module udp_complete #( parameter ARP_REQUEST_RETRY_INTERVAL = 125000000*2, parameter ARP_REQUEST_TIMEOUT = 125000000*30, parameter UDP_CHECKSUM_GEN_ENABLE = 1, - parameter UDP_CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH = 11, - parameter UDP_CHECKSUM_HEADER_FIFO_ADDR_WIDTH = 3 + parameter UDP_CHECKSUM_PAYLOAD_FIFO_DEPTH = 2048, + parameter UDP_CHECKSUM_HEADER_FIFO_DEPTH = 8 ) ( input wire clk, @@ -518,8 +518,8 @@ ip_complete_inst ( */ udp #( .CHECKSUM_GEN_ENABLE(UDP_CHECKSUM_GEN_ENABLE), - .CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH(UDP_CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH), - .CHECKSUM_HEADER_FIFO_ADDR_WIDTH(UDP_CHECKSUM_HEADER_FIFO_ADDR_WIDTH) + .CHECKSUM_PAYLOAD_FIFO_DEPTH(UDP_CHECKSUM_PAYLOAD_FIFO_DEPTH), + .CHECKSUM_HEADER_FIFO_DEPTH(UDP_CHECKSUM_HEADER_FIFO_DEPTH) ) udp_inst ( .clk(clk), diff --git a/rtl/udp_complete_64.v b/rtl/udp_complete_64.v index c31e225a..2ab69c91 100644 --- a/rtl/udp_complete_64.v +++ b/rtl/udp_complete_64.v @@ -35,8 +35,8 @@ module udp_complete_64 #( parameter ARP_REQUEST_RETRY_INTERVAL = 125000000*2, parameter ARP_REQUEST_TIMEOUT = 125000000*30, parameter UDP_CHECKSUM_GEN_ENABLE = 1, - parameter UDP_CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH = 11, - parameter UDP_CHECKSUM_HEADER_FIFO_ADDR_WIDTH = 3 + parameter UDP_CHECKSUM_PAYLOAD_FIFO_DEPTH = 2048, + parameter UDP_CHECKSUM_HEADER_FIFO_DEPTH = 8 ) ( input wire clk, @@ -534,8 +534,8 @@ ip_complete_64_inst ( */ udp_64 #( .CHECKSUM_GEN_ENABLE(UDP_CHECKSUM_GEN_ENABLE), - .CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH(UDP_CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH), - .CHECKSUM_HEADER_FIFO_ADDR_WIDTH(UDP_CHECKSUM_HEADER_FIFO_ADDR_WIDTH) + .CHECKSUM_PAYLOAD_FIFO_DEPTH(UDP_CHECKSUM_PAYLOAD_FIFO_DEPTH), + .CHECKSUM_HEADER_FIFO_DEPTH(UDP_CHECKSUM_HEADER_FIFO_DEPTH) ) udp_64_inst ( .clk(clk), diff --git a/tb/test_eth_mac_10g_fifo_32.py b/tb/test_eth_mac_10g_fifo_32.py index 0488c8a3..16688f34 100755 --- a/tb/test_eth_mac_10g_fifo_32.py +++ b/tb/test_eth_mac_10g_fifo_32.py @@ -41,6 +41,7 @@ srcs.append("../rtl/axis_xgmii_rx_32.v") srcs.append("../rtl/axis_xgmii_tx_32.v") srcs.append("../rtl/eth_mac_10g.v") srcs.append("../lib/axis/rtl/axis_async_fifo.v") +srcs.append("../lib/axis/rtl/axis_async_fifo_adapter.v") srcs.append("%s.v" % testbench) src = ' '.join(srcs) @@ -51,13 +52,21 @@ def bench(): # Parameters DATA_WIDTH = 32 - KEEP_WIDTH = (DATA_WIDTH/8) CTRL_WIDTH = (DATA_WIDTH/8) + AXIS_DATA_WIDTH = DATA_WIDTH + AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8) + AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8) ENABLE_PADDING = 1 ENABLE_DIC = 1 MIN_FRAME_LENGTH = 64 - TX_FIFO_ADDR_WIDTH = 9 - RX_FIFO_ADDR_WIDTH = 9 + TX_FIFO_DEPTH = 4096 + TX_FRAME_FIFO = 1 + TX_DROP_BAD_FRAME = TX_FRAME_FIFO + TX_DROP_WHEN_FULL = 0 + RX_FIFO_DEPTH = 4096 + RX_FRAME_FIFO = 1 + RX_DROP_BAD_FRAME = RX_FRAME_FIFO + RX_DROP_WHEN_FULL = RX_FRAME_FIFO # Inputs clk = Signal(bool(0)) @@ -70,8 +79,8 @@ def bench(): tx_rst = Signal(bool(0)) logic_clk = Signal(bool(0)) logic_rst = Signal(bool(0)) - tx_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) - tx_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) + tx_axis_tdata = Signal(intbv(0)[AXIS_DATA_WIDTH:]) + tx_axis_tkeep = Signal(intbv(0)[AXIS_KEEP_WIDTH:]) tx_axis_tvalid = Signal(bool(0)) tx_axis_tlast = Signal(bool(0)) tx_axis_tuser = Signal(bool(0)) @@ -82,8 +91,8 @@ def bench(): # Outputs tx_axis_tready = Signal(bool(0)) - rx_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) - rx_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) + rx_axis_tdata = Signal(intbv(0)[AXIS_DATA_WIDTH:]) + rx_axis_tkeep = Signal(intbv(0)[AXIS_KEEP_WIDTH:]) rx_axis_tvalid = Signal(bool(0)) rx_axis_tlast = Signal(bool(0)) rx_axis_tuser = Signal(bool(0)) diff --git a/tb/test_eth_mac_10g_fifo_32.v b/tb/test_eth_mac_10g_fifo_32.v index 02592b06..e27fccfb 100644 --- a/tb/test_eth_mac_10g_fifo_32.v +++ b/tb/test_eth_mac_10g_fifo_32.v @@ -33,13 +33,21 @@ module test_eth_mac_10g_fifo_32; // Parameters parameter DATA_WIDTH = 32; -parameter KEEP_WIDTH = (DATA_WIDTH/8); parameter CTRL_WIDTH = (DATA_WIDTH/8); +parameter AXIS_DATA_WIDTH = DATA_WIDTH; +parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8); +parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8); parameter ENABLE_PADDING = 1; parameter ENABLE_DIC = 1; parameter MIN_FRAME_LENGTH = 64; -parameter TX_FIFO_ADDR_WIDTH = 9; -parameter RX_FIFO_ADDR_WIDTH = 9; +parameter TX_FIFO_DEPTH = 4096; +parameter TX_FRAME_FIFO = 1; +parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO; +parameter TX_DROP_WHEN_FULL = 0; +parameter RX_FIFO_DEPTH = 4096; +parameter RX_FRAME_FIFO = 1; +parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO; +parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO; // Inputs reg clk = 0; @@ -52,8 +60,8 @@ reg tx_clk = 0; reg tx_rst = 0; reg logic_clk = 0; reg logic_rst = 0; -reg [DATA_WIDTH-1:0] tx_axis_tdata = 0; -reg [KEEP_WIDTH-1:0] tx_axis_tkeep = 0; +reg [AXIS_DATA_WIDTH-1:0] tx_axis_tdata = 0; +reg [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep = 0; reg tx_axis_tvalid = 0; reg tx_axis_tlast = 0; reg tx_axis_tuser = 0; @@ -64,8 +72,8 @@ reg [7:0] ifg_delay = 0; // Outputs wire tx_axis_tready; -wire [DATA_WIDTH-1:0] rx_axis_tdata; -wire [KEEP_WIDTH-1:0] rx_axis_tkeep; +wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata; +wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep; wire rx_axis_tvalid; wire rx_axis_tlast; wire rx_axis_tuser; @@ -130,13 +138,21 @@ end eth_mac_10g_fifo #( .DATA_WIDTH(DATA_WIDTH), - .KEEP_WIDTH(KEEP_WIDTH), .CTRL_WIDTH(CTRL_WIDTH), + .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH), + .AXIS_KEEP_ENABLE(AXIS_KEEP_ENABLE), + .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH), .ENABLE_PADDING(ENABLE_PADDING), .ENABLE_DIC(ENABLE_DIC), .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), - .TX_FIFO_ADDR_WIDTH(TX_FIFO_ADDR_WIDTH), - .RX_FIFO_ADDR_WIDTH(RX_FIFO_ADDR_WIDTH) + .TX_FIFO_DEPTH(TX_FIFO_DEPTH), + .TX_FRAME_FIFO(TX_FRAME_FIFO), + .TX_DROP_BAD_FRAME(TX_DROP_BAD_FRAME), + .TX_DROP_WHEN_FULL(TX_DROP_WHEN_FULL), + .RX_FIFO_DEPTH(RX_FIFO_DEPTH), + .RX_FRAME_FIFO(RX_FRAME_FIFO), + .RX_DROP_BAD_FRAME(RX_DROP_BAD_FRAME), + .RX_DROP_WHEN_FULL(RX_DROP_WHEN_FULL) ) UUT ( .rx_clk(rx_clk), diff --git a/tb/test_eth_mac_10g_fifo_64.py b/tb/test_eth_mac_10g_fifo_64.py index 71402866..18875e1b 100755 --- a/tb/test_eth_mac_10g_fifo_64.py +++ b/tb/test_eth_mac_10g_fifo_64.py @@ -41,6 +41,7 @@ srcs.append("../rtl/axis_xgmii_rx_64.v") srcs.append("../rtl/axis_xgmii_tx_64.v") srcs.append("../rtl/eth_mac_10g.v") srcs.append("../lib/axis/rtl/axis_async_fifo.v") +srcs.append("../lib/axis/rtl/axis_async_fifo_adapter.v") srcs.append("%s.v" % testbench) src = ' '.join(srcs) @@ -51,13 +52,21 @@ def bench(): # Parameters DATA_WIDTH = 64 - KEEP_WIDTH = (DATA_WIDTH/8) CTRL_WIDTH = (DATA_WIDTH/8) + AXIS_DATA_WIDTH = DATA_WIDTH + AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8) + AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8) ENABLE_PADDING = 1 ENABLE_DIC = 1 MIN_FRAME_LENGTH = 64 - TX_FIFO_ADDR_WIDTH = 9 - RX_FIFO_ADDR_WIDTH = 9 + TX_FIFO_DEPTH = 4096 + TX_FRAME_FIFO = 1 + TX_DROP_BAD_FRAME = TX_FRAME_FIFO + TX_DROP_WHEN_FULL = 0 + RX_FIFO_DEPTH = 4096 + RX_FRAME_FIFO = 1 + RX_DROP_BAD_FRAME = RX_FRAME_FIFO + RX_DROP_WHEN_FULL = RX_FRAME_FIFO # Inputs clk = Signal(bool(0)) @@ -70,8 +79,8 @@ def bench(): tx_rst = Signal(bool(0)) logic_clk = Signal(bool(0)) logic_rst = Signal(bool(0)) - tx_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) - tx_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) + tx_axis_tdata = Signal(intbv(0)[AXIS_DATA_WIDTH:]) + tx_axis_tkeep = Signal(intbv(0)[AXIS_KEEP_WIDTH:]) tx_axis_tvalid = Signal(bool(0)) tx_axis_tlast = Signal(bool(0)) tx_axis_tuser = Signal(bool(0)) @@ -82,8 +91,8 @@ def bench(): # Outputs tx_axis_tready = Signal(bool(0)) - rx_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) - rx_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) + rx_axis_tdata = Signal(intbv(0)[AXIS_DATA_WIDTH:]) + rx_axis_tkeep = Signal(intbv(0)[AXIS_KEEP_WIDTH:]) rx_axis_tvalid = Signal(bool(0)) rx_axis_tlast = Signal(bool(0)) rx_axis_tuser = Signal(bool(0)) diff --git a/tb/test_eth_mac_10g_fifo_64.v b/tb/test_eth_mac_10g_fifo_64.v index c035ceb0..53961a5c 100644 --- a/tb/test_eth_mac_10g_fifo_64.v +++ b/tb/test_eth_mac_10g_fifo_64.v @@ -33,13 +33,21 @@ module test_eth_mac_10g_fifo_64; // Parameters parameter DATA_WIDTH = 64; -parameter KEEP_WIDTH = (DATA_WIDTH/8); parameter CTRL_WIDTH = (DATA_WIDTH/8); +parameter AXIS_DATA_WIDTH = DATA_WIDTH; +parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8); +parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8); parameter ENABLE_PADDING = 1; parameter ENABLE_DIC = 1; parameter MIN_FRAME_LENGTH = 64; -parameter TX_FIFO_ADDR_WIDTH = 9; -parameter RX_FIFO_ADDR_WIDTH = 9; +parameter TX_FIFO_DEPTH = 4096; +parameter TX_FRAME_FIFO = 1; +parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO; +parameter TX_DROP_WHEN_FULL = 0; +parameter RX_FIFO_DEPTH = 4096; +parameter RX_FRAME_FIFO = 1; +parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO; +parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO; // Inputs reg clk = 0; @@ -52,8 +60,8 @@ reg tx_clk = 0; reg tx_rst = 0; reg logic_clk = 0; reg logic_rst = 0; -reg [DATA_WIDTH-1:0] tx_axis_tdata = 0; -reg [KEEP_WIDTH-1:0] tx_axis_tkeep = 0; +reg [AXIS_DATA_WIDTH-1:0] tx_axis_tdata = 0; +reg [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep = 0; reg tx_axis_tvalid = 0; reg tx_axis_tlast = 0; reg tx_axis_tuser = 0; @@ -64,8 +72,8 @@ reg [7:0] ifg_delay = 0; // Outputs wire tx_axis_tready; -wire [DATA_WIDTH-1:0] rx_axis_tdata; -wire [KEEP_WIDTH-1:0] rx_axis_tkeep; +wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata; +wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep; wire rx_axis_tvalid; wire rx_axis_tlast; wire rx_axis_tuser; @@ -130,13 +138,21 @@ end eth_mac_10g_fifo #( .DATA_WIDTH(DATA_WIDTH), - .KEEP_WIDTH(KEEP_WIDTH), .CTRL_WIDTH(CTRL_WIDTH), + .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH), + .AXIS_KEEP_ENABLE(AXIS_KEEP_ENABLE), + .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH), .ENABLE_PADDING(ENABLE_PADDING), .ENABLE_DIC(ENABLE_DIC), .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), - .TX_FIFO_ADDR_WIDTH(TX_FIFO_ADDR_WIDTH), - .RX_FIFO_ADDR_WIDTH(RX_FIFO_ADDR_WIDTH) + .TX_FIFO_DEPTH(TX_FIFO_DEPTH), + .TX_FRAME_FIFO(TX_FRAME_FIFO), + .TX_DROP_BAD_FRAME(TX_DROP_BAD_FRAME), + .TX_DROP_WHEN_FULL(TX_DROP_WHEN_FULL), + .RX_FIFO_DEPTH(RX_FIFO_DEPTH), + .RX_FRAME_FIFO(RX_FRAME_FIFO), + .RX_DROP_BAD_FRAME(RX_DROP_BAD_FRAME), + .RX_DROP_WHEN_FULL(RX_DROP_WHEN_FULL) ) UUT ( .rx_clk(rx_clk), diff --git a/tb/test_eth_mac_1g_fifo.py b/tb/test_eth_mac_1g_fifo.py index df1feceb..5f007433 100755 --- a/tb/test_eth_mac_1g_fifo.py +++ b/tb/test_eth_mac_1g_fifo.py @@ -41,6 +41,7 @@ srcs.append("../rtl/axis_gmii_rx.v") srcs.append("../rtl/axis_gmii_tx.v") srcs.append("../rtl/eth_mac_1g.v") srcs.append("../lib/axis/rtl/axis_async_fifo.v") +srcs.append("../lib/axis/rtl/axis_async_fifo_adapter.v") srcs.append("%s.v" % testbench) src = ' '.join(srcs) @@ -50,10 +51,19 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src) def bench(): # Parameters + AXIS_DATA_WIDTH = 8 + AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8) + AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8) ENABLE_PADDING = 1 MIN_FRAME_LENGTH = 64 - TX_FIFO_ADDR_WIDTH = 9 - RX_FIFO_ADDR_WIDTH = 9 + TX_FIFO_DEPTH = 4096 + TX_FRAME_FIFO = 1 + TX_DROP_BAD_FRAME = TX_FRAME_FIFO + TX_DROP_WHEN_FULL = 0 + RX_FIFO_DEPTH = 4096 + RX_FRAME_FIFO = 1 + RX_DROP_BAD_FRAME = RX_FRAME_FIFO + RX_DROP_WHEN_FULL = RX_FRAME_FIFO # Inputs clk = Signal(bool(0)) @@ -66,7 +76,8 @@ def bench(): tx_rst = Signal(bool(0)) logic_clk = Signal(bool(0)) logic_rst = Signal(bool(0)) - tx_axis_tdata = Signal(intbv(0)[8:]) + tx_axis_tdata = Signal(intbv(0)[AXIS_DATA_WIDTH:]) + tx_axis_tkeep = Signal(intbv(1)[AXIS_KEEP_WIDTH:]) tx_axis_tvalid = Signal(bool(0)) tx_axis_tlast = Signal(bool(0)) tx_axis_tuser = Signal(bool(0)) @@ -82,7 +93,8 @@ def bench(): # Outputs tx_axis_tready = Signal(bool(0)) - rx_axis_tdata = Signal(intbv(0)[8:]) + rx_axis_tdata = Signal(intbv(0)[AXIS_DATA_WIDTH:]) + rx_axis_tkeep = Signal(intbv(1)[AXIS_KEEP_WIDTH:]) rx_axis_tvalid = Signal(bool(0)) rx_axis_tlast = Signal(bool(0)) rx_axis_tuser = Signal(bool(0)) @@ -135,6 +147,7 @@ def bench(): logic_clk, logic_rst, tdata=tx_axis_tdata, + tkeep=tx_axis_tkeep, tvalid=tx_axis_tvalid, tready=tx_axis_tready, tlast=tx_axis_tlast, @@ -149,6 +162,7 @@ def bench(): logic_clk, logic_rst, tdata=rx_axis_tdata, + tkeep=rx_axis_tkeep, tvalid=rx_axis_tvalid, tready=rx_axis_tready, tlast=rx_axis_tlast, @@ -175,14 +189,16 @@ def bench(): logic_rst=logic_rst, tx_axis_tdata=tx_axis_tdata, + tx_axis_tkeep=tx_axis_tkeep, tx_axis_tvalid=tx_axis_tvalid, tx_axis_tready=tx_axis_tready, tx_axis_tlast=tx_axis_tlast, tx_axis_tuser=tx_axis_tuser, rx_axis_tdata=rx_axis_tdata, - rx_axis_tready=rx_axis_tready, + rx_axis_tkeep=rx_axis_tkeep, rx_axis_tvalid=rx_axis_tvalid, + rx_axis_tready=rx_axis_tready, rx_axis_tlast=rx_axis_tlast, rx_axis_tuser=rx_axis_tuser, diff --git a/tb/test_eth_mac_1g_fifo.v b/tb/test_eth_mac_1g_fifo.v index ea7e9cca..67d42248 100644 --- a/tb/test_eth_mac_1g_fifo.v +++ b/tb/test_eth_mac_1g_fifo.v @@ -32,10 +32,19 @@ THE SOFTWARE. module test_eth_mac_1g_fifo; // Parameters +parameter AXIS_DATA_WIDTH = 8; +parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8); +parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8); parameter ENABLE_PADDING = 1; parameter MIN_FRAME_LENGTH = 64; -parameter TX_FIFO_ADDR_WIDTH = 9; -parameter RX_FIFO_ADDR_WIDTH = 9; +parameter TX_FIFO_DEPTH = 4096; +parameter TX_FRAME_FIFO = 1; +parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO; +parameter TX_DROP_WHEN_FULL = 0; +parameter RX_FIFO_DEPTH = 4096; +parameter RX_FRAME_FIFO = 1; +parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO; +parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO; // Inputs reg clk = 0; @@ -48,7 +57,8 @@ reg tx_clk = 0; reg tx_rst = 0; reg logic_clk = 0; reg logic_rst = 0; -reg [7:0] tx_axis_tdata = 0; +reg [AXIS_DATA_WIDTH-1:0] tx_axis_tdata = 0; +reg [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep = 0; reg tx_axis_tvalid = 0; reg tx_axis_tlast = 0; reg tx_axis_tuser = 0; @@ -64,7 +74,8 @@ reg [7:0] ifg_delay = 0; // Outputs wire tx_axis_tready; -wire [7:0] rx_axis_tdata; +wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata; +wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep; wire rx_axis_tvalid; wire rx_axis_tlast; wire rx_axis_tuser; @@ -94,6 +105,7 @@ initial begin logic_clk, logic_rst, tx_axis_tdata, + tx_axis_tkeep, tx_axis_tvalid, tx_axis_tlast, tx_axis_tuser, @@ -110,6 +122,7 @@ initial begin $to_myhdl( tx_axis_tready, rx_axis_tdata, + rx_axis_tkeep, rx_axis_tvalid, rx_axis_tlast, rx_axis_tuser, @@ -133,10 +146,19 @@ initial begin end eth_mac_1g_fifo #( + .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH), + .AXIS_KEEP_ENABLE(AXIS_KEEP_ENABLE), + .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH), .ENABLE_PADDING(ENABLE_PADDING), .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), - .TX_FIFO_ADDR_WIDTH(TX_FIFO_ADDR_WIDTH), - .RX_FIFO_ADDR_WIDTH(RX_FIFO_ADDR_WIDTH) + .TX_FIFO_DEPTH(TX_FIFO_DEPTH), + .TX_FRAME_FIFO(TX_FRAME_FIFO), + .TX_DROP_BAD_FRAME(TX_DROP_BAD_FRAME), + .TX_DROP_WHEN_FULL(TX_DROP_WHEN_FULL), + .RX_FIFO_DEPTH(RX_FIFO_DEPTH), + .RX_FRAME_FIFO(RX_FRAME_FIFO), + .RX_DROP_BAD_FRAME(RX_DROP_BAD_FRAME), + .RX_DROP_WHEN_FULL(RX_DROP_WHEN_FULL) ) UUT ( .rx_clk(rx_clk), @@ -146,11 +168,13 @@ UUT ( .logic_clk(logic_clk), .logic_rst(logic_rst), .tx_axis_tdata(tx_axis_tdata), + .tx_axis_tkeep(tx_axis_tkeep), .tx_axis_tvalid(tx_axis_tvalid), .tx_axis_tready(tx_axis_tready), .tx_axis_tlast(tx_axis_tlast), .tx_axis_tuser(tx_axis_tuser), .rx_axis_tdata(rx_axis_tdata), + .rx_axis_tkeep(rx_axis_tkeep), .rx_axis_tvalid(rx_axis_tvalid), .rx_axis_tready(rx_axis_tready), .rx_axis_tlast(rx_axis_tlast), diff --git a/tb/test_eth_mac_1g_gmii_fifo.py b/tb/test_eth_mac_1g_gmii_fifo.py index fef5f144..5a4b6092 100755 --- a/tb/test_eth_mac_1g_gmii_fifo.py +++ b/tb/test_eth_mac_1g_gmii_fifo.py @@ -46,6 +46,7 @@ srcs.append("../rtl/oddr.v") srcs.append("../rtl/ssio_sdr_in.v") srcs.append("../rtl/ssio_sdr_out.v") srcs.append("../lib/axis/rtl/axis_async_fifo.v") +srcs.append("../lib/axis/rtl/axis_async_fifo_adapter.v") srcs.append("%s.v" % testbench) src = ' '.join(srcs) @@ -58,10 +59,19 @@ def bench(): TARGET = "SIM" IODDR_STYLE = "IODDR2" CLOCK_INPUT_STYLE = "BUFIO2" + AXIS_DATA_WIDTH = 8 + AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8) + AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8) ENABLE_PADDING = 1 MIN_FRAME_LENGTH = 64 - TX_FIFO_ADDR_WIDTH = 9 - RX_FIFO_ADDR_WIDTH = 9 + TX_FIFO_DEPTH = 4096 + TX_FRAME_FIFO = 1 + TX_DROP_BAD_FRAME = TX_FRAME_FIFO + TX_DROP_WHEN_FULL = 0 + RX_FIFO_DEPTH = 4096 + RX_FRAME_FIFO = 1 + RX_DROP_BAD_FRAME = RX_FRAME_FIFO + RX_DROP_WHEN_FULL = RX_FRAME_FIFO # Inputs clk = Signal(bool(0)) @@ -72,7 +82,8 @@ def bench(): gtx_rst = Signal(bool(0)) logic_clk = Signal(bool(0)) logic_rst = Signal(bool(0)) - tx_axis_tdata = Signal(intbv(0)[8:]) + tx_axis_tdata = Signal(intbv(0)[AXIS_DATA_WIDTH:]) + tx_axis_tkeep = Signal(intbv(1)[AXIS_KEEP_WIDTH:]) tx_axis_tvalid = Signal(bool(0)) tx_axis_tlast = Signal(bool(0)) tx_axis_tuser = Signal(bool(0)) @@ -86,7 +97,8 @@ def bench(): # Outputs tx_axis_tready = Signal(bool(0)) - rx_axis_tdata = Signal(intbv(0)[8:]) + rx_axis_tdata = Signal(intbv(0)[AXIS_DATA_WIDTH:]) + rx_axis_tkeep = Signal(intbv(1)[AXIS_KEEP_WIDTH:]) rx_axis_tvalid = Signal(bool(0)) rx_axis_tlast = Signal(bool(0)) rx_axis_tuser = Signal(bool(0)) @@ -141,6 +153,7 @@ def bench(): logic_clk, logic_rst, tdata=tx_axis_tdata, + tkeep=tx_axis_tkeep, tvalid=tx_axis_tvalid, tready=tx_axis_tready, tlast=tx_axis_tlast, @@ -155,6 +168,7 @@ def bench(): logic_clk, logic_rst, tdata=rx_axis_tdata, + tkeep=rx_axis_tkeep, tvalid=rx_axis_tvalid, tready=rx_axis_tready, tlast=rx_axis_tlast, @@ -179,14 +193,16 @@ def bench(): logic_rst=logic_rst, tx_axis_tdata=tx_axis_tdata, + tx_axis_tkeep=tx_axis_tkeep, tx_axis_tvalid=tx_axis_tvalid, tx_axis_tready=tx_axis_tready, tx_axis_tlast=tx_axis_tlast, tx_axis_tuser=tx_axis_tuser, rx_axis_tdata=rx_axis_tdata, - rx_axis_tready=rx_axis_tready, + rx_axis_tkeep=rx_axis_tkeep, rx_axis_tvalid=rx_axis_tvalid, + rx_axis_tready=rx_axis_tready, rx_axis_tlast=rx_axis_tlast, rx_axis_tuser=rx_axis_tuser, diff --git a/tb/test_eth_mac_1g_gmii_fifo.v b/tb/test_eth_mac_1g_gmii_fifo.v index 6c60bba7..295d30df 100644 --- a/tb/test_eth_mac_1g_gmii_fifo.v +++ b/tb/test_eth_mac_1g_gmii_fifo.v @@ -35,10 +35,19 @@ module test_eth_mac_1g_gmii_fifo; parameter TARGET = "SIM"; parameter IODDR_STYLE = "IODDR2"; parameter CLOCK_INPUT_STYLE = "BUFIO2"; +parameter AXIS_DATA_WIDTH = 8; +parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8); +parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8); parameter ENABLE_PADDING = 1; parameter MIN_FRAME_LENGTH = 64; -parameter TX_FIFO_ADDR_WIDTH = 9; -parameter RX_FIFO_ADDR_WIDTH = 9; +parameter TX_FIFO_DEPTH = 4096; +parameter TX_FRAME_FIFO = 1; +parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO; +parameter TX_DROP_WHEN_FULL = 0; +parameter RX_FIFO_DEPTH = 4096; +parameter RX_FRAME_FIFO = 1; +parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO; +parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO; // Inputs reg clk = 0; @@ -49,7 +58,8 @@ reg gtx_clk = 0; reg gtx_rst = 0; reg logic_clk = 0; reg logic_rst = 0; -reg [7:0] tx_axis_tdata = 0; +reg [AXIS_DATA_WIDTH-1:0] tx_axis_tdata = 0; +reg [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep = 0; reg tx_axis_tvalid = 0; reg tx_axis_tlast = 0; reg tx_axis_tuser = 0; @@ -63,7 +73,8 @@ reg [7:0] ifg_delay = 0; // Outputs wire tx_axis_tready; -wire [7:0] rx_axis_tdata; +wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata; +wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep; wire rx_axis_tvalid; wire rx_axis_tlast; wire rx_axis_tuser; @@ -93,6 +104,7 @@ initial begin logic_clk, logic_rst, tx_axis_tdata, + tx_axis_tkeep, tx_axis_tvalid, tx_axis_tlast, tx_axis_tuser, @@ -107,6 +119,7 @@ initial begin $to_myhdl( tx_axis_tready, rx_axis_tdata, + rx_axis_tkeep, rx_axis_tvalid, rx_axis_tlast, rx_axis_tuser, @@ -135,10 +148,19 @@ eth_mac_1g_gmii_fifo #( .TARGET(TARGET), .IODDR_STYLE(IODDR_STYLE), .CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE), + .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH), + .AXIS_KEEP_ENABLE(AXIS_KEEP_ENABLE), + .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH), .ENABLE_PADDING(ENABLE_PADDING), .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), - .TX_FIFO_ADDR_WIDTH(TX_FIFO_ADDR_WIDTH), - .RX_FIFO_ADDR_WIDTH(RX_FIFO_ADDR_WIDTH) + .TX_FIFO_DEPTH(TX_FIFO_DEPTH), + .TX_FRAME_FIFO(TX_FRAME_FIFO), + .TX_DROP_BAD_FRAME(TX_DROP_BAD_FRAME), + .TX_DROP_WHEN_FULL(TX_DROP_WHEN_FULL), + .RX_FIFO_DEPTH(RX_FIFO_DEPTH), + .RX_FRAME_FIFO(RX_FRAME_FIFO), + .RX_DROP_BAD_FRAME(RX_DROP_BAD_FRAME), + .RX_DROP_WHEN_FULL(RX_DROP_WHEN_FULL) ) UUT ( .gtx_clk(gtx_clk), @@ -146,11 +168,13 @@ UUT ( .logic_clk(logic_clk), .logic_rst(logic_rst), .tx_axis_tdata(tx_axis_tdata), + .tx_axis_tkeep(tx_axis_tkeep), .tx_axis_tvalid(tx_axis_tvalid), .tx_axis_tready(tx_axis_tready), .tx_axis_tlast(tx_axis_tlast), .tx_axis_tuser(tx_axis_tuser), .rx_axis_tdata(rx_axis_tdata), + .rx_axis_tkeep(rx_axis_tkeep), .rx_axis_tvalid(rx_axis_tvalid), .rx_axis_tready(rx_axis_tready), .rx_axis_tlast(rx_axis_tlast), diff --git a/tb/test_eth_mac_1g_rgmii_fifo.py b/tb/test_eth_mac_1g_rgmii_fifo.py index 2840402d..b1d9708f 100755 --- a/tb/test_eth_mac_1g_rgmii_fifo.py +++ b/tb/test_eth_mac_1g_rgmii_fifo.py @@ -47,6 +47,7 @@ srcs.append("../rtl/oddr.v") srcs.append("../rtl/ssio_ddr_in.v") srcs.append("../rtl/ssio_ddr_out.v") srcs.append("../lib/axis/rtl/axis_async_fifo.v") +srcs.append("../lib/axis/rtl/axis_async_fifo_adapter.v") srcs.append("%s.v" % testbench) src = ' '.join(srcs) @@ -60,8 +61,19 @@ def bench(): IODDR_STYLE = "IODDR2" CLOCK_INPUT_STYLE = "BUFIO2" USE_CLK90 = "TRUE" + AXIS_DATA_WIDTH = 8 + AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8) + AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8) ENABLE_PADDING = 1 MIN_FRAME_LENGTH = 64 + TX_FIFO_DEPTH = 4096 + TX_FRAME_FIFO = 1 + TX_DROP_BAD_FRAME = TX_FRAME_FIFO + TX_DROP_WHEN_FULL = 0 + RX_FIFO_DEPTH = 4096 + RX_FRAME_FIFO = 1 + RX_DROP_BAD_FRAME = RX_FRAME_FIFO + RX_DROP_WHEN_FULL = RX_FRAME_FIFO # Inputs clk = Signal(bool(0)) @@ -73,7 +85,8 @@ def bench(): gtx_rst = Signal(bool(0)) logic_clk = Signal(bool(0)) logic_rst = Signal(bool(0)) - tx_axis_tdata = Signal(intbv(0)[8:]) + tx_axis_tdata = Signal(intbv(0)[AXIS_DATA_WIDTH:]) + tx_axis_tkeep = Signal(intbv(1)[AXIS_KEEP_WIDTH:]) tx_axis_tvalid = Signal(bool(0)) tx_axis_tlast = Signal(bool(0)) tx_axis_tuser = Signal(bool(0)) @@ -85,7 +98,8 @@ def bench(): # Outputs tx_axis_tready = Signal(bool(0)) - rx_axis_tdata = Signal(intbv(0)[8:]) + rx_axis_tdata = Signal(intbv(0)[AXIS_DATA_WIDTH:]) + rx_axis_tkeep = Signal(intbv(1)[AXIS_KEEP_WIDTH:]) rx_axis_tvalid = Signal(bool(0)) rx_axis_tlast = Signal(bool(0)) rx_axis_tuser = Signal(bool(0)) @@ -137,6 +151,7 @@ def bench(): logic_clk, logic_rst, tdata=tx_axis_tdata, + tkeep=tx_axis_tkeep, tvalid=tx_axis_tvalid, tready=tx_axis_tready, tlast=tx_axis_tlast, @@ -151,6 +166,7 @@ def bench(): logic_clk, logic_rst, tdata=rx_axis_tdata, + tkeep=rx_axis_tkeep, tvalid=rx_axis_tvalid, tready=rx_axis_tready, tlast=rx_axis_tlast, @@ -176,12 +192,14 @@ def bench(): logic_rst=logic_rst, tx_axis_tdata=tx_axis_tdata, + tx_axis_tkeep=tx_axis_tkeep, tx_axis_tvalid=tx_axis_tvalid, tx_axis_tready=tx_axis_tready, tx_axis_tlast=tx_axis_tlast, tx_axis_tuser=tx_axis_tuser, rx_axis_tdata=rx_axis_tdata, + rx_axis_tkeep=rx_axis_tkeep, rx_axis_tvalid=rx_axis_tvalid, rx_axis_tready=rx_axis_tready, rx_axis_tlast=rx_axis_tlast, diff --git a/tb/test_eth_mac_1g_rgmii_fifo.v b/tb/test_eth_mac_1g_rgmii_fifo.v index e141b3c2..c36c1acd 100644 --- a/tb/test_eth_mac_1g_rgmii_fifo.v +++ b/tb/test_eth_mac_1g_rgmii_fifo.v @@ -36,10 +36,19 @@ parameter TARGET = "SIM"; parameter IODDR_STYLE = "IODDR2"; parameter CLOCK_INPUT_STYLE = "BUFIO2"; parameter USE_CLK90 = "TRUE"; +parameter AXIS_DATA_WIDTH = 8; +parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8); +parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8); parameter ENABLE_PADDING = 1; parameter MIN_FRAME_LENGTH = 64; -parameter TX_FIFO_ADDR_WIDTH = 9; -parameter RX_FIFO_ADDR_WIDTH = 9; +parameter TX_FIFO_DEPTH = 4096; +parameter TX_FRAME_FIFO = 1; +parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO; +parameter TX_DROP_WHEN_FULL = 0; +parameter RX_FIFO_DEPTH = 4096; +parameter RX_FRAME_FIFO = 1; +parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO; +parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO; // Inputs reg clk = 0; @@ -51,7 +60,8 @@ reg gtx_clk90 = 0; reg gtx_rst = 0; reg logic_clk = 0; reg logic_rst = 0; -reg [7:0] tx_axis_tdata = 0; +reg [AXIS_DATA_WIDTH-1:0] tx_axis_tdata = 0; +reg [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep = 0; reg tx_axis_tvalid = 0; reg tx_axis_tlast = 0; reg tx_axis_tuser = 0; @@ -63,7 +73,8 @@ reg [7:0] ifg_delay = 0; // Outputs wire tx_axis_tready; -wire [7:0] rx_axis_tdata; +wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata; +wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep; wire rx_axis_tvalid; wire rx_axis_tlast; wire rx_axis_tuser; @@ -93,6 +104,7 @@ initial begin logic_clk, logic_rst, tx_axis_tdata, + tx_axis_tkeep, tx_axis_tvalid, tx_axis_tlast, tx_axis_tuser, @@ -105,6 +117,7 @@ initial begin $to_myhdl( tx_axis_tready, rx_axis_tdata, + rx_axis_tkeep, rx_axis_tvalid, rx_axis_tlast, rx_axis_tuser, @@ -133,10 +146,19 @@ eth_mac_1g_rgmii_fifo #( .IODDR_STYLE(IODDR_STYLE), .CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE), .USE_CLK90(USE_CLK90), + .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH), + .AXIS_KEEP_ENABLE(AXIS_KEEP_ENABLE), + .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH), .ENABLE_PADDING(ENABLE_PADDING), .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), - .TX_FIFO_ADDR_WIDTH(TX_FIFO_ADDR_WIDTH), - .RX_FIFO_ADDR_WIDTH(RX_FIFO_ADDR_WIDTH) + .TX_FIFO_DEPTH(TX_FIFO_DEPTH), + .TX_FRAME_FIFO(TX_FRAME_FIFO), + .TX_DROP_BAD_FRAME(TX_DROP_BAD_FRAME), + .TX_DROP_WHEN_FULL(TX_DROP_WHEN_FULL), + .RX_FIFO_DEPTH(RX_FIFO_DEPTH), + .RX_FRAME_FIFO(RX_FRAME_FIFO), + .RX_DROP_BAD_FRAME(RX_DROP_BAD_FRAME), + .RX_DROP_WHEN_FULL(RX_DROP_WHEN_FULL) ) UUT ( .gtx_clk(gtx_clk), @@ -145,11 +167,13 @@ UUT ( .logic_clk(logic_clk), .logic_rst(logic_rst), .tx_axis_tdata(tx_axis_tdata), + .tx_axis_tkeep(tx_axis_tkeep), .tx_axis_tvalid(tx_axis_tvalid), .tx_axis_tready(tx_axis_tready), .tx_axis_tlast(tx_axis_tlast), .tx_axis_tuser(tx_axis_tuser), .rx_axis_tdata(rx_axis_tdata), + .rx_axis_tkeep(rx_axis_tkeep), .rx_axis_tvalid(rx_axis_tvalid), .rx_axis_tready(rx_axis_tready), .rx_axis_tlast(rx_axis_tlast), diff --git a/tb/test_eth_mac_mii_fifo.py b/tb/test_eth_mac_mii_fifo.py index 1192112f..16abf82c 100755 --- a/tb/test_eth_mac_mii_fifo.py +++ b/tb/test_eth_mac_mii_fifo.py @@ -44,6 +44,7 @@ srcs.append("../rtl/eth_mac_mii.v") srcs.append("../rtl/mii_phy_if.v") srcs.append("../rtl/ssio_sdr_in.v") srcs.append("../lib/axis/rtl/axis_async_fifo.v") +srcs.append("../lib/axis/rtl/axis_async_fifo_adapter.v") srcs.append("%s.v" % testbench) src = ' '.join(srcs) @@ -55,10 +56,19 @@ def bench(): # Parameters TARGET = "SIM" CLOCK_INPUT_STYLE = "BUFIO2" + AXIS_DATA_WIDTH = 8 + AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8) + AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8) ENABLE_PADDING = 1 MIN_FRAME_LENGTH = 64 - TX_FIFO_ADDR_WIDTH = 9 - RX_FIFO_ADDR_WIDTH = 9 + TX_FIFO_DEPTH = 4096 + TX_FRAME_FIFO = 1 + TX_DROP_BAD_FRAME = TX_FRAME_FIFO + TX_DROP_WHEN_FULL = 0 + RX_FIFO_DEPTH = 4096 + RX_FRAME_FIFO = 1 + RX_DROP_BAD_FRAME = RX_FRAME_FIFO + RX_DROP_WHEN_FULL = RX_FRAME_FIFO # Inputs clk = Signal(bool(0)) @@ -67,7 +77,8 @@ def bench(): logic_clk = Signal(bool(0)) logic_rst = Signal(bool(0)) - tx_axis_tdata = Signal(intbv(0)[8:]) + tx_axis_tdata = Signal(intbv(0)[AXIS_DATA_WIDTH:]) + tx_axis_tkeep = Signal(intbv(1)[AXIS_KEEP_WIDTH:]) tx_axis_tvalid = Signal(bool(0)) tx_axis_tlast = Signal(bool(0)) tx_axis_tuser = Signal(bool(0)) @@ -81,7 +92,8 @@ def bench(): # Outputs tx_axis_tready = Signal(bool(0)) - rx_axis_tdata = Signal(intbv(0)[8:]) + rx_axis_tdata = Signal(intbv(0)[AXIS_DATA_WIDTH:]) + rx_axis_tkeep = Signal(intbv(1)[AXIS_KEEP_WIDTH:]) rx_axis_tvalid = Signal(bool(0)) rx_axis_tlast = Signal(bool(0)) rx_axis_tuser = Signal(bool(0)) @@ -130,6 +142,7 @@ def bench(): logic_clk, logic_rst, tdata=tx_axis_tdata, + tkeep=tx_axis_tkeep, tvalid=tx_axis_tvalid, tready=tx_axis_tready, tlast=tx_axis_tlast, @@ -144,6 +157,7 @@ def bench(): logic_clk, logic_rst, tdata=rx_axis_tdata, + tkeep=rx_axis_tkeep, tvalid=rx_axis_tvalid, tready=rx_axis_tready, tlast=rx_axis_tlast, @@ -166,14 +180,16 @@ def bench(): logic_rst=logic_rst, tx_axis_tdata=tx_axis_tdata, + tx_axis_tkeep=tx_axis_tkeep, tx_axis_tvalid=tx_axis_tvalid, tx_axis_tready=tx_axis_tready, tx_axis_tlast=tx_axis_tlast, tx_axis_tuser=tx_axis_tuser, rx_axis_tdata=rx_axis_tdata, - rx_axis_tready=rx_axis_tready, + rx_axis_tkeep=rx_axis_tkeep, rx_axis_tvalid=rx_axis_tvalid, + rx_axis_tready=rx_axis_tready, rx_axis_tlast=rx_axis_tlast, rx_axis_tuser=rx_axis_tuser, diff --git a/tb/test_eth_mac_mii_fifo.v b/tb/test_eth_mac_mii_fifo.v index 5eb2eff4..54e04a8c 100644 --- a/tb/test_eth_mac_mii_fifo.v +++ b/tb/test_eth_mac_mii_fifo.v @@ -34,10 +34,19 @@ module test_eth_mac_mii_fifo; // Parameters parameter TARGET = "SIM"; parameter CLOCK_INPUT_STYLE = "BUFIO2"; +parameter AXIS_DATA_WIDTH = 8; +parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8); +parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8); parameter ENABLE_PADDING = 1; parameter MIN_FRAME_LENGTH = 64; -parameter TX_FIFO_ADDR_WIDTH = 9; -parameter RX_FIFO_ADDR_WIDTH = 9; +parameter TX_FIFO_DEPTH = 4096; +parameter TX_FRAME_FIFO = 1; +parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO; +parameter TX_DROP_WHEN_FULL = 0; +parameter RX_FIFO_DEPTH = 4096; +parameter RX_FRAME_FIFO = 1; +parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO; +parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO; // Inputs reg clk = 0; @@ -46,7 +55,8 @@ reg [7:0] current_test = 0; reg logic_clk = 0; reg logic_rst = 0; -reg [7:0] tx_axis_tdata = 0; +reg [AXIS_DATA_WIDTH-1:0] tx_axis_tdata = 0; +reg [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep = 0; reg tx_axis_tvalid = 0; reg tx_axis_tlast = 0; reg tx_axis_tuser = 0; @@ -60,7 +70,8 @@ reg [7:0] ifg_delay = 0; // Outputs wire tx_axis_tready; -wire [7:0] rx_axis_tdata; +wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata; +wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep; wire rx_axis_tvalid; wire rx_axis_tlast; wire rx_axis_tuser; @@ -86,6 +97,7 @@ initial begin logic_clk, logic_rst, tx_axis_tdata, + tx_axis_tkeep, tx_axis_tvalid, tx_axis_tlast, tx_axis_tuser, @@ -100,6 +112,7 @@ initial begin $to_myhdl( tx_axis_tready, rx_axis_tdata, + rx_axis_tkeep, rx_axis_tvalid, rx_axis_tlast, rx_axis_tuser, @@ -125,21 +138,32 @@ end eth_mac_mii_fifo #( .TARGET(TARGET), .CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE), + .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH), + .AXIS_KEEP_ENABLE(AXIS_KEEP_ENABLE), + .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH), .ENABLE_PADDING(ENABLE_PADDING), .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), - .TX_FIFO_ADDR_WIDTH(TX_FIFO_ADDR_WIDTH), - .RX_FIFO_ADDR_WIDTH(RX_FIFO_ADDR_WIDTH) + .TX_FIFO_DEPTH(TX_FIFO_DEPTH), + .TX_FRAME_FIFO(TX_FRAME_FIFO), + .TX_DROP_BAD_FRAME(TX_DROP_BAD_FRAME), + .TX_DROP_WHEN_FULL(TX_DROP_WHEN_FULL), + .RX_FIFO_DEPTH(RX_FIFO_DEPTH), + .RX_FRAME_FIFO(RX_FRAME_FIFO), + .RX_DROP_BAD_FRAME(RX_DROP_BAD_FRAME), + .RX_DROP_WHEN_FULL(RX_DROP_WHEN_FULL) ) UUT ( .rst(rst), .logic_clk(logic_clk), .logic_rst(logic_rst), .tx_axis_tdata(tx_axis_tdata), + .tx_axis_tkeep(tx_axis_tkeep), .tx_axis_tvalid(tx_axis_tvalid), .tx_axis_tready(tx_axis_tready), .tx_axis_tlast(tx_axis_tlast), .tx_axis_tuser(tx_axis_tuser), .rx_axis_tdata(rx_axis_tdata), + .rx_axis_tkeep(rx_axis_tkeep), .rx_axis_tvalid(rx_axis_tvalid), .rx_axis_tready(rx_axis_tready), .rx_axis_tlast(rx_axis_tlast), diff --git a/tb/test_eth_mac_phy_10g_fifo.py b/tb/test_eth_mac_phy_10g_fifo.py index c2f13fc8..403ad02c 100755 --- a/tb/test_eth_mac_phy_10g_fifo.py +++ b/tb/test_eth_mac_phy_10g_fifo.py @@ -48,6 +48,7 @@ srcs.append("../rtl/eth_phy_10g_rx_ber_mon.v") srcs.append("../rtl/eth_phy_10g_rx_frame_sync.v") srcs.append("../rtl/lfsr.v") srcs.append("../lib/axis/rtl/axis_async_fifo.v") +srcs.append("../lib/axis/rtl/axis_async_fifo_adapter.v") srcs.append("%s.v" % testbench) src = ' '.join(srcs) @@ -58,9 +59,10 @@ def bench(): # Parameters DATA_WIDTH = 64 - KEEP_WIDTH = int(DATA_WIDTH/8) - CTRL_WIDTH = int(DATA_WIDTH/8) - HDR_WIDTH = int(DATA_WIDTH/32) + HDR_WIDTH = (DATA_WIDTH/32) + AXIS_DATA_WIDTH = DATA_WIDTH + AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8) + AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8) ENABLE_PADDING = 1 ENABLE_DIC = 1 MIN_FRAME_LENGTH = 64 @@ -71,11 +73,11 @@ def bench(): RX_SERDES_PIPELINE = 2 SLIP_COUNT_WIDTH = 3 COUNT_125US = 125000/6.4 - TX_FIFO_ADDR_WIDTH = 12-(KEEP_WIDTH-1).bit_length() + TX_FIFO_DEPTH = 4096 TX_FRAME_FIFO = 1 TX_DROP_BAD_FRAME = TX_FRAME_FIFO TX_DROP_WHEN_FULL = 0 - RX_FIFO_ADDR_WIDTH = 12-(KEEP_WIDTH-1).bit_length() + RX_FIFO_DEPTH = 4096 RX_FRAME_FIFO = 1 RX_DROP_BAD_FRAME = RX_FRAME_FIFO RX_DROP_WHEN_FULL = RX_FRAME_FIFO @@ -91,8 +93,8 @@ def bench(): tx_rst = Signal(bool(0)) logic_clk = Signal(bool(0)) logic_rst = Signal(bool(0)) - tx_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) - tx_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) + tx_axis_tdata = Signal(intbv(0)[AXIS_DATA_WIDTH:]) + tx_axis_tkeep = Signal(intbv(0)[AXIS_KEEP_WIDTH:]) tx_axis_tvalid = Signal(bool(0)) tx_axis_tlast = Signal(bool(0)) tx_axis_tuser = Signal(bool(0)) @@ -108,8 +110,8 @@ def bench(): # Outputs tx_axis_tready = Signal(bool(0)) - rx_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) - rx_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) + rx_axis_tdata = Signal(intbv(0)[AXIS_DATA_WIDTH:]) + rx_axis_tkeep = Signal(intbv(0)[AXIS_KEEP_WIDTH:]) rx_axis_tvalid = Signal(bool(0)) rx_axis_tlast = Signal(bool(0)) rx_axis_tuser = Signal(bool(0)) @@ -131,6 +133,7 @@ def bench(): # sources and sinks axis_source_pause = Signal(bool(0)) + axis_sink_pause = Signal(bool(0)) serdes_source = baser_serdes_ep.BaseRSerdesSource() @@ -176,6 +179,7 @@ def bench(): tready=rx_axis_tready, tlast=rx_axis_tlast, tuser=rx_axis_tuser, + pause=axis_sink_pause, name='axis_sink' ) diff --git a/tb/test_eth_mac_phy_10g_fifo.v b/tb/test_eth_mac_phy_10g_fifo.v index 00276002..3f22059c 100644 --- a/tb/test_eth_mac_phy_10g_fifo.v +++ b/tb/test_eth_mac_phy_10g_fifo.v @@ -33,9 +33,10 @@ module test_eth_mac_phy_10g_fifo; // Parameters parameter DATA_WIDTH = 64; -parameter KEEP_WIDTH = (DATA_WIDTH/8); -parameter CTRL_WIDTH = (DATA_WIDTH/8); parameter HDR_WIDTH = (DATA_WIDTH/32); +parameter AXIS_DATA_WIDTH = DATA_WIDTH; +parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8); +parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8); parameter ENABLE_PADDING = 1; parameter ENABLE_DIC = 1; parameter MIN_FRAME_LENGTH = 64; @@ -46,11 +47,11 @@ parameter TX_SERDES_PIPELINE = 2; parameter RX_SERDES_PIPELINE = 2; parameter SLIP_COUNT_WIDTH = 3; parameter COUNT_125US = 125000/6.4; -parameter TX_FIFO_ADDR_WIDTH = 12-$clog2(KEEP_WIDTH); +parameter TX_FIFO_DEPTH = 4096; parameter TX_FRAME_FIFO = 1; parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO; parameter TX_DROP_WHEN_FULL = 0; -parameter RX_FIFO_ADDR_WIDTH = 12-$clog2(KEEP_WIDTH); +parameter RX_FIFO_DEPTH = 4096; parameter RX_FRAME_FIFO = 1; parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO; parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO; @@ -66,8 +67,8 @@ reg tx_clk = 0; reg tx_rst = 0; reg logic_clk = 0; reg logic_rst = 0; -reg [DATA_WIDTH-1:0] tx_axis_tdata = 0; -reg [KEEP_WIDTH-1:0] tx_axis_tkeep = 0; +reg [AXIS_DATA_WIDTH-1:0] tx_axis_tdata = 0; +reg [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep = 0; reg tx_axis_tvalid = 0; reg tx_axis_tlast = 0; reg tx_axis_tuser = 0; @@ -80,8 +81,8 @@ reg rx_prbs31_enable = 0; // Outputs wire tx_axis_tready; -wire [DATA_WIDTH-1:0] rx_axis_tdata; -wire [KEEP_WIDTH-1:0] rx_axis_tkeep; +wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata; +wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep; wire rx_axis_tvalid; wire rx_axis_tlast; wire rx_axis_tuser; @@ -156,9 +157,10 @@ end eth_mac_phy_10g_fifo #( .DATA_WIDTH(DATA_WIDTH), - .KEEP_WIDTH(KEEP_WIDTH), - .CTRL_WIDTH(CTRL_WIDTH), .HDR_WIDTH(HDR_WIDTH), + .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH), + .AXIS_KEEP_ENABLE(AXIS_KEEP_ENABLE), + .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH), .ENABLE_PADDING(ENABLE_PADDING), .ENABLE_DIC(ENABLE_DIC), .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), @@ -169,11 +171,11 @@ eth_mac_phy_10g_fifo #( .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), .SLIP_COUNT_WIDTH(SLIP_COUNT_WIDTH), .COUNT_125US(COUNT_125US), - .TX_FIFO_ADDR_WIDTH(TX_FIFO_ADDR_WIDTH), + .TX_FIFO_DEPTH(TX_FIFO_DEPTH), .TX_FRAME_FIFO(TX_FRAME_FIFO), .TX_DROP_BAD_FRAME(TX_DROP_BAD_FRAME), .TX_DROP_WHEN_FULL(TX_DROP_WHEN_FULL), - .RX_FIFO_ADDR_WIDTH(RX_FIFO_ADDR_WIDTH), + .RX_FIFO_DEPTH(RX_FIFO_DEPTH), .RX_FRAME_FIFO(RX_FRAME_FIFO), .RX_DROP_BAD_FRAME(RX_DROP_BAD_FRAME), .RX_DROP_WHEN_FULL(RX_DROP_WHEN_FULL) diff --git a/tb/test_udp.py b/tb/test_udp.py index a1e2da1a..b24d008f 100755 --- a/tb/test_udp.py +++ b/tb/test_udp.py @@ -48,6 +48,10 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src) def bench(): + # Parameters + CHECKSUM_PAYLOAD_FIFO_DEPTH = 2048 + CHECKSUM_HEADER_FIFO_DEPTH = 8 + # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) diff --git a/tb/test_udp.v b/tb/test_udp.v index aa0c71b4..a9eed083 100644 --- a/tb/test_udp.v +++ b/tb/test_udp.v @@ -33,8 +33,8 @@ module test_udp; // Parameters parameter CHECKSUM_GEN_ENABLE = 1; -parameter CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH = 11; -parameter CHECKSUM_HEADER_FIFO_ADDR_WIDTH = 3; +parameter CHECKSUM_PAYLOAD_FIFO_DEPTH = 2048; +parameter CHECKSUM_HEADER_FIFO_DEPTH = 8; // Inputs reg clk = 0; @@ -267,8 +267,8 @@ end udp #( .CHECKSUM_GEN_ENABLE(CHECKSUM_GEN_ENABLE), - .CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH(CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH), - .CHECKSUM_HEADER_FIFO_ADDR_WIDTH(CHECKSUM_HEADER_FIFO_ADDR_WIDTH) + .CHECKSUM_PAYLOAD_FIFO_DEPTH(CHECKSUM_PAYLOAD_FIFO_DEPTH), + .CHECKSUM_HEADER_FIFO_DEPTH(CHECKSUM_HEADER_FIFO_DEPTH) ) UUT ( .clk(clk), diff --git a/tb/test_udp_64.py b/tb/test_udp_64.py index 941f3dcf..1ae9c93c 100755 --- a/tb/test_udp_64.py +++ b/tb/test_udp_64.py @@ -48,6 +48,10 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src) def bench(): + # Parameters + CHECKSUM_PAYLOAD_FIFO_DEPTH = 2048 + CHECKSUM_HEADER_FIFO_DEPTH = 8 + # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) diff --git a/tb/test_udp_64.v b/tb/test_udp_64.v index 96623cde..4ca3d7c4 100644 --- a/tb/test_udp_64.v +++ b/tb/test_udp_64.v @@ -33,8 +33,8 @@ module test_udp_64; // Parameters parameter CHECKSUM_GEN_ENABLE = 1; -parameter CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH = 11; -parameter CHECKSUM_HEADER_FIFO_ADDR_WIDTH = 3; +parameter CHECKSUM_PAYLOAD_FIFO_DEPTH = 2048; +parameter CHECKSUM_HEADER_FIFO_DEPTH = 8; // Inputs reg clk = 0; @@ -275,8 +275,8 @@ end udp_64 #( .CHECKSUM_GEN_ENABLE(CHECKSUM_GEN_ENABLE), - .CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH(CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH), - .CHECKSUM_HEADER_FIFO_ADDR_WIDTH(CHECKSUM_HEADER_FIFO_ADDR_WIDTH) + .CHECKSUM_PAYLOAD_FIFO_DEPTH(CHECKSUM_PAYLOAD_FIFO_DEPTH), + .CHECKSUM_HEADER_FIFO_DEPTH(CHECKSUM_HEADER_FIFO_DEPTH) ) UUT ( .clk(clk), diff --git a/tb/test_udp_checksum_gen.py b/tb/test_udp_checksum_gen.py index 25eb3ec1..38bb2822 100755 --- a/tb/test_udp_checksum_gen.py +++ b/tb/test_udp_checksum_gen.py @@ -47,8 +47,8 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src) def bench(): # Parameters - PAYLOAD_FIFO_ADDR_WIDTH = 11 - HEADER_FIFO_ADDR_WIDTH = 3 + PAYLOAD_FIFO_DEPTH = 2048 + HEADER_FIFO_DEPTH = 8 # Inputs clk = Signal(bool(0)) diff --git a/tb/test_udp_checksum_gen.v b/tb/test_udp_checksum_gen.v index 82410420..e4a14d16 100644 --- a/tb/test_udp_checksum_gen.v +++ b/tb/test_udp_checksum_gen.v @@ -32,8 +32,8 @@ THE SOFTWARE. module test_udp_checksum_gen; // Parameters -parameter PAYLOAD_FIFO_ADDR_WIDTH = 11; -parameter HEADER_FIFO_ADDR_WIDTH = 3; +parameter PAYLOAD_FIFO_DEPTH = 2048; +parameter HEADER_FIFO_DEPTH = 8; // Inputs reg clk = 0; @@ -161,8 +161,8 @@ initial begin end udp_checksum_gen #( - .PAYLOAD_FIFO_ADDR_WIDTH(PAYLOAD_FIFO_ADDR_WIDTH), - .HEADER_FIFO_ADDR_WIDTH(HEADER_FIFO_ADDR_WIDTH) + .PAYLOAD_FIFO_DEPTH(PAYLOAD_FIFO_DEPTH), + .HEADER_FIFO_DEPTH(HEADER_FIFO_DEPTH) ) UUT ( .clk(clk), diff --git a/tb/test_udp_checksum_gen_64.py b/tb/test_udp_checksum_gen_64.py index 1202d29f..c9a70cf3 100755 --- a/tb/test_udp_checksum_gen_64.py +++ b/tb/test_udp_checksum_gen_64.py @@ -47,8 +47,8 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src) def bench(): # Parameters - PAYLOAD_FIFO_ADDR_WIDTH = 8 - HEADER_FIFO_ADDR_WIDTH = 3 + PAYLOAD_FIFO_DEPTH = 2048 + HEADER_FIFO_DEPTH = 8 # Inputs clk = Signal(bool(0)) diff --git a/tb/test_udp_checksum_gen_64.v b/tb/test_udp_checksum_gen_64.v index 79afa851..505603dd 100644 --- a/tb/test_udp_checksum_gen_64.v +++ b/tb/test_udp_checksum_gen_64.v @@ -32,8 +32,8 @@ THE SOFTWARE. module test_udp_checksum_gen_64; // Parameters -parameter PAYLOAD_FIFO_ADDR_WIDTH = 8; -parameter HEADER_FIFO_ADDR_WIDTH = 3; +parameter PAYLOAD_FIFO_DEPTH = 2048; +parameter HEADER_FIFO_DEPTH = 8; // Inputs reg clk = 0; @@ -165,8 +165,8 @@ initial begin end udp_checksum_gen_64 #( - .PAYLOAD_FIFO_ADDR_WIDTH(PAYLOAD_FIFO_ADDR_WIDTH), - .HEADER_FIFO_ADDR_WIDTH(HEADER_FIFO_ADDR_WIDTH) + .PAYLOAD_FIFO_DEPTH(PAYLOAD_FIFO_DEPTH), + .HEADER_FIFO_DEPTH(HEADER_FIFO_DEPTH) ) UUT ( .clk(clk), diff --git a/tb/test_udp_complete.py b/tb/test_udp_complete.py index 7ebd4ba5..336f045f 100755 --- a/tb/test_udp_complete.py +++ b/tb/test_udp_complete.py @@ -63,6 +63,15 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src) def bench(): + # Parameters + ARP_CACHE_ADDR_WIDTH = 2 + ARP_REQUEST_RETRY_COUNT = 4 + ARP_REQUEST_RETRY_INTERVAL = 150 + ARP_REQUEST_TIMEOUT = 400 + UDP_CHECKSUM_GEN_ENABLE = 1 + UDP_CHECKSUM_PAYLOAD_FIFO_DEPTH = 2048 + UDP_CHECKSUM_HEADER_FIFO_DEPTH = 8 + # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) diff --git a/tb/test_udp_complete.v b/tb/test_udp_complete.v index 8f89a3f6..d208ab5d 100644 --- a/tb/test_udp_complete.v +++ b/tb/test_udp_complete.v @@ -37,8 +37,8 @@ parameter ARP_REQUEST_RETRY_COUNT = 4; parameter ARP_REQUEST_RETRY_INTERVAL = 150; parameter ARP_REQUEST_TIMEOUT = 400; parameter UDP_CHECKSUM_GEN_ENABLE = 1; -parameter UDP_CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH = 11; -parameter UDP_CHECKSUM_HEADER_FIFO_ADDR_WIDTH = 3; +parameter UDP_CHECKSUM_PAYLOAD_FIFO_DEPTH = 2048; +parameter UDP_CHECKSUM_HEADER_FIFO_DEPTH = 8; // Inputs reg clk = 0; @@ -310,8 +310,8 @@ udp_complete #( .ARP_REQUEST_RETRY_INTERVAL(ARP_REQUEST_RETRY_INTERVAL), .ARP_REQUEST_TIMEOUT(ARP_REQUEST_TIMEOUT), .UDP_CHECKSUM_GEN_ENABLE(UDP_CHECKSUM_GEN_ENABLE), - .UDP_CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH(UDP_CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH), - .UDP_CHECKSUM_HEADER_FIFO_ADDR_WIDTH(UDP_CHECKSUM_HEADER_FIFO_ADDR_WIDTH) + .UDP_CHECKSUM_PAYLOAD_FIFO_DEPTH(UDP_CHECKSUM_PAYLOAD_FIFO_DEPTH), + .UDP_CHECKSUM_HEADER_FIFO_DEPTH(UDP_CHECKSUM_HEADER_FIFO_DEPTH) ) UUT ( .clk(clk), diff --git a/tb/test_udp_complete_64.py b/tb/test_udp_complete_64.py index c285a4b9..d8ef9b21 100755 --- a/tb/test_udp_complete_64.py +++ b/tb/test_udp_complete_64.py @@ -63,6 +63,15 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src) def bench(): + # Parameters + ARP_CACHE_ADDR_WIDTH = 2 + ARP_REQUEST_RETRY_COUNT = 4 + ARP_REQUEST_RETRY_INTERVAL = 150 + ARP_REQUEST_TIMEOUT = 400 + UDP_CHECKSUM_GEN_ENABLE = 1 + UDP_CHECKSUM_PAYLOAD_FIFO_DEPTH = 2048 + UDP_CHECKSUM_HEADER_FIFO_DEPTH = 8 + # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) diff --git a/tb/test_udp_complete_64.v b/tb/test_udp_complete_64.v index 7822a684..a75a5278 100644 --- a/tb/test_udp_complete_64.v +++ b/tb/test_udp_complete_64.v @@ -37,8 +37,8 @@ parameter ARP_REQUEST_RETRY_COUNT = 4; parameter ARP_REQUEST_RETRY_INTERVAL = 150; parameter ARP_REQUEST_TIMEOUT = 400; parameter UDP_CHECKSUM_GEN_ENABLE = 1; -parameter UDP_CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH = 11; -parameter UDP_CHECKSUM_HEADER_FIFO_ADDR_WIDTH = 3; +parameter UDP_CHECKSUM_PAYLOAD_FIFO_DEPTH = 2048; +parameter UDP_CHECKSUM_HEADER_FIFO_DEPTH = 8; // Inputs reg clk = 0; @@ -322,8 +322,8 @@ udp_complete_64 #( .ARP_REQUEST_RETRY_INTERVAL(ARP_REQUEST_RETRY_INTERVAL), .ARP_REQUEST_TIMEOUT(ARP_REQUEST_TIMEOUT), .UDP_CHECKSUM_GEN_ENABLE(UDP_CHECKSUM_GEN_ENABLE), - .UDP_CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH(UDP_CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH), - .UDP_CHECKSUM_HEADER_FIFO_ADDR_WIDTH(UDP_CHECKSUM_HEADER_FIFO_ADDR_WIDTH) + .UDP_CHECKSUM_PAYLOAD_FIFO_DEPTH(UDP_CHECKSUM_PAYLOAD_FIFO_DEPTH), + .UDP_CHECKSUM_HEADER_FIFO_DEPTH(UDP_CHECKSUM_HEADER_FIFO_DEPTH) ) UUT ( .clk(clk),