diff --git a/example/AU200/fpga_10g/fpga.xdc b/example/AU200/fpga_10g/fpga.xdc
index 33046e6d..aa61c277 100644
--- a/example/AU200/fpga_10g/fpga.xdc
+++ b/example/AU200/fpga_10g/fpga.xdc
@@ -11,7 +11,6 @@ set_property BITSTREAM.CONFIG.CONFIGRATE 63.8          [current_design]
 set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES       [current_design]
 set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4           [current_design]
 set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES        [current_design]
-set_property BITSTREAM.CONFIG.SPI_OPCODE 8'h6B         [current_design]
 set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP         [current_design]
 
 # System clocks
diff --git a/example/AU250/fpga_10g/fpga.xdc b/example/AU250/fpga_10g/fpga.xdc
index 764edac1..58a54e6a 100644
--- a/example/AU250/fpga_10g/fpga.xdc
+++ b/example/AU250/fpga_10g/fpga.xdc
@@ -11,7 +11,6 @@ set_property BITSTREAM.CONFIG.CONFIGRATE 63.8          [current_design]
 set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES       [current_design]
 set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4           [current_design]
 set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES        [current_design]
-set_property BITSTREAM.CONFIG.SPI_OPCODE 8'h6B         [current_design]
 set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP         [current_design]
 
 # System clocks