mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-14 06:43:18 +08:00
Add timing constraints for Quartus Prime Pro
This commit is contained in:
parent
7751aba8da
commit
40265a3e1c
34
syn/quartus_pro/eth_mac_1g_gmii.sdc
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34
syn/quartus_pro/eth_mac_1g_gmii.sdc
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# Copyright (c) 2021 Alex Forencich
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
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# of this software and associated documentation files (the "Software"), to deal
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# in the Software without restriction, including without limitation the rights
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# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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# copies of the Software, and to permit persons to whom the Software is
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# furnished to do so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included in
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# all copies or substantial portions of the Software.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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# THE SOFTWARE.
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# GMII Gigabit Ethernet MAC timing constraints
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proc constrain_eth_mac_1g_gmii_inst { inst } {
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puts "Inserting timing constraints for eth_mac_1g_gmii instance $inst"
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# MII select sync
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set_data_delay -from [get_registers "$inst|mii_select_reg"] -to [get_registers "$inst|tx_mii_select_sync[0]"] -override -get_value_from_clock_period dst_clock_period -value_multiplier 0.8
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set_data_delay -from [get_registers "$inst|mii_select_reg"] -to [get_registers "$inst|rx_mii_select_sync[0]"] -override -get_value_from_clock_period dst_clock_period -value_multiplier 0.8
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# RX prescale sync
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set_data_delay -from [get_registers "$inst|rx_prescale[2]"] -to [get_registers "$inst|rx_prescale_sync[0]"] -override -get_value_from_clock_period dst_clock_period -value_multiplier 0.8
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constrain_gmii_phy_if_inst "$inst|gmii_phy_if_inst"
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}
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34
syn/quartus_pro/eth_mac_1g_rgmii.sdc
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34
syn/quartus_pro/eth_mac_1g_rgmii.sdc
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# Copyright (c) 2021 Alex Forencich
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
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# of this software and associated documentation files (the "Software"), to deal
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# in the Software without restriction, including without limitation the rights
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# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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# copies of the Software, and to permit persons to whom the Software is
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# furnished to do so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included in
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# all copies or substantial portions of the Software.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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# THE SOFTWARE.
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# RGMII Gigabit Ethernet MAC timing constraints
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proc constrain_eth_mac_1g_rgmii_inst { inst } {
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puts "Inserting timing constraints for eth_mac_1g_rgmii instance $inst"
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# MII select sync
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set_data_delay -from [get_registers "$inst|mii_select_reg"] -to [get_registers "$inst|tx_mii_select_sync[0]"] -override -get_value_from_clock_period dst_clock_period -value_multiplier 0.8
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set_data_delay -from [get_registers "$inst|mii_select_reg"] -to [get_registers "$inst|rx_mii_select_sync[0]"] -override -get_value_from_clock_period dst_clock_period -value_multiplier 0.8
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# RX prescale sync
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set_data_delay -from [get_registers "$inst|rx_prescale[2]"] -to [get_registers "$inst|rx_prescale_sync[0]"] -override -get_value_from_clock_period dst_clock_period -value_multiplier 0.8
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constrain_rgmii_phy_if_inst "$inst|rgmii_phy_if_inst"
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}
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31
syn/quartus_pro/eth_mac_fifo.sdc
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31
syn/quartus_pro/eth_mac_fifo.sdc
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# Copyright (c) 2021 Alex Forencich
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
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# of this software and associated documentation files (the "Software"), to deal
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# in the Software without restriction, including without limitation the rights
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# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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||||||
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# copies of the Software, and to permit persons to whom the Software is
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# furnished to do so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included in
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# all copies or substantial portions of the Software.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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# THE SOFTWARE.
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# Ethernet MAC with FIFO timing constraints
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proc constrain_eth_mac_fifo_inst { inst } {
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puts "Inserting timing constraints for ethernet MAC with FIFO instance $inst"
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# RX status sync
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set_data_delay -from [get_registers "$inst|rx_sync_reg_1_reg[*]"] -to [get_registers "$inst|rx_sync_reg_2_reg[*]"] -override -get_value_from_clock_period dst_clock_period -value_multiplier 0.8
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# TX status sync
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set_data_delay -from [get_registers "$inst|tx_sync_reg_1_reg[*]"] -to [get_registers "$inst|tx_sync_reg_2_reg[*]"] -override -get_value_from_clock_period dst_clock_period -value_multiplier 0.8
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}
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28
syn/quartus_pro/gmii_phy_if.sdc
Normal file
28
syn/quartus_pro/gmii_phy_if.sdc
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@ -0,0 +1,28 @@
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# Copyright (c) 2021 Alex Forencich
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
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# of this software and associated documentation files (the "Software"), to deal
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# in the Software without restriction, including without limitation the rights
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|
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||||
|
# copies of the Software, and to permit persons to whom the Software is
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# furnished to do so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included in
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# all copies or substantial portions of the Software.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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# THE SOFTWARE.
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# GMII PHY IF timing constraints
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proc constrain_gmii_phy_if_inst { inst } {
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puts "Inserting timing constraints for gmii_phy_if instance $inst"
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# reset synchronization
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set_false_path -from * -to [get_registers "$inst|tx_rst_reg[*] $inst|rx_rst_reg[*]"]
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}
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28
syn/quartus_pro/mii_phy_if.sdc
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28
syn/quartus_pro/mii_phy_if.sdc
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# Copyright (c) 2021 Alex Forencich
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
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# of this software and associated documentation files (the "Software"), to deal
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# in the Software without restriction, including without limitation the rights
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# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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||||||
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# copies of the Software, and to permit persons to whom the Software is
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# furnished to do so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included in
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# all copies or substantial portions of the Software.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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# THE SOFTWARE.
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# MII PHY IF timing constraints
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proc constrain_mii_phy_if_inst { inst } {
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puts "Inserting timing constraints for mii_phy_if instance $inst"
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# reset synchronization
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set_false_path -from * -to [get_registers "$inst|tx_rst_reg[*] $inst|rx_rst_reg[*]"]
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}
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32
syn/quartus_pro/rgmii_phy_if.sdc
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32
syn/quartus_pro/rgmii_phy_if.sdc
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# Copyright (c) 2021 Alex Forencich
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
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# of this software and associated documentation files (the "Software"), to deal
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# in the Software without restriction, including without limitation the rights
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# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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||||||
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# copies of the Software, and to permit persons to whom the Software is
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# furnished to do so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included in
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# all copies or substantial portions of the Software.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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# THE SOFTWARE.
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# RGMII PHY IF timing constraints
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proc constrain_rgmii_phy_if_inst { inst } {
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puts "Inserting timing constraints for rgmii_phy_if instance $inst"
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# reset synchronization
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set_false_path -from * -to [get_registers "$inst|tx_rst_reg[*] $inst|rx_rst_reg[*]"]
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# clock output
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# set_max_delay -from [get_registers "$inst|rgmii_tx_clk_1"] -to [get_cells "$inst|clk_oddr_inst|altddio_out_inst|auto_generated|ddio_outa[0]"] 2.000
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# set_max_delay -from [get_registers "$inst|rgmii_tx_clk_2"] -to [get_cells "$inst|clk_oddr_inst|altddio_out_inst|auto_generated|ddio_outa[0]"] 2.000
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}
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