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Rework UDP datapath modules to separate output register

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Alex Forencich 2014-10-28 01:55:29 -07:00
parent 867b799ecd
commit 4474181549
4 changed files with 661 additions and 916 deletions
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344
rtl/udp_ip_rx.v
View File

@ -130,21 +130,19 @@ UDP Frame
payload length octets
This module receives an IP frame with decoded fields and decodes
the AXI packet format. If the Ethertype does not match, the packet is
discarded.
This module receives an IP frame with header fields in parallel and payload on
an AXI stream interface, decodes and strips the UDP header fields, then
produces the header fields in parallel along with the UDP payload in a
separate AXI stream.
*/
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_READ_HEADER = 3'd1,
STATE_READ_PAYLOAD_IDLE = 3'd2,
STATE_READ_PAYLOAD_TRANSFER = 3'd3,
STATE_READ_PAYLOAD_TRANSFER_WAIT = 3'd4,
STATE_READ_PAYLOAD_TRANSFER_LAST = 3'd5,
STATE_READ_PAYLOAD_TRANSFER_WAIT_LAST = 3'd6,
STATE_WAIT_LAST = 3'd7;
STATE_READ_PAYLOAD = 3'd2,
STATE_READ_PAYLOAD_LAST = 3'd3,
STATE_WAIT_LAST = 3'd4;
reg [2:0] state_reg = STATE_IDLE, state_next;
@ -158,18 +156,11 @@ reg store_udp_length_0;
reg store_udp_length_1;
reg store_udp_checksum_0;
reg store_udp_checksum_1;
reg transfer_in_out;
reg transfer_in_temp;
reg transfer_temp_out;
reg assert_tlast;
reg assert_tuser;
reg store_last_word;
reg [15:0] frame_ptr_reg = 0, frame_ptr_next;
reg input_ip_hdr_ready_reg = 0;
reg input_ip_payload_tready_reg = 0;
reg [7:0] last_word_data_reg = 0;
reg output_udp_hdr_valid_reg = 0, output_udp_hdr_valid_next;
reg [47:0] output_eth_dest_mac_reg = 0;
@ -192,18 +183,21 @@ reg [15:0] output_udp_source_port_reg = 0;
reg [15:0] output_udp_dest_port_reg = 0;
reg [15:0] output_udp_length_reg = 0;
reg [15:0] output_udp_checksum_reg = 0;
reg [7:0] output_udp_payload_tdata_reg = 0;
reg output_udp_payload_tvalid_reg = 0;
reg output_udp_payload_tlast_reg = 0;
reg output_udp_payload_tuser_reg = 0;
reg input_ip_hdr_ready_reg = 0, input_ip_hdr_ready_next;
reg input_ip_payload_tready_reg = 0, input_ip_payload_tready_next;
reg busy_reg = 0;
reg error_header_early_termination_reg = 0, error_header_early_termination_next;
reg error_payload_early_termination_reg = 0, error_payload_early_termination_next;
reg [7:0] temp_udp_payload_tdata_reg = 0;
reg temp_udp_payload_tlast_reg = 0;
reg temp_udp_payload_tuser_reg = 0;
// internal datapath
reg [7:0] output_udp_payload_tdata_int;
reg output_udp_payload_tvalid_int;
reg output_udp_payload_tready_int = 0;
reg output_udp_payload_tlast_int;
reg output_udp_payload_tuser_int;
wire output_udp_payload_tready_int_early;
assign input_ip_hdr_ready = input_ip_hdr_ready_reg;
assign input_ip_payload_tready = input_ip_payload_tready_reg;
@ -229,10 +223,6 @@ assign output_udp_source_port = output_udp_source_port_reg;
assign output_udp_dest_port = output_udp_dest_port_reg;
assign output_udp_length = output_udp_length_reg;
assign output_udp_checksum = output_udp_checksum_reg;
assign output_udp_payload_tdata = output_udp_payload_tdata_reg;
assign output_udp_payload_tvalid = output_udp_payload_tvalid_reg;
assign output_udp_payload_tlast = output_udp_payload_tlast_reg;
assign output_udp_payload_tuser = output_udp_payload_tuser_reg;
assign busy = busy_reg;
assign error_header_early_termination = error_header_early_termination_reg;
@ -241,12 +231,8 @@ assign error_payload_early_termination = error_payload_early_termination_reg;
always @* begin
state_next = 2'bz;
transfer_in_out = 0;
transfer_in_temp = 0;
transfer_temp_out = 0;
assert_tlast = 0;
assert_tuser = 0;
input_ip_hdr_ready_next = 0;
input_ip_payload_tready_next = 0;
store_ip_hdr = 0;
store_udp_source_port_0 = 0;
@ -258,6 +244,8 @@ always @* begin
store_udp_checksum_0 = 0;
store_udp_checksum_1 = 0;
store_last_word = 0;
frame_ptr_next = frame_ptr_reg;
output_udp_hdr_valid_next = output_udp_hdr_valid_reg & ~output_udp_hdr_ready;
@ -265,13 +253,20 @@ always @* begin
error_header_early_termination_next = 0;
error_payload_early_termination_next = 0;
output_udp_payload_tdata_int = 0;
output_udp_payload_tvalid_int = 0;
output_udp_payload_tlast_int = 0;
output_udp_payload_tuser_int = 0;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for header
frame_ptr_next = 0;
input_ip_hdr_ready_next = ~output_udp_hdr_valid_reg;
if (input_ip_hdr_ready & input_ip_hdr_valid) begin
frame_ptr_next = 0;
input_ip_hdr_ready_next = 0;
input_ip_payload_tready_next = 1;
store_ip_hdr = 1;
state_next = STATE_READ_HEADER;
end else begin
@ -280,7 +275,9 @@ always @* begin
end
STATE_READ_HEADER: begin
// read header state
if (input_ip_payload_tvalid) begin
input_ip_payload_tready_next = 1;
if (input_ip_payload_tready & input_ip_payload_tvalid) begin
// word transfer in - store it
frame_ptr_next = frame_ptr_reg+1;
state_next = STATE_READ_HEADER;
@ -296,130 +293,86 @@ always @* begin
8'h07: begin
store_udp_checksum_0 = 1;
output_udp_hdr_valid_next = 1;
state_next = STATE_READ_PAYLOAD_IDLE;
input_ip_payload_tready_next = output_udp_payload_tready_int_early;
state_next = STATE_READ_PAYLOAD;
end
endcase
if (input_ip_payload_tlast) begin
state_next = STATE_IDLE;
output_udp_hdr_valid_next = 0;
error_header_early_termination_next = 1;
output_udp_hdr_valid_next = 0;
input_ip_hdr_ready_next = ~output_udp_hdr_valid_reg;
input_ip_payload_tready_next = 0;
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_READ_HEADER;
end
end
STATE_READ_PAYLOAD_IDLE: begin
// idle; no data in registers
if (input_ip_payload_tvalid) begin
// word transfer in - store it in output register
transfer_in_out = 1;
STATE_READ_PAYLOAD: begin
// read payload
input_ip_payload_tready_next = output_udp_payload_tready_int_early;
output_udp_payload_tdata_int = input_ip_payload_tdata;
output_udp_payload_tvalid_int = input_ip_payload_tvalid;
output_udp_payload_tlast_int = input_ip_payload_tlast;
output_udp_payload_tuser_int = input_ip_payload_tuser;
if (input_ip_payload_tready & input_ip_payload_tvalid) begin
// word transfer through
frame_ptr_next = frame_ptr_reg+1;
if (input_ip_payload_tlast) begin
if (frame_ptr_next != output_udp_length_reg) begin
// end of frame, but length does not match
assert_tuser = 1;
output_udp_payload_tuser_int = 1;
error_payload_early_termination_next = 1;
end
state_next = STATE_READ_PAYLOAD_TRANSFER_LAST;
input_ip_hdr_ready_next = ~output_udp_hdr_valid_reg;
input_ip_payload_tready_next = 0;
state_next = STATE_IDLE;
end else begin
if (frame_ptr_next == output_udp_length_reg) begin
// not end of frame, but we have the entire payload
state_next = STATE_READ_PAYLOAD_TRANSFER_WAIT_LAST;
store_last_word = 1;
output_udp_payload_tvalid_int = 0;
state_next = STATE_READ_PAYLOAD_LAST;
end else begin
state_next = STATE_READ_PAYLOAD_TRANSFER;
state_next = STATE_READ_PAYLOAD;
end
end
end else begin
state_next = STATE_READ_PAYLOAD_IDLE;
state_next = STATE_READ_PAYLOAD;
end
end
STATE_READ_PAYLOAD_TRANSFER: begin
// read payload; data in output register
if (input_ip_payload_tvalid & output_udp_payload_tready) begin
// word transfer through - update output register
transfer_in_out = 1;
frame_ptr_next = frame_ptr_reg+1;
STATE_READ_PAYLOAD_LAST: begin
// read and discard until end of frame
input_ip_payload_tready_next = output_udp_payload_tready_int_early;
output_udp_payload_tdata_int = last_word_data_reg;
output_udp_payload_tvalid_int = input_ip_payload_tvalid & input_ip_payload_tlast;
output_udp_payload_tlast_int = input_ip_payload_tlast;
output_udp_payload_tuser_int = input_ip_payload_tuser;
if (input_ip_payload_tready & input_ip_payload_tvalid) begin
if (input_ip_payload_tlast) begin
if (frame_ptr_next != output_udp_length_reg) begin
// end of frame, but length does not match
assert_tuser = 1;
error_payload_early_termination_next = 1;
end
state_next = STATE_READ_PAYLOAD_TRANSFER_LAST;
input_ip_hdr_ready_next = ~output_udp_hdr_valid_reg;
input_ip_payload_tready_next = 0;
state_next = STATE_IDLE;
end else begin
if (frame_ptr_next == output_udp_length_reg) begin
// not end of frame, but we have the entire payload
state_next = STATE_READ_PAYLOAD_TRANSFER_WAIT_LAST;
end else begin
state_next = STATE_READ_PAYLOAD_TRANSFER;
end
end
end else if (~input_ip_payload_tvalid & output_udp_payload_tready) begin
// word transfer out - go back to idle
state_next = STATE_READ_PAYLOAD_IDLE;
end else if (input_ip_payload_tvalid & ~output_udp_payload_tready) begin
// word transfer in - store in temp
transfer_in_temp = 1;
frame_ptr_next = frame_ptr_reg+1;
state_next = STATE_READ_PAYLOAD_TRANSFER_WAIT;
end else begin
state_next = STATE_READ_PAYLOAD_TRANSFER;
end
end
STATE_READ_PAYLOAD_TRANSFER_WAIT: begin
// read payload; data in both output and temp registers
if (output_udp_payload_tready) begin
// transfer out - move temp to output
transfer_temp_out = 1;
if (temp_udp_payload_tlast_reg) begin
if (frame_ptr_next != output_udp_length_reg) begin
// end of frame, but length does not match
assert_tuser = 1;
error_payload_early_termination_next = 1;
end
state_next = STATE_READ_PAYLOAD_TRANSFER_LAST;
end else begin
if (frame_ptr_next == output_udp_length_reg) begin
// not end of frame, but we have the entire payload
state_next = STATE_READ_PAYLOAD_TRANSFER_WAIT_LAST;
end else begin
state_next = STATE_READ_PAYLOAD_TRANSFER;
end
state_next = STATE_READ_PAYLOAD_LAST;
end
end else begin
state_next = STATE_READ_PAYLOAD_TRANSFER_WAIT;
end
end
STATE_READ_PAYLOAD_TRANSFER_LAST: begin
// read last payload word; data in output register; do not accept new data
if (output_udp_payload_tready) begin
// word transfer out - done
state_next = STATE_IDLE;
end else begin
state_next = STATE_READ_PAYLOAD_TRANSFER_LAST;
end
end
STATE_READ_PAYLOAD_TRANSFER_WAIT_LAST: begin
// wait for end of frame; data in output register; read and discard
if (input_ip_payload_tvalid) begin
if (input_ip_payload_tlast) begin
// assert tlast and transfer tuser
assert_tlast = 1;
assert_tuser = input_ip_payload_tuser;
state_next = STATE_READ_PAYLOAD_TRANSFER_LAST;
end else begin
state_next = STATE_READ_PAYLOAD_TRANSFER_WAIT_LAST;
end
end else begin
state_next = STATE_READ_PAYLOAD_TRANSFER_WAIT_LAST;
state_next = STATE_READ_PAYLOAD_LAST;
end
end
STATE_WAIT_LAST: begin
// wait for end of frame; read and discard
if (input_ip_payload_tvalid) begin
input_ip_payload_tready_next = 1;
if (input_ip_payload_tready & input_ip_payload_tvalid) begin
if (input_ip_payload_tlast) begin
input_ip_hdr_ready_next = ~output_udp_hdr_valid_reg;
input_ip_payload_tready_next = 0;
state_next = STATE_IDLE;
end else begin
state_next = STATE_WAIT_LAST;
@ -435,6 +388,7 @@ always @(posedge clk or posedge rst) begin
if (rst) begin
state_reg <= STATE_IDLE;
frame_ptr_reg <= 0;
last_word_data_reg <= 0;
input_ip_hdr_ready_reg <= 0;
input_ip_payload_tready_reg <= 0;
output_udp_hdr_valid_reg <= 0;
@ -458,13 +412,6 @@ always @(posedge clk or posedge rst) begin
output_udp_dest_port_reg <= 0;
output_udp_length_reg <= 0;
output_udp_checksum_reg <= 0;
output_udp_payload_tdata_reg <= 0;
output_udp_payload_tvalid_reg <= 0;
output_udp_payload_tlast_reg <= 0;
output_udp_payload_tuser_reg <= 0;
temp_udp_payload_tdata_reg <= 0;
temp_udp_payload_tlast_reg <= 0;
temp_udp_payload_tuser_reg <= 0;
busy_reg <= 0;
error_header_early_termination_reg <= 0;
error_payload_early_termination_reg <= 0;
@ -473,6 +420,9 @@ always @(posedge clk or posedge rst) begin
frame_ptr_reg <= frame_ptr_next;
input_ip_hdr_ready_reg <= input_ip_hdr_ready_next;
input_ip_payload_tready_reg <= input_ip_payload_tready_next;
output_udp_hdr_valid_reg <= output_udp_hdr_valid_next;
error_header_early_termination_reg <= error_header_early_termination_next;
@ -480,58 +430,6 @@ always @(posedge clk or posedge rst) begin
busy_reg <= state_next != STATE_IDLE;
// generate valid outputs
case (state_next)
STATE_IDLE: begin
// idle; accept new data
input_ip_hdr_ready_reg <= ~output_udp_hdr_valid;
input_ip_payload_tready_reg <= 0;
output_udp_payload_tvalid_reg <= 0;
end
STATE_READ_HEADER: begin
// read header; accept new data
input_ip_hdr_ready_reg <= 0;
input_ip_payload_tready_reg <= 1;
output_udp_payload_tvalid_reg <= 0;
end
STATE_READ_PAYLOAD_IDLE: begin
// read payload; no data in registers; accept new data
input_ip_hdr_ready_reg <= 0;
input_ip_payload_tready_reg <= 1;
output_udp_payload_tvalid_reg <= 0;
end
STATE_READ_PAYLOAD_TRANSFER: begin
// read payload; data in output register; accept new data
input_ip_hdr_ready_reg <= 0;
input_ip_payload_tready_reg <= 1;
output_udp_payload_tvalid_reg <= 1;
end
STATE_READ_PAYLOAD_TRANSFER_WAIT: begin
// read payload; data in output and temp registers; do not accept new data
input_ip_hdr_ready_reg <= 0;
input_ip_payload_tready_reg <= 0;
output_udp_payload_tvalid_reg <= 1;
end
STATE_READ_PAYLOAD_TRANSFER_LAST: begin
// read last payload word; data in output register; do not accept new data
input_ip_hdr_ready_reg <= 0;
input_ip_payload_tready_reg <= 0;
output_udp_payload_tvalid_reg <= 1;
end
STATE_READ_PAYLOAD_TRANSFER_WAIT_LAST: begin
// wait for end of frame; data in output register; read and discard
input_ip_hdr_ready_reg <= 0;
input_ip_payload_tready_reg <= 1;
output_udp_payload_tvalid_reg <= 0;
end
STATE_WAIT_LAST: begin
// wait for end of frame; read and discard
input_ip_hdr_ready_reg <= 0;
input_ip_payload_tready_reg <= 1;
output_udp_payload_tvalid_reg <= 0;
end
endcase
// datapath
if (store_ip_hdr) begin
output_eth_dest_mac_reg <= input_eth_dest_mac;
@ -552,6 +450,10 @@ always @(posedge clk or posedge rst) begin
output_ip_dest_ip_reg <= input_ip_dest_ip;
end
if (store_last_word) begin
last_word_data_reg <= output_udp_payload_tdata_int;
end
if (store_udp_source_port_0) output_udp_source_port_reg[ 7: 0] <= input_ip_payload_tdata;
if (store_udp_source_port_1) output_udp_source_port_reg[15: 8] <= input_ip_payload_tdata;
if (store_udp_dest_port_0) output_udp_dest_port_reg[ 7: 0] <= input_ip_payload_tdata;
@ -560,23 +462,69 @@ always @(posedge clk or posedge rst) begin
if (store_udp_length_1) output_udp_length_reg[15: 8] <= input_ip_payload_tdata;
if (store_udp_checksum_0) output_udp_checksum_reg[ 7: 0] <= input_ip_payload_tdata;
if (store_udp_checksum_1) output_udp_checksum_reg[15: 8] <= input_ip_payload_tdata;
end
end
if (transfer_in_out) begin
output_udp_payload_tdata_reg <= input_ip_payload_tdata;
output_udp_payload_tlast_reg <= input_ip_payload_tlast;
output_udp_payload_tuser_reg <= input_ip_payload_tuser;
end else if (transfer_in_temp) begin
temp_udp_payload_tdata_reg <= input_ip_payload_tdata;
temp_udp_payload_tlast_reg <= input_ip_payload_tlast;
temp_udp_payload_tuser_reg <= input_ip_payload_tuser;
end else if (transfer_temp_out) begin
// output datapath logic
reg [7:0] output_udp_payload_tdata_reg = 0;
reg output_udp_payload_tvalid_reg = 0;
reg output_udp_payload_tlast_reg = 0;
reg output_udp_payload_tuser_reg = 0;
reg [7:0] temp_udp_payload_tdata_reg = 0;
reg temp_udp_payload_tvalid_reg = 0;
reg temp_udp_payload_tlast_reg = 0;
reg temp_udp_payload_tuser_reg = 0;
// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle
assign output_udp_payload_tready_int_early = output_udp_payload_tready | (~temp_udp_payload_tvalid_reg & ~output_udp_payload_tvalid_reg) | (~temp_udp_payload_tvalid_reg & ~output_udp_payload_tvalid_int);
assign output_udp_payload_tdata = output_udp_payload_tdata_reg;
assign output_udp_payload_tvalid = output_udp_payload_tvalid_reg;
assign output_udp_payload_tlast = output_udp_payload_tlast_reg;
assign output_udp_payload_tuser = output_udp_payload_tuser_reg;
always @(posedge clk or posedge rst) begin
if (rst) begin
output_udp_payload_tdata_reg <= 0;
output_udp_payload_tvalid_reg <= 0;
output_udp_payload_tlast_reg <= 0;
output_udp_payload_tuser_reg <= 0;
output_udp_payload_tready_int <= 0;
temp_udp_payload_tdata_reg <= 0;
temp_udp_payload_tvalid_reg <= 0;
temp_udp_payload_tlast_reg <= 0;
temp_udp_payload_tuser_reg <= 0;
end else begin
// transfer sink ready state to source
output_udp_payload_tready_int <= output_udp_payload_tready_int_early;
if (output_udp_payload_tready_int) begin
// input is ready
if (output_udp_payload_tready | ~output_udp_payload_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
output_udp_payload_tdata_reg <= output_udp_payload_tdata_int;
output_udp_payload_tvalid_reg <= output_udp_payload_tvalid_int;
output_udp_payload_tlast_reg <= output_udp_payload_tlast_int;
output_udp_payload_tuser_reg <= output_udp_payload_tuser_int;
end else begin
// output is not ready and currently valid, store input in temp
temp_udp_payload_tdata_reg <= output_udp_payload_tdata_int;
temp_udp_payload_tvalid_reg <= output_udp_payload_tvalid_int;
temp_udp_payload_tlast_reg <= output_udp_payload_tlast_int;
temp_udp_payload_tuser_reg <= output_udp_payload_tuser_int;
end
end else if (output_udp_payload_tready) begin
// input is not ready, but output is ready
output_udp_payload_tdata_reg <= temp_udp_payload_tdata_reg;
output_udp_payload_tvalid_reg <= temp_udp_payload_tvalid_reg;
output_udp_payload_tlast_reg <= temp_udp_payload_tlast_reg;
output_udp_payload_tuser_reg <= temp_udp_payload_tuser_reg;
temp_udp_payload_tdata_reg <= 0;
temp_udp_payload_tvalid_reg <= 0;
temp_udp_payload_tlast_reg <= 0;
temp_udp_payload_tuser_reg <= 0;
end
if (assert_tlast) output_udp_payload_tlast_reg <= 1;
if (assert_tuser) output_udp_payload_tuser_reg <= 1;
end
end

412
rtl/udp_ip_rx_64.v
View File

@ -132,41 +132,31 @@ UDP Frame
payload length octets
This module receives an IP frame with decoded fields and decodes
the AXI packet format. If the Ethertype does not match, the packet is
discarded.
This module receives an IP frame with header fields in parallel and payload on
an AXI stream interface, decodes and strips the UDP header fields, then
produces the header fields in parallel along with the UDP payload in a
separate AXI stream.
*/
localparam [3:0]
STATE_IDLE = 4'd0,
STATE_READ_HEADER = 4'd1,
STATE_READ_PAYLOAD_IDLE = 4'd2,
STATE_READ_PAYLOAD_TRANSFER = 4'd3,
STATE_READ_PAYLOAD_TRANSFER_WAIT = 4'd4,
STATE_READ_PAYLOAD_TRANSFER_LAST = 4'd5,
STATE_READ_PAYLOAD_TRANSFER_WAIT_LAST = 4'd6,
STATE_READ_PAYLOAD_TRANSFER_WAIT_LAST_WAIT = 4'd7,
STATE_WAIT_LAST = 4'd8;
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_READ_HEADER = 3'd1,
STATE_READ_PAYLOAD = 3'd2,
STATE_READ_PAYLOAD_LAST = 3'd3,
STATE_WAIT_LAST = 3'd4;
reg [3:0] state_reg = STATE_IDLE, state_next;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg store_ip_hdr;
reg store_hdr_word_0;
reg transfer_in_out;
reg transfer_in_temp;
reg transfer_temp_out;
reg assert_tlast;
reg assert_tuser;
reg [7:0] tkeep_mask;
reg store_last_word;
reg [15:0] frame_ptr_reg = 0, frame_ptr_next;
reg input_ip_hdr_ready_reg = 0;
reg input_ip_payload_tready_reg = 0;
reg [63:0] last_word_data_reg = 0;
reg [7:0] last_word_keep_reg = 0;
reg output_udp_hdr_valid_reg = 0, output_udp_hdr_valid_next;
reg [47:0] output_eth_dest_mac_reg = 0;
@ -189,20 +179,22 @@ reg [15:0] output_udp_source_port_reg = 0;
reg [15:0] output_udp_dest_port_reg = 0;
reg [15:0] output_udp_length_reg = 0;
reg [15:0] output_udp_checksum_reg = 0;
reg [63:0] output_udp_payload_tdata_reg = 0;
reg [7:0] output_udp_payload_tkeep_reg = 0;
reg output_udp_payload_tvalid_reg = 0;
reg output_udp_payload_tlast_reg = 0;
reg output_udp_payload_tuser_reg = 0;
reg input_ip_hdr_ready_reg = 0, input_ip_hdr_ready_next;
reg input_ip_payload_tready_reg = 0, input_ip_payload_tready_next;
reg busy_reg = 0;
reg error_header_early_termination_reg = 0, error_header_early_termination_next;
reg error_payload_early_termination_reg = 0, error_payload_early_termination_next;
reg [63:0] temp_udp_payload_tdata_reg = 0;
reg [7:0] temp_udp_payload_tkeep_reg = 0;
reg temp_udp_payload_tlast_reg = 0;
reg temp_udp_payload_tuser_reg = 0;
// internal datapath
reg [63:0] output_udp_payload_tdata_int;
reg [7:0] output_udp_payload_tkeep_int;
reg output_udp_payload_tvalid_int;
reg output_udp_payload_tready_int = 0;
reg output_udp_payload_tlast_int;
reg output_udp_payload_tuser_int;
wire output_udp_payload_tready_int_early;
assign input_ip_hdr_ready = input_ip_hdr_ready_reg;
assign input_ip_payload_tready = input_ip_payload_tready_reg;
@ -228,11 +220,6 @@ assign output_udp_source_port = output_udp_source_port_reg;
assign output_udp_dest_port = output_udp_dest_port_reg;
assign output_udp_length = output_udp_length_reg;
assign output_udp_checksum = output_udp_checksum_reg;
assign output_udp_payload_tdata = output_udp_payload_tdata_reg;
assign output_udp_payload_tkeep = output_udp_payload_tkeep_reg;
assign output_udp_payload_tvalid = output_udp_payload_tvalid_reg;
assign output_udp_payload_tlast = output_udp_payload_tlast_reg;
assign output_udp_payload_tuser = output_udp_payload_tuser_reg;
assign busy = busy_reg;
assign error_header_early_termination = error_header_early_termination_reg;
@ -271,17 +258,14 @@ endfunction
always @* begin
state_next = 2'bz;
transfer_in_out = 0;
transfer_in_temp = 0;
transfer_temp_out = 0;
assert_tlast = 0;
assert_tuser = 0;
tkeep_mask = 8'hff;
input_ip_hdr_ready_next = 0;
input_ip_payload_tready_next = 0;
store_ip_hdr = 0;
store_hdr_word_0 = 0;
store_last_word = 0;
frame_ptr_next = frame_ptr_reg;
output_udp_hdr_valid_next = output_udp_hdr_valid_reg & ~output_udp_hdr_ready;
@ -289,13 +273,21 @@ always @* begin
error_header_early_termination_next = 0;
error_payload_early_termination_next = 0;
output_udp_payload_tdata_int = 0;
output_udp_payload_tkeep_int = 0;
output_udp_payload_tvalid_int = 0;
output_udp_payload_tlast_int = 0;
output_udp_payload_tuser_int = 0;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for header
frame_ptr_next = 0;
input_ip_hdr_ready_next = ~output_udp_hdr_valid_reg;
if (input_ip_hdr_ready & input_ip_hdr_valid) begin
frame_ptr_next = 0;
input_ip_hdr_ready_next = 0;
input_ip_payload_tready_next = 1;
store_ip_hdr = 1;
state_next = STATE_READ_HEADER;
end else begin
@ -304,7 +296,9 @@ always @* begin
end
STATE_READ_HEADER: begin
// read header state
if (input_ip_payload_tvalid) begin
input_ip_payload_tready_next = 1;
if (input_ip_payload_tready & input_ip_payload_tvalid) begin
// word transfer in - store it
frame_ptr_next = frame_ptr_reg+8;
state_next = STATE_READ_HEADER;
@ -313,159 +307,95 @@ always @* begin
8'h00: begin
store_hdr_word_0 = 1;
output_udp_hdr_valid_next = 1;
state_next = STATE_READ_PAYLOAD_IDLE;
input_ip_payload_tready_next = output_udp_payload_tready_int_early;
state_next = STATE_READ_PAYLOAD;
end
endcase
if (input_ip_payload_tlast) begin
state_next = STATE_IDLE;
output_udp_hdr_valid_next = 0;
error_header_early_termination_next = 1;
output_udp_hdr_valid_next = 0;
input_ip_hdr_ready_next = ~output_udp_hdr_valid_reg;
input_ip_payload_tready_next = 0;
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_READ_HEADER;
end
end
STATE_READ_PAYLOAD_IDLE: begin
// idle; no data in registers
if (input_ip_payload_tvalid) begin
// word transfer in - store it in output register
transfer_in_out = 1;
STATE_READ_PAYLOAD: begin
// read payload
input_ip_payload_tready_next = output_udp_payload_tready_int_early;
output_udp_payload_tdata_int = input_ip_payload_tdata;
output_udp_payload_tkeep_int = input_ip_payload_tkeep;
output_udp_payload_tvalid_int = input_ip_payload_tvalid;
output_udp_payload_tlast_int = input_ip_payload_tlast;
output_udp_payload_tuser_int = input_ip_payload_tuser;
if (input_ip_payload_tready & input_ip_payload_tvalid) begin
// word transfer through
frame_ptr_next = frame_ptr_reg+keep2count(input_ip_payload_tkeep);
if (frame_ptr_next >= output_udp_length_reg) begin
// have entire payload
frame_ptr_next = output_udp_length_reg;
tkeep_mask = count2keep(output_udp_length_reg - frame_ptr_reg);
output_udp_payload_tkeep_int = input_ip_payload_tkeep & count2keep(output_udp_length_reg - frame_ptr_reg);
if (input_ip_payload_tlast) begin
state_next = STATE_READ_PAYLOAD_TRANSFER_LAST;
input_ip_payload_tready_next = 0;
input_ip_hdr_ready_next = ~output_udp_hdr_valid_reg;
state_next = STATE_IDLE;
end else begin
state_next = STATE_READ_PAYLOAD_TRANSFER_WAIT_LAST;
store_last_word = 1;
output_udp_payload_tvalid_int = 0;
state_next = STATE_READ_PAYLOAD_LAST;
end
end else begin
if (input_ip_payload_tlast) begin
// end of frame, but length does not match
assert_tuser = 1;
assert_tlast = 1;
error_payload_early_termination_next = 1;
state_next = STATE_READ_PAYLOAD_TRANSFER_LAST;
output_udp_payload_tuser_int = 1;
input_ip_payload_tready_next = 0;
input_ip_hdr_ready_next = ~output_udp_hdr_valid_reg;
state_next = STATE_IDLE;
end else begin
state_next = STATE_READ_PAYLOAD_TRANSFER;
state_next = STATE_READ_PAYLOAD;
end
end
end else begin
state_next = STATE_READ_PAYLOAD_IDLE;
state_next = STATE_READ_PAYLOAD;
end
end
STATE_READ_PAYLOAD_TRANSFER: begin
// read payload; data in output register
if (input_ip_payload_tvalid & output_udp_payload_tready) begin
// word transfer through - update output register
transfer_in_out = 1;
frame_ptr_next = frame_ptr_reg+keep2count(input_ip_payload_tkeep);
if (frame_ptr_next >= output_udp_length_reg) begin
// have entire payload
frame_ptr_next = output_udp_length_reg;
tkeep_mask = count2keep(output_udp_length_reg - frame_ptr_reg);
if (input_ip_payload_tlast) begin
state_next = STATE_READ_PAYLOAD_TRANSFER_LAST;
end else begin
state_next = STATE_READ_PAYLOAD_TRANSFER_WAIT_LAST;
end
end else begin
if (input_ip_payload_tlast) begin
// end of frame, but length does not match
assert_tuser = 1;
assert_tlast = 1;
error_payload_early_termination_next = 1;
state_next = STATE_READ_PAYLOAD_TRANSFER_LAST;
end else begin
state_next = STATE_READ_PAYLOAD_TRANSFER;
end
end
end else if (~input_ip_payload_tvalid & output_udp_payload_tready) begin
// word transfer out - go back to idle
state_next = STATE_READ_PAYLOAD_IDLE;
end else if (input_ip_payload_tvalid & ~output_udp_payload_tready) begin
// word transfer in - store in temp
transfer_in_temp = 1;
frame_ptr_next = frame_ptr_reg+keep2count(input_ip_payload_tkeep);
state_next = STATE_READ_PAYLOAD_TRANSFER_WAIT;
if (frame_ptr_next >= output_udp_length_reg) begin
// have entire payload
frame_ptr_next = output_udp_length_reg;
tkeep_mask = count2keep(output_udp_length_reg - frame_ptr_reg);
if (~input_ip_payload_tlast) begin
state_next = STATE_READ_PAYLOAD_TRANSFER_WAIT_LAST_WAIT;
end
end
end else begin
state_next = STATE_READ_PAYLOAD_TRANSFER;
end
end
STATE_READ_PAYLOAD_TRANSFER_WAIT: begin
// read payload; data in both output and temp registers
if (output_udp_payload_tready) begin
// transfer out - move temp to output
transfer_temp_out = 1;
if (temp_udp_payload_tlast_reg) begin
if (frame_ptr_next <= output_udp_length_reg) begin
// end of frame, but length does not match
assert_tuser = 1;
assert_tlast = 1;
error_payload_early_termination_next = 1;
end
state_next = STATE_READ_PAYLOAD_TRANSFER_LAST;
end else begin
if (frame_ptr_next >= output_udp_length_reg) begin
// not end of frame, but we have the entire payload
state_next = STATE_READ_PAYLOAD_TRANSFER_WAIT_LAST;
end else begin
state_next = STATE_READ_PAYLOAD_TRANSFER;
end
end
end else begin
state_next = STATE_READ_PAYLOAD_TRANSFER_WAIT;
end
end
STATE_READ_PAYLOAD_TRANSFER_LAST: begin
// read last payload word; data in output register; do not accept new data
if (output_udp_payload_tready) begin
// word transfer out - done
state_next = STATE_IDLE;
end else begin
state_next = STATE_READ_PAYLOAD_TRANSFER_LAST;
end
end
STATE_READ_PAYLOAD_TRANSFER_WAIT_LAST: begin
// wait for end of frame; data in output register; read and discard
if (input_ip_payload_tvalid) begin
STATE_READ_PAYLOAD_LAST: begin
// read and discard until end of frame
input_ip_payload_tready_next = output_udp_payload_tready_int_early;
output_udp_payload_tdata_int = last_word_data_reg;
output_udp_payload_tkeep_int = last_word_keep_reg;
output_udp_payload_tvalid_int = input_ip_payload_tvalid & input_ip_payload_tlast;
output_udp_payload_tlast_int = input_ip_payload_tlast;
output_udp_payload_tuser_int = input_ip_payload_tuser;
if (input_ip_payload_tready & input_ip_payload_tvalid) begin
if (input_ip_payload_tlast) begin
// assert tlast and transfer tuser
assert_tlast = 1;
assert_tuser = input_ip_payload_tuser;
state_next = STATE_READ_PAYLOAD_TRANSFER_LAST;
input_ip_hdr_ready_next = ~output_udp_hdr_valid_reg;
input_ip_payload_tready_next = 0;
state_next = STATE_IDLE;
end else begin
state_next = STATE_READ_PAYLOAD_TRANSFER_WAIT_LAST;
state_next = STATE_READ_PAYLOAD_LAST;
end
end else begin
state_next = STATE_READ_PAYLOAD_TRANSFER_WAIT_LAST;
end
end
STATE_READ_PAYLOAD_TRANSFER_WAIT_LAST_WAIT: begin
// wait for end of frame; data in both output and temp registers; read and discard
if (output_udp_payload_tready) begin
// transfer out - move temp to output
transfer_temp_out = 1;
state_next = STATE_READ_PAYLOAD_TRANSFER_WAIT_LAST;
end else begin
state_next = STATE_READ_PAYLOAD_TRANSFER_WAIT_LAST_WAIT;
state_next = STATE_READ_PAYLOAD_LAST;
end
end
STATE_WAIT_LAST: begin
// wait for end of frame; read and discard
if (input_ip_payload_tvalid) begin
input_ip_payload_tready_next = 1;
if (input_ip_payload_tready & input_ip_payload_tvalid) begin
if (input_ip_payload_tlast) begin
input_ip_hdr_ready_next = ~output_udp_hdr_valid_reg;
input_ip_payload_tready_next = 0;
state_next = STATE_IDLE;
end else begin
state_next = STATE_WAIT_LAST;
@ -481,6 +411,7 @@ always @(posedge clk or posedge rst) begin
if (rst) begin
state_reg <= STATE_IDLE;
frame_ptr_reg <= 0;
last_word_data_reg <= 0;
input_ip_hdr_ready_reg <= 0;
input_ip_payload_tready_reg <= 0;
output_udp_hdr_valid_reg <= 0;
@ -504,15 +435,6 @@ always @(posedge clk or posedge rst) begin
output_udp_dest_port_reg <= 0;
output_udp_length_reg <= 0;
output_udp_checksum_reg <= 0;
output_udp_payload_tdata_reg <= 0;
output_udp_payload_tkeep_reg <= 0;
output_udp_payload_tvalid_reg <= 0;
output_udp_payload_tlast_reg <= 0;
output_udp_payload_tuser_reg <= 0;
temp_udp_payload_tdata_reg <= 0;
temp_udp_payload_tkeep_reg <= 0;
temp_udp_payload_tlast_reg <= 0;
temp_udp_payload_tuser_reg <= 0;
busy_reg <= 0;
error_header_early_termination_reg <= 0;
error_payload_early_termination_reg <= 0;
@ -521,6 +443,9 @@ always @(posedge clk or posedge rst) begin
frame_ptr_reg <= frame_ptr_next;
input_ip_hdr_ready_reg <= input_ip_hdr_ready_next;
input_ip_payload_tready_reg <= input_ip_payload_tready_next;
output_udp_hdr_valid_reg <= output_udp_hdr_valid_next;
error_header_early_termination_reg <= error_header_early_termination_next;
@ -528,64 +453,6 @@ always @(posedge clk or posedge rst) begin
busy_reg <= state_next != STATE_IDLE;
// generate valid outputs
case (state_next)
STATE_IDLE: begin
// idle; accept new data
input_ip_hdr_ready_reg <= ~output_udp_hdr_valid;
input_ip_payload_tready_reg <= 0;
output_udp_payload_tvalid_reg <= 0;
end
STATE_READ_HEADER: begin
// read header; accept new data
input_ip_hdr_ready_reg <= 0;
input_ip_payload_tready_reg <= 1;
output_udp_payload_tvalid_reg <= 0;
end
STATE_READ_PAYLOAD_IDLE: begin
// read payload; no data in registers; accept new data
input_ip_hdr_ready_reg <= 0;
input_ip_payload_tready_reg <= 1;
output_udp_payload_tvalid_reg <= 0;
end
STATE_READ_PAYLOAD_TRANSFER: begin
// read payload; data in output register; accept new data
input_ip_hdr_ready_reg <= 0;
input_ip_payload_tready_reg <= 1;
output_udp_payload_tvalid_reg <= 1;
end
STATE_READ_PAYLOAD_TRANSFER_WAIT: begin
// read payload; data in output and temp registers; do not accept new data
input_ip_hdr_ready_reg <= 0;
input_ip_payload_tready_reg <= 0;
output_udp_payload_tvalid_reg <= 1;
end
STATE_READ_PAYLOAD_TRANSFER_LAST: begin
// read last payload word; data in output register; do not accept new data
input_ip_hdr_ready_reg <= 0;
input_ip_payload_tready_reg <= 0;
output_udp_payload_tvalid_reg <= 1;
end
STATE_READ_PAYLOAD_TRANSFER_WAIT_LAST: begin
// wait for end of frame; data in output register; read and discard
input_ip_hdr_ready_reg <= 0;
input_ip_payload_tready_reg <= 1;
output_udp_payload_tvalid_reg <= 0;
end
STATE_READ_PAYLOAD_TRANSFER_WAIT_LAST_WAIT: begin
// wait for end of frame; data in output and temp registers; do not accept new data
input_ip_hdr_ready_reg <= 0;
input_ip_payload_tready_reg <= 0;
output_udp_payload_tvalid_reg <= 1;
end
STATE_WAIT_LAST: begin
// wait for end of frame; read and discard
input_ip_hdr_ready_reg <= 0;
input_ip_payload_tready_reg <= 1;
output_udp_payload_tvalid_reg <= 0;
end
endcase
// datapath
if (store_ip_hdr) begin
output_eth_dest_mac_reg <= input_eth_dest_mac;
@ -606,6 +473,11 @@ always @(posedge clk or posedge rst) begin
output_ip_dest_ip_reg <= input_ip_dest_ip;
end
if (store_last_word) begin
last_word_data_reg <= output_udp_payload_tdata_int;
last_word_keep_reg <= output_udp_payload_tkeep_int;
end
if (store_hdr_word_0) begin
output_udp_source_port_reg[15: 8] <= input_ip_payload_tdata[ 7: 0];
output_udp_source_port_reg[ 7: 0] <= input_ip_payload_tdata[15: 8];
@ -616,26 +488,78 @@ always @(posedge clk or posedge rst) begin
output_udp_checksum_reg[15: 8] <= input_ip_payload_tdata[55:48];
output_udp_checksum_reg[ 7: 0] <= input_ip_payload_tdata[63:56];
end
end
end
if (transfer_in_out) begin
output_udp_payload_tdata_reg <= input_ip_payload_tdata;
output_udp_payload_tkeep_reg <= input_ip_payload_tkeep & tkeep_mask;
output_udp_payload_tlast_reg <= input_ip_payload_tlast;
output_udp_payload_tuser_reg <= input_ip_payload_tuser;
end else if (transfer_in_temp) begin
temp_udp_payload_tdata_reg <= input_ip_payload_tdata;
temp_udp_payload_tkeep_reg <= input_ip_payload_tkeep & tkeep_mask;
temp_udp_payload_tlast_reg <= input_ip_payload_tlast;
temp_udp_payload_tuser_reg <= input_ip_payload_tuser;
end else if (transfer_temp_out) begin
// output datapath logic
reg [63:0] output_udp_payload_tdata_reg = 0;
reg [7:0] output_udp_payload_tkeep_reg = 0;
reg output_udp_payload_tvalid_reg = 0;
reg output_udp_payload_tlast_reg = 0;
reg output_udp_payload_tuser_reg = 0;
reg [63:0] temp_udp_payload_tdata_reg = 0;
reg [7:0] temp_udp_payload_tkeep_reg = 0;
reg temp_udp_payload_tvalid_reg = 0;
reg temp_udp_payload_tlast_reg = 0;
reg temp_udp_payload_tuser_reg = 0;
// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle
assign output_udp_payload_tready_int_early = output_udp_payload_tready | (~temp_udp_payload_tvalid_reg & ~output_udp_payload_tvalid_reg) | (~temp_udp_payload_tvalid_reg & ~output_udp_payload_tvalid_int);
assign output_udp_payload_tdata = output_udp_payload_tdata_reg;
assign output_udp_payload_tkeep = output_udp_payload_tkeep_reg;
assign output_udp_payload_tvalid = output_udp_payload_tvalid_reg;
assign output_udp_payload_tlast = output_udp_payload_tlast_reg;
assign output_udp_payload_tuser = output_udp_payload_tuser_reg;
always @(posedge clk or posedge rst) begin
if (rst) begin
output_udp_payload_tdata_reg <= 0;
output_udp_payload_tkeep_reg <= 0;
output_udp_payload_tvalid_reg <= 0;
output_udp_payload_tlast_reg <= 0;
output_udp_payload_tuser_reg <= 0;
output_udp_payload_tready_int <= 0;
temp_udp_payload_tdata_reg <= 0;
temp_udp_payload_tkeep_reg <= 0;
temp_udp_payload_tvalid_reg <= 0;
temp_udp_payload_tlast_reg <= 0;
temp_udp_payload_tuser_reg <= 0;
end else begin
// transfer sink ready state to source
output_udp_payload_tready_int <= output_udp_payload_tready_int_early;
if (output_udp_payload_tready_int) begin
// input is ready
if (output_udp_payload_tready | ~output_udp_payload_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
output_udp_payload_tdata_reg <= output_udp_payload_tdata_int;
output_udp_payload_tkeep_reg <= output_udp_payload_tkeep_int;
output_udp_payload_tvalid_reg <= output_udp_payload_tvalid_int;
output_udp_payload_tlast_reg <= output_udp_payload_tlast_int;
output_udp_payload_tuser_reg <= output_udp_payload_tuser_int;
end else begin
// output is not ready and currently valid, store input in temp
temp_udp_payload_tdata_reg <= output_udp_payload_tdata_int;
temp_udp_payload_tkeep_reg <= output_udp_payload_tkeep_int;
temp_udp_payload_tvalid_reg <= output_udp_payload_tvalid_int;
temp_udp_payload_tlast_reg <= output_udp_payload_tlast_int;
temp_udp_payload_tuser_reg <= output_udp_payload_tuser_int;
end
end else if (output_udp_payload_tready) begin
// input is not ready, but output is ready
output_udp_payload_tdata_reg <= temp_udp_payload_tdata_reg;
output_udp_payload_tkeep_reg <= temp_udp_payload_tkeep_reg;
output_udp_payload_tvalid_reg <= temp_udp_payload_tvalid_reg;
output_udp_payload_tlast_reg <= temp_udp_payload_tlast_reg;
output_udp_payload_tuser_reg <= temp_udp_payload_tuser_reg;
temp_udp_payload_tdata_reg <= 0;
temp_udp_payload_tkeep_reg <= 0;
temp_udp_payload_tvalid_reg <= 0;
temp_udp_payload_tlast_reg <= 0;
temp_udp_payload_tuser_reg <= 0;
end
if (assert_tlast) output_udp_payload_tlast_reg <= 1;
if (assert_tuser) output_udp_payload_tuser_reg <= 1;
end
end

368
rtl/udp_ip_tx.v
View File

@ -128,48 +128,36 @@ UDP Frame
payload length octets
This module receives an IP frame with decoded fields and decodes
the AXI packet format. If the Ethertype does not match, the packet is
discarded.
This module receives a UDP frame with header fields in parallel along with the
payload in an AXI stream, combines the header with the payload, passes through
the IP headers, and transmits the complete IP payload on an AXI interface.
*/
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_WRITE_HEADER = 3'd1,
STATE_WRITE_PAYLOAD_IDLE = 3'd2,
STATE_WRITE_PAYLOAD_TRANSFER = 3'd3,
STATE_WRITE_PAYLOAD_TRANSFER_WAIT = 3'd4,
STATE_WRITE_PAYLOAD_TRANSFER_LAST = 3'd5,
STATE_WRITE_PAYLOAD_TRANSFER_WAIT_LAST = 3'd6,
STATE_WAIT_LAST = 3'd7;
STATE_WRITE_PAYLOAD = 3'd2,
STATE_WRITE_PAYLOAD_LAST = 3'd3,
STATE_WAIT_LAST = 3'd4;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg store_udp_hdr;
reg [7:0] write_hdr_data;
reg write_hdr_out;
reg transfer_in_out;
reg transfer_in_temp;
reg transfer_temp_out;
reg assert_tlast;
reg assert_tuser;
reg store_last_word;
reg [15:0] frame_ptr_reg = 0, frame_ptr_next;
reg [15:0] hdr_sum_reg = 0, hdr_sum_next;
reg [7:0] last_word_data_reg = 0;
reg [15:0] udp_source_port_reg = 0;
reg [15:0] udp_dest_port_reg = 0;
reg [15:0] udp_length_reg = 0;
reg [15:0] udp_checksum_reg = 0;
reg input_udp_hdr_ready_reg = 0;
reg input_udp_payload_tready_reg = 0;
reg input_udp_hdr_ready_reg = 0, input_udp_hdr_ready_next;
reg input_udp_payload_tready_reg = 0, input_udp_payload_tready_next;
reg output_ip_hdr_valid_reg = 0, output_ip_hdr_valid_next;
reg [47:0] output_eth_dest_mac_reg = 0;
@ -188,17 +176,17 @@ reg [7:0] output_ip_protocol_reg = 0;
reg [15:0] output_ip_header_checksum_reg = 0;
reg [31:0] output_ip_source_ip_reg = 0;
reg [31:0] output_ip_dest_ip_reg = 0;
reg [7:0] output_ip_payload_tdata_reg = 0;
reg output_ip_payload_tvalid_reg = 0;
reg output_ip_payload_tlast_reg = 0;
reg output_ip_payload_tuser_reg = 0;
reg busy_reg = 0;
reg error_payload_early_termination_reg = 0, error_payload_early_termination_next;
reg [7:0] temp_ip_payload_tdata_reg = 0;
reg temp_ip_payload_tlast_reg = 0;
reg temp_ip_payload_tuser_reg = 0;
// internal datapath
reg [7:0] output_ip_payload_tdata_int;
reg output_ip_payload_tvalid_int;
reg output_ip_payload_tready_int = 0;
reg output_ip_payload_tlast_int;
reg output_ip_payload_tuser_int;
wire output_ip_payload_tready_int_early;
assign input_udp_hdr_ready = input_udp_hdr_ready_reg;
assign input_udp_payload_tready = input_udp_payload_tready_reg;
@ -220,10 +208,6 @@ assign output_ip_protocol = output_ip_protocol_reg;
assign output_ip_header_checksum = output_ip_header_checksum_reg;
assign output_ip_source_ip = output_ip_source_ip_reg;
assign output_ip_dest_ip = output_ip_dest_ip_reg;
assign output_ip_payload_tdata = output_ip_payload_tdata_reg;
assign output_ip_payload_tvalid = output_ip_payload_tvalid_reg;
assign output_ip_payload_tlast = output_ip_payload_tlast_reg;
assign output_ip_payload_tuser = output_ip_payload_tuser_reg;
assign busy = busy_reg;
assign error_payload_early_termination = error_payload_early_termination_reg;
@ -231,37 +215,39 @@ assign error_payload_early_termination = error_payload_early_termination_reg;
always @* begin
state_next = 2'bz;
input_udp_hdr_ready_next = 0;
input_udp_payload_tready_next = 0;
store_udp_hdr = 0;
write_hdr_data = 0;
write_hdr_out = 0;
transfer_in_out = 0;
transfer_in_temp = 0;
transfer_temp_out = 0;
assert_tlast = 0;
assert_tuser = 0;
store_last_word = 0;
frame_ptr_next = frame_ptr_reg;
hdr_sum_next = hdr_sum_reg;
output_ip_hdr_valid_next = output_ip_hdr_valid_reg & ~output_ip_hdr_ready;
error_payload_early_termination_next = 0;
output_ip_payload_tdata_int = 0;
output_ip_payload_tvalid_int = 0;
output_ip_payload_tlast_int = 0;
output_ip_payload_tuser_int = 0;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for data
frame_ptr_next = 0;
input_udp_hdr_ready_next = ~output_ip_hdr_valid_reg;
if (input_udp_hdr_valid & input_udp_hdr_ready) begin
if (input_udp_hdr_ready & input_udp_hdr_valid) begin
store_udp_hdr = 1;
write_hdr_out = 1;
write_hdr_data = input_udp_source_port[15: 8];
input_udp_hdr_ready_next = 0;
output_ip_hdr_valid_next = 1;
frame_ptr_next = 1;
if (output_ip_payload_tready_int) begin
output_ip_payload_tvalid_int = 1;
output_ip_payload_tdata_int = input_udp_source_port[15: 8];
frame_ptr_next = 1;
end
state_next = STATE_WRITE_HEADER;
end else begin
state_next = STATE_IDLE;
@ -269,137 +255,92 @@ always @* begin
end
STATE_WRITE_HEADER: begin
// write header state
if (output_ip_payload_tready) begin
if (output_ip_payload_tready_int) begin
// word transfer out
frame_ptr_next = frame_ptr_reg+1;
output_ip_payload_tvalid_int = 1;
state_next = STATE_WRITE_HEADER;
write_hdr_out = 1;
case (frame_ptr_reg)
8'h01: write_hdr_data = udp_source_port_reg[ 7: 0];
8'h02: write_hdr_data = udp_dest_port_reg[15: 8];
8'h03: write_hdr_data = udp_dest_port_reg[ 7: 0];
8'h04: write_hdr_data = udp_length_reg[15: 8];
8'h05: write_hdr_data = udp_length_reg[ 7: 0];
8'h06: write_hdr_data = udp_checksum_reg[15: 8];
8'h00: output_ip_payload_tdata_int = input_udp_source_port[15: 8];
8'h01: output_ip_payload_tdata_int = udp_source_port_reg[ 7: 0];
8'h02: output_ip_payload_tdata_int = udp_dest_port_reg[15: 8];
8'h03: output_ip_payload_tdata_int = udp_dest_port_reg[ 7: 0];
8'h04: output_ip_payload_tdata_int = udp_length_reg[15: 8];
8'h05: output_ip_payload_tdata_int = udp_length_reg[ 7: 0];
8'h06: output_ip_payload_tdata_int = udp_checksum_reg[15: 8];
8'h07: begin
write_hdr_data = udp_checksum_reg[ 7: 0];
state_next = STATE_WRITE_PAYLOAD_TRANSFER;
output_ip_payload_tdata_int = udp_checksum_reg[ 7: 0];
input_udp_payload_tready_next = output_ip_payload_tready_int_early;
state_next = STATE_WRITE_PAYLOAD;
end
endcase
end else begin
state_next = STATE_WRITE_HEADER;
end
end
STATE_WRITE_PAYLOAD_IDLE: begin
// idle; no data in registers
if (input_udp_payload_tvalid) begin
// word transfer in - store it in output register
transfer_in_out = 1;
STATE_WRITE_PAYLOAD: begin
// write payload
input_udp_payload_tready_next = output_ip_payload_tready_int_early;
output_ip_payload_tdata_int = input_udp_payload_tdata;
output_ip_payload_tvalid_int = input_udp_payload_tvalid;
output_ip_payload_tlast_int = input_udp_payload_tlast;
output_ip_payload_tuser_int = input_udp_payload_tuser;
if (input_udp_payload_tready & input_udp_payload_tvalid) begin
// word transfer through
frame_ptr_next = frame_ptr_reg+1;
if (input_udp_payload_tlast) begin
if (frame_ptr_next != udp_length_reg) begin
// end of frame, but length does not match
assert_tuser = 1;
output_ip_payload_tuser_int = 1;
error_payload_early_termination_next = 1;
end
state_next = STATE_WRITE_PAYLOAD_TRANSFER_LAST;
input_udp_hdr_ready_next = ~output_ip_hdr_valid_reg;
input_udp_payload_tready_next = 0;
state_next = STATE_IDLE;
end else begin
if (frame_ptr_next == udp_length_reg) begin
// not end of frame, but we have the entire payload
state_next = STATE_WRITE_PAYLOAD_TRANSFER_WAIT_LAST;
store_last_word = 1;
output_ip_payload_tvalid_int = 0;
state_next = STATE_WRITE_PAYLOAD_LAST;
end else begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER;
state_next = STATE_WRITE_PAYLOAD;
end
end
end else begin
state_next = STATE_WRITE_PAYLOAD_IDLE;
state_next = STATE_WRITE_PAYLOAD;
end
end
STATE_WRITE_PAYLOAD_TRANSFER: begin
// write payload; data in output register
if (input_udp_payload_tvalid & output_ip_payload_tready) begin
// word transfer through - update output register
transfer_in_out = 1;
frame_ptr_next = frame_ptr_reg+1;
STATE_WRITE_PAYLOAD_LAST: begin
// read and discard until end of frame
input_udp_payload_tready_next = output_ip_payload_tready_int_early;
output_ip_payload_tdata_int = last_word_data_reg;
output_ip_payload_tvalid_int = input_udp_payload_tvalid & input_udp_payload_tlast;
output_ip_payload_tlast_int = input_udp_payload_tlast;
output_ip_payload_tuser_int = input_udp_payload_tuser;
if (input_udp_payload_tready & input_udp_payload_tvalid) begin
if (input_udp_payload_tlast) begin
if (frame_ptr_next != udp_length_reg) begin
// end of frame, but length does not match
assert_tuser = 1;
error_payload_early_termination_next = 1;
end
state_next = STATE_WRITE_PAYLOAD_TRANSFER_LAST;
input_udp_hdr_ready_next = ~output_ip_hdr_valid_reg;
input_udp_payload_tready_next = 0;
state_next = STATE_IDLE;
end else begin
if (frame_ptr_next == udp_length_reg) begin
// not end of frame, but we have the entire payload
state_next = STATE_WRITE_PAYLOAD_TRANSFER_WAIT_LAST;
end else begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER;
end
end
end else if (~input_udp_payload_tvalid & output_ip_payload_tready) begin
// word transfer out - go back to idle
state_next = STATE_WRITE_PAYLOAD_IDLE;
end else if (input_udp_payload_tvalid & ~output_ip_payload_tready) begin
// word transfer in - store in temp
transfer_in_temp = 1;
frame_ptr_next = frame_ptr_reg+1;
state_next = STATE_WRITE_PAYLOAD_TRANSFER_WAIT;
end else begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER;
end
end
STATE_WRITE_PAYLOAD_TRANSFER_WAIT: begin
// write payload; data in both output and temp registers
if (output_ip_payload_tready) begin
// transfer out - move temp to output
transfer_temp_out = 1;
if (temp_ip_payload_tlast_reg) begin
if (frame_ptr_next != udp_length_reg) begin
// end of frame, but length does not match
assert_tuser = 1;
error_payload_early_termination_next = 1;
end
state_next = STATE_WRITE_PAYLOAD_TRANSFER_LAST;
end else begin
if (frame_ptr_next == udp_length_reg) begin
// not end of frame, but we have the entire payload
state_next = STATE_WRITE_PAYLOAD_TRANSFER_WAIT_LAST;
end else begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER;
end
state_next = STATE_WRITE_PAYLOAD_LAST;
end
end else begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER_WAIT;
end
end
STATE_WRITE_PAYLOAD_TRANSFER_LAST: begin
// write last payload word; data in output register; do not accept new data
if (output_ip_payload_tready) begin
// word transfer out - done
state_next = STATE_IDLE;
end else begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER_LAST;
end
end
STATE_WRITE_PAYLOAD_TRANSFER_WAIT_LAST: begin
// wait for end of frame; data in output register; read and discard
if (input_udp_payload_tvalid) begin
if (input_udp_payload_tlast) begin
// assert tlast and transfer tuser
assert_tlast = 1;
assert_tuser = input_udp_payload_tuser;
state_next = STATE_WRITE_PAYLOAD_TRANSFER_LAST;
end else begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER_WAIT_LAST;
end
end else begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER_WAIT_LAST;
state_next = STATE_WRITE_PAYLOAD_LAST;
end
end
STATE_WAIT_LAST: begin
// wait for end of frame; read and discard
input_udp_payload_tready_next = 1;
if (input_udp_payload_tvalid) begin
if (input_udp_payload_tlast) begin
input_udp_hdr_ready_next = ~output_ip_hdr_valid_reg;
input_udp_payload_tready_next = 0;
state_next = STATE_IDLE;
end else begin
state_next = STATE_WAIT_LAST;
@ -415,7 +356,7 @@ always @(posedge clk or posedge rst) begin
if (rst) begin
state_reg <= STATE_IDLE;
frame_ptr_reg <= 0;
hdr_sum_reg <= 0;
last_word_data_reg <= 0;
input_udp_hdr_ready_reg <= 0;
input_udp_payload_tready_reg <= 0;
udp_source_port_reg <= 0;
@ -443,9 +384,6 @@ always @(posedge clk or posedge rst) begin
output_ip_payload_tvalid_reg <= 0;
output_ip_payload_tlast_reg <= 0;
output_ip_payload_tuser_reg <= 0;
temp_ip_payload_tdata_reg <= 0;
temp_ip_payload_tlast_reg <= 0;
temp_ip_payload_tuser_reg <= 0;
busy_reg <= 0;
error_payload_early_termination_reg <= 0;
end else begin
@ -453,7 +391,8 @@ always @(posedge clk or posedge rst) begin
frame_ptr_reg <= frame_ptr_next;
hdr_sum_reg <= hdr_sum_next;
input_udp_hdr_ready_reg <= input_udp_hdr_ready_next;
input_udp_payload_tready_reg <= input_udp_payload_tready_next;
output_ip_hdr_valid_reg <= output_ip_hdr_valid_next;
@ -461,58 +400,7 @@ always @(posedge clk or posedge rst) begin
error_payload_early_termination_reg <= error_payload_early_termination_next;
// generate valid outputs
case (state_next)
STATE_IDLE: begin
// idle; accept new data
input_udp_hdr_ready_reg <= 1;
input_udp_payload_tready_reg <= 0;
output_ip_payload_tvalid_reg <= 0;
end
STATE_WRITE_HEADER: begin
// write header
input_udp_hdr_ready_reg <= 0;
input_udp_payload_tready_reg <= 0;
output_ip_payload_tvalid_reg <= 1;
end
STATE_WRITE_PAYLOAD_IDLE: begin
// write payload; no data in registers; accept new data
input_udp_hdr_ready_reg <= 0;
input_udp_payload_tready_reg <= 1;
output_ip_payload_tvalid_reg <= 0;
end
STATE_WRITE_PAYLOAD_TRANSFER: begin
// write payload; data in output register; accept new data
input_udp_hdr_ready_reg <= 0;
input_udp_payload_tready_reg <= 1;
output_ip_payload_tvalid_reg <= 1;
end
STATE_WRITE_PAYLOAD_TRANSFER_WAIT: begin
// write payload; data in output and temp registers; do not accept new data
input_udp_hdr_ready_reg <= 0;
input_udp_payload_tready_reg <= 0;
output_ip_payload_tvalid_reg <= 1;
end
STATE_WRITE_PAYLOAD_TRANSFER_LAST: begin
// write last payload word; data in output register; do not accept new data
input_udp_hdr_ready_reg <= 0;
input_udp_payload_tready_reg <= 0;
output_ip_payload_tvalid_reg <= 1;
end
STATE_WRITE_PAYLOAD_TRANSFER_WAIT_LAST: begin
// wait for end of frame; data in output register; read and discard
input_udp_hdr_ready_reg <= 0;
input_udp_payload_tready_reg <= 1;
output_ip_payload_tvalid_reg <= 0;
end
STATE_WAIT_LAST: begin
// wait for end of frame; read and discard
input_udp_hdr_ready_reg <= 0;
input_udp_payload_tready_reg <= 1;
output_ip_payload_tvalid_reg <= 0;
end
endcase
// datapath
if (store_udp_hdr) begin
output_eth_dest_mac_reg <= input_eth_dest_mac;
output_eth_src_mac_reg <= input_eth_src_mac;
@ -536,26 +424,72 @@ always @(posedge clk or posedge rst) begin
udp_checksum_reg <= input_udp_checksum;
end
if (write_hdr_out) begin
output_ip_payload_tdata_reg <= write_hdr_data;
output_ip_payload_tlast_reg <= 0;
output_ip_payload_tuser_reg <= 0;
end else if (transfer_in_out) begin
output_ip_payload_tdata_reg <= input_udp_payload_tdata;
output_ip_payload_tlast_reg <= input_udp_payload_tlast;
output_ip_payload_tuser_reg <= input_udp_payload_tuser;
end else if (transfer_in_temp) begin
temp_ip_payload_tdata_reg <= input_udp_payload_tdata;
temp_ip_payload_tlast_reg <= input_udp_payload_tlast;
temp_ip_payload_tuser_reg <= input_udp_payload_tuser;
end else if (transfer_temp_out) begin
if (store_last_word) begin
last_word_data_reg <= output_ip_payload_tdata_int;
end
end
end
// output datapath logic
reg [7:0] output_ip_payload_tdata_reg = 0;
reg output_ip_payload_tvalid_reg = 0;
reg output_ip_payload_tlast_reg = 0;
reg output_ip_payload_tuser_reg = 0;
reg [7:0] temp_ip_payload_tdata_reg = 0;
reg temp_ip_payload_tvalid_reg = 0;
reg temp_ip_payload_tlast_reg = 0;
reg temp_ip_payload_tuser_reg = 0;
// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle
assign output_ip_payload_tready_int_early = output_ip_payload_tready | (~temp_ip_payload_tvalid_reg & ~output_ip_payload_tvalid_reg) | (~temp_ip_payload_tvalid_reg & ~output_ip_payload_tvalid_int);
assign output_ip_payload_tdata = output_ip_payload_tdata_reg;
assign output_ip_payload_tvalid = output_ip_payload_tvalid_reg;
assign output_ip_payload_tlast = output_ip_payload_tlast_reg;
assign output_ip_payload_tuser = output_ip_payload_tuser_reg;
always @(posedge clk or posedge rst) begin
if (rst) begin
output_ip_payload_tdata_reg <= 0;
output_ip_payload_tvalid_reg <= 0;
output_ip_payload_tlast_reg <= 0;
output_ip_payload_tuser_reg <= 0;
output_ip_payload_tready_int <= 0;
temp_ip_payload_tdata_reg <= 0;
temp_ip_payload_tvalid_reg <= 0;
temp_ip_payload_tlast_reg <= 0;
temp_ip_payload_tuser_reg <= 0;
end else begin
// transfer sink ready state to source
output_ip_payload_tready_int <= output_ip_payload_tready_int_early;
if (output_ip_payload_tready_int) begin
// input is ready
if (output_ip_payload_tready | ~output_ip_payload_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
output_ip_payload_tdata_reg <= output_ip_payload_tdata_int;
output_ip_payload_tvalid_reg <= output_ip_payload_tvalid_int;
output_ip_payload_tlast_reg <= output_ip_payload_tlast_int;
output_ip_payload_tuser_reg <= output_ip_payload_tuser_int;
end else begin
// output is not ready and currently valid, store input in temp
temp_ip_payload_tdata_reg <= output_ip_payload_tdata_int;
temp_ip_payload_tvalid_reg <= output_ip_payload_tvalid_int;
temp_ip_payload_tlast_reg <= output_ip_payload_tlast_int;
temp_ip_payload_tuser_reg <= output_ip_payload_tuser_int;
end
end else if (output_ip_payload_tready) begin
// input is not ready, but output is ready
output_ip_payload_tdata_reg <= temp_ip_payload_tdata_reg;
output_ip_payload_tvalid_reg <= temp_ip_payload_tvalid_reg;
output_ip_payload_tlast_reg <= temp_ip_payload_tlast_reg;
output_ip_payload_tuser_reg <= temp_ip_payload_tuser_reg;
temp_ip_payload_tdata_reg <= 0;
temp_ip_payload_tvalid_reg <= 0;
temp_ip_payload_tlast_reg <= 0;
temp_ip_payload_tuser_reg <= 0;
end
if (assert_tlast) output_ip_payload_tlast_reg <= 1;
if (assert_tuser) output_ip_payload_tuser_reg <= 1;
end
end

453
rtl/udp_ip_tx_64.v
View File

@ -130,52 +130,37 @@ UDP Frame
payload length octets
This module receives an IP frame with decoded fields and decodes
the AXI packet format. If the Ethertype does not match, the packet is
discarded.
This module receives a UDP frame with header fields in parallel along with the
payload in an AXI stream, combines the header with the payload, passes through
the IP headers, and transmits the complete IP payload on an AXI interface.
*/
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_WRITE_PAYLOAD_IDLE = 3'd1,
STATE_WRITE_PAYLOAD_TRANSFER = 3'd2,
STATE_WRITE_PAYLOAD_TRANSFER_WAIT = 3'd3,
STATE_WRITE_PAYLOAD_TRANSFER_LAST = 3'd4,
STATE_WRITE_PAYLOAD_TRANSFER_WAIT_LAST = 3'd5,
STATE_WRITE_PAYLOAD_TRANSFER_WAIT_LAST_WAIT = 3'd6,
STATE_WAIT_LAST = 3'd7;
STATE_WRITE_HEADER = 3'd1,
STATE_WRITE_PAYLOAD = 3'd2,
STATE_WRITE_PAYLOAD_LAST = 3'd3,
STATE_WAIT_LAST = 3'd4;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg store_udp_hdr;
reg [63:0] write_hdr_data;
reg [7:0] write_hdr_keep;
reg write_hdr_last;
reg write_hdr_user;
reg write_hdr_out;
reg transfer_in_out;
reg transfer_in_temp;
reg transfer_temp_out;
reg assert_tlast;
reg assert_tuser;
reg [7:0] tkeep_mask;
reg store_last_word;
reg [15:0] frame_ptr_reg = 0, frame_ptr_next;
reg [15:0] hdr_sum_reg = 0, hdr_sum_next;
reg [63:0] last_word_data_reg = 0;
reg [7:0] last_word_keep_reg = 0;
reg [15:0] udp_source_port_reg = 0;
reg [15:0] udp_dest_port_reg = 0;
reg [15:0] udp_length_reg = 0;
reg [15:0] udp_checksum_reg = 0;
reg input_udp_hdr_ready_reg = 0;
reg input_udp_payload_tready_reg = 0;
reg input_udp_hdr_ready_reg = 0, input_udp_hdr_ready_next;
reg input_udp_payload_tready_reg = 0, input_udp_payload_tready_next;
reg output_ip_hdr_valid_reg = 0, output_ip_hdr_valid_next;
reg [47:0] output_eth_dest_mac_reg = 0;
@ -194,19 +179,18 @@ reg [7:0] output_ip_protocol_reg = 0;
reg [15:0] output_ip_header_checksum_reg = 0;
reg [31:0] output_ip_source_ip_reg = 0;
reg [31:0] output_ip_dest_ip_reg = 0;
reg [63:0] output_ip_payload_tdata_reg = 0;
reg [7:0] output_ip_payload_tkeep_reg = 0;
reg output_ip_payload_tvalid_reg = 0;
reg output_ip_payload_tlast_reg = 0;
reg output_ip_payload_tuser_reg = 0;
reg busy_reg = 0;
reg error_payload_early_termination_reg = 0, error_payload_early_termination_next;
reg [63:0] temp_ip_payload_tdata_reg = 0;
reg [7:0] temp_ip_payload_tkeep_reg = 0;
reg temp_ip_payload_tlast_reg = 0;
reg temp_ip_payload_tuser_reg = 0;
// internal datapath
reg [63:0] output_ip_payload_tdata_int;
reg [7:0] output_ip_payload_tkeep_int;
reg output_ip_payload_tvalid_int;
reg output_ip_payload_tready_int = 0;
reg output_ip_payload_tlast_int;
reg output_ip_payload_tuser_int;
wire output_ip_payload_tready_int_early;
assign input_udp_hdr_ready = input_udp_hdr_ready_reg;
assign input_udp_payload_tready = input_udp_payload_tready_reg;
@ -228,11 +212,6 @@ assign output_ip_protocol = output_ip_protocol_reg;
assign output_ip_header_checksum = output_ip_header_checksum_reg;
assign output_ip_source_ip = output_ip_source_ip_reg;
assign output_ip_dest_ip = output_ip_dest_ip_reg;
assign output_ip_payload_tdata = output_ip_payload_tdata_reg;
assign output_ip_payload_tkeep = output_ip_payload_tkeep_reg;
assign output_ip_payload_tvalid = output_ip_payload_tvalid_reg;
assign output_ip_payload_tlast = output_ip_payload_tlast_reg;
assign output_ip_payload_tuser = output_ip_payload_tuser_reg;
assign busy = busy_reg;
assign error_payload_early_termination = error_payload_early_termination_reg;
@ -270,193 +249,153 @@ endfunction
always @* begin
state_next = 2'bz;
input_udp_hdr_ready_next = 0;
input_udp_payload_tready_next = 0;
store_udp_hdr = 0;
write_hdr_data = 0;
write_hdr_keep = 0;
write_hdr_last = 0;
write_hdr_user = 0;
write_hdr_out = 0;
transfer_in_out = 0;
transfer_in_temp = 0;
transfer_temp_out = 0;
assert_tlast = 0;
assert_tuser = 0;
tkeep_mask = 8'hff;
store_last_word = 0;
frame_ptr_next = frame_ptr_reg;
hdr_sum_next = hdr_sum_reg;
output_ip_hdr_valid_next = output_ip_hdr_valid_reg & ~output_ip_hdr_ready;
error_payload_early_termination_next = 0;
output_ip_payload_tdata_int = 0;
output_ip_payload_tkeep_int = 0;
output_ip_payload_tvalid_int = 0;
output_ip_payload_tlast_int = 0;
output_ip_payload_tuser_int = 0;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for data
frame_ptr_next = 0;
input_udp_hdr_ready_next = ~output_ip_hdr_valid_reg;
if (input_udp_hdr_valid & input_udp_hdr_ready) begin
if (input_udp_hdr_ready & input_udp_hdr_valid) begin
store_udp_hdr = 1;
write_hdr_out = 1;
write_hdr_data[ 7: 0] = input_udp_source_port[15: 8];
write_hdr_data[15: 8] = input_udp_source_port[ 7: 0];
write_hdr_data[23:16] = input_udp_dest_port[15: 8];
write_hdr_data[31:24] = input_udp_dest_port[ 7: 0];
write_hdr_data[39:32] = input_udp_length[15: 8];
write_hdr_data[47:40] = input_udp_length[ 7: 0];
write_hdr_data[55:48] = input_udp_checksum[15: 8];
write_hdr_data[63:56] = input_udp_checksum[ 7: 0];
write_hdr_keep = 8'hff;
input_udp_hdr_ready_next = 0;
output_ip_hdr_valid_next = 1;
frame_ptr_next = 8;
state_next = STATE_WRITE_PAYLOAD_TRANSFER;
state_next = STATE_WRITE_HEADER;
if (output_ip_payload_tready_int) begin
output_ip_payload_tvalid_int = 1;
output_ip_payload_tdata_int[ 7: 0] = input_udp_source_port[15: 8];
output_ip_payload_tdata_int[15: 8] = input_udp_source_port[ 7: 0];
output_ip_payload_tdata_int[23:16] = input_udp_dest_port[15: 8];
output_ip_payload_tdata_int[31:24] = input_udp_dest_port[ 7: 0];
output_ip_payload_tdata_int[39:32] = input_udp_length[15: 8];
output_ip_payload_tdata_int[47:40] = input_udp_length[ 7: 0];
output_ip_payload_tdata_int[55:48] = input_udp_checksum[15: 8];
output_ip_payload_tdata_int[63:56] = input_udp_checksum[ 7: 0];
output_ip_payload_tkeep_int = 8'hff;
frame_ptr_next = 8;
input_udp_payload_tready_next = output_ip_payload_tready_int_early;
state_next = STATE_WRITE_PAYLOAD;
end
end else begin
state_next = STATE_IDLE;
end
end
STATE_WRITE_PAYLOAD_IDLE: begin
// idle; no data in registers
if (input_udp_payload_tvalid) begin
// word transfer in - store it in output register
transfer_in_out = 1;
STATE_WRITE_HEADER: begin
// write header state
if (output_ip_payload_tready_int) begin
// word transfer out
frame_ptr_next = frame_ptr_reg+8;
output_ip_payload_tvalid_int = 1;
state_next = STATE_WRITE_HEADER;
case (frame_ptr_reg)
8'h00: begin
output_ip_payload_tdata_int[ 7: 0] = input_udp_source_port[15: 8];
output_ip_payload_tdata_int[15: 8] = input_udp_source_port[ 7: 0];
output_ip_payload_tdata_int[23:16] = input_udp_dest_port[15: 8];
output_ip_payload_tdata_int[31:24] = input_udp_dest_port[ 7: 0];
output_ip_payload_tdata_int[39:32] = input_udp_length[15: 8];
output_ip_payload_tdata_int[47:40] = input_udp_length[ 7: 0];
output_ip_payload_tdata_int[55:48] = input_udp_checksum[15: 8];
output_ip_payload_tdata_int[63:56] = input_udp_checksum[ 7: 0];
output_ip_payload_tkeep_int = 8'hff;
input_udp_payload_tready_next = output_ip_payload_tready_int_early;
state_next = STATE_WRITE_PAYLOAD;
end
endcase
end else begin
state_next = STATE_WRITE_HEADER;
end
end
STATE_WRITE_PAYLOAD: begin
// write payload
input_udp_payload_tready_next = output_ip_payload_tready_int_early;
output_ip_payload_tdata_int = input_udp_payload_tdata;
output_ip_payload_tkeep_int = input_udp_payload_tkeep;
output_ip_payload_tvalid_int = input_udp_payload_tvalid;
output_ip_payload_tlast_int = input_udp_payload_tlast;
output_ip_payload_tuser_int = input_udp_payload_tuser;
if (output_ip_payload_tready_int & input_udp_payload_tvalid) begin
// word transfer through
frame_ptr_next = frame_ptr_reg+keep2count(input_udp_payload_tkeep);
if (frame_ptr_next >= udp_length_reg) begin
// have entire payload
frame_ptr_next = udp_length_reg;
tkeep_mask = count2keep(udp_length_reg - frame_ptr_reg);
output_ip_payload_tkeep_int = count2keep(udp_length_reg - frame_ptr_reg);
if (input_udp_payload_tlast) begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER_LAST;
input_udp_payload_tready_next = 0;
input_udp_hdr_ready_next = ~output_ip_hdr_valid_reg;
state_next = STATE_IDLE;
end else begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER_WAIT_LAST;
store_last_word = 1;
output_ip_payload_tvalid_int = 0;
state_next = STATE_WRITE_PAYLOAD_LAST;
end
end else begin
if (input_udp_payload_tlast) begin
// end of frame, but length does not match
assert_tuser = 1;
assert_tlast = 1;
error_payload_early_termination_next = 1;
state_next = STATE_WRITE_PAYLOAD_TRANSFER_LAST;
output_ip_payload_tuser_int = 1;
input_udp_payload_tready_next = 0;
input_udp_hdr_ready_next = ~output_ip_hdr_valid_reg;
state_next = STATE_IDLE;
end else begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER;
state_next = STATE_WRITE_PAYLOAD;
end
end
end else begin
state_next = STATE_WRITE_PAYLOAD_IDLE;
state_next = STATE_WRITE_PAYLOAD;
end
end
STATE_WRITE_PAYLOAD_TRANSFER: begin
// write payload; data in output register
if (input_udp_payload_tvalid & output_ip_payload_tready) begin
// word transfer through - update output register
transfer_in_out = 1;
frame_ptr_next = frame_ptr_reg+keep2count(input_udp_payload_tkeep);
if (frame_ptr_next >= udp_length_reg) begin
// have entire payload
frame_ptr_next = udp_length_reg;
tkeep_mask = count2keep(udp_length_reg - frame_ptr_reg);
if (input_udp_payload_tlast) begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER_LAST;
end else begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER_WAIT_LAST;
end
end else begin
if (input_udp_payload_tlast) begin
// end of frame, but length does not match
assert_tuser = 1;
assert_tlast = 1;
error_payload_early_termination_next = 1;
state_next = STATE_WRITE_PAYLOAD_TRANSFER_LAST;
end else begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER;
end
end
end else if (~input_udp_payload_tvalid & output_ip_payload_tready) begin
// word transfer out - go back to idle
state_next = STATE_WRITE_PAYLOAD_IDLE;
end else if (input_udp_payload_tvalid & ~output_ip_payload_tready) begin
// word transfer in - store in temp
transfer_in_temp = 1;
frame_ptr_next = frame_ptr_reg+keep2count(input_udp_payload_tkeep);
state_next = STATE_WRITE_PAYLOAD_TRANSFER_WAIT;
if (frame_ptr_next >= udp_length_reg) begin
// have entire payload
frame_ptr_next = udp_length_reg;
tkeep_mask = count2keep(udp_length_reg - frame_ptr_reg);
if (~input_udp_payload_tlast) begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER_WAIT_LAST_WAIT;
end
end
end else begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER;
end
end
STATE_WRITE_PAYLOAD_TRANSFER_WAIT: begin
// write payload; data in both output and temp registers
if (output_ip_payload_tready) begin
// transfer out - move temp to output
transfer_temp_out = 1;
if (temp_ip_payload_tlast_reg) begin
if (frame_ptr_next < udp_length_reg) begin
// end of frame, but length does not match
assert_tuser = 1;
assert_tlast = 1;
error_payload_early_termination_next = 1;
end
state_next = STATE_WRITE_PAYLOAD_TRANSFER_LAST;
end else begin
if (frame_ptr_next >= udp_length_reg) begin
// not end of frame, but we have the entire payload
state_next = STATE_WRITE_PAYLOAD_TRANSFER_WAIT_LAST;
end else begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER;
end
end
end else begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER_WAIT;
end
end
STATE_WRITE_PAYLOAD_TRANSFER_LAST: begin
// write last payload word; data in output register; do not accept new data
if (output_ip_payload_tready) begin
// word transfer out - done
state_next = STATE_IDLE;
end else begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER_LAST;
end
end
STATE_WRITE_PAYLOAD_TRANSFER_WAIT_LAST: begin
// wait for end of frame; data in output register; read and discard
if (input_udp_payload_tvalid) begin
STATE_WRITE_PAYLOAD_LAST: begin
// read and discard until end of frame
input_udp_payload_tready_next = output_ip_payload_tready_int_early;
output_ip_payload_tdata_int = last_word_data_reg;
output_ip_payload_tkeep_int = last_word_keep_reg;
output_ip_payload_tvalid_int = input_udp_payload_tvalid & input_udp_payload_tlast;
output_ip_payload_tlast_int = input_udp_payload_tlast;
output_ip_payload_tuser_int = input_udp_payload_tuser;
if (input_udp_payload_tready & input_udp_payload_tvalid) begin
if (input_udp_payload_tlast) begin
// assert tlast and transfer tuser
assert_tlast = 1;
assert_tuser = input_udp_payload_tuser;
state_next = STATE_WRITE_PAYLOAD_TRANSFER_LAST;
input_udp_hdr_ready_next = ~output_ip_hdr_valid_reg;
input_udp_payload_tready_next = 0;
state_next = STATE_IDLE;
end else begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER_WAIT_LAST;
state_next = STATE_WRITE_PAYLOAD_LAST;
end
end else begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER_WAIT_LAST;
end
end
STATE_WRITE_PAYLOAD_TRANSFER_WAIT_LAST_WAIT: begin
// wait for end of frame; data in both output and temp registers; read and discard
if (output_ip_payload_tready) begin
// transfer out - move temp to output
transfer_temp_out = 1;
state_next = STATE_WRITE_PAYLOAD_TRANSFER_WAIT_LAST;
end else begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER_WAIT_LAST_WAIT;
state_next = STATE_WRITE_PAYLOAD_LAST;
end
end
STATE_WAIT_LAST: begin
// wait for end of frame; read and discard
input_udp_payload_tready_next = 1;
if (input_udp_payload_tvalid) begin
if (input_udp_payload_tlast) begin
input_udp_hdr_ready_next = ~output_ip_hdr_valid_reg;
input_udp_payload_tready_next = 0;
state_next = STATE_IDLE;
end else begin
state_next = STATE_WAIT_LAST;
@ -472,7 +411,8 @@ always @(posedge clk or posedge rst) begin
if (rst) begin
state_reg <= STATE_IDLE;
frame_ptr_reg <= 0;
hdr_sum_reg <= 0;
last_word_data_reg <= 0;
last_word_keep_reg <= 0;
input_udp_hdr_ready_reg <= 0;
input_udp_payload_tready_reg <= 0;
udp_source_port_reg <= 0;
@ -500,9 +440,6 @@ always @(posedge clk or posedge rst) begin
output_ip_payload_tvalid_reg <= 0;
output_ip_payload_tlast_reg <= 0;
output_ip_payload_tuser_reg <= 0;
temp_ip_payload_tdata_reg <= 0;
temp_ip_payload_tlast_reg <= 0;
temp_ip_payload_tuser_reg <= 0;
busy_reg <= 0;
error_payload_early_termination_reg <= 0;
end else begin
@ -510,7 +447,8 @@ always @(posedge clk or posedge rst) begin
frame_ptr_reg <= frame_ptr_next;
hdr_sum_reg <= hdr_sum_next;
input_udp_hdr_ready_reg <= input_udp_hdr_ready_next;
input_udp_payload_tready_reg <= input_udp_payload_tready_next;
output_ip_hdr_valid_reg <= output_ip_hdr_valid_next;
@ -518,58 +456,7 @@ always @(posedge clk or posedge rst) begin
error_payload_early_termination_reg <= error_payload_early_termination_next;
// generate valid outputs
case (state_next)
STATE_IDLE: begin
// idle; accept new data
input_udp_hdr_ready_reg <= 1;
input_udp_payload_tready_reg <= 0;
output_ip_payload_tvalid_reg <= 0;
end
STATE_WRITE_PAYLOAD_IDLE: begin
// write payload; no data in registers; accept new data
input_udp_hdr_ready_reg <= 0;
input_udp_payload_tready_reg <= 1;
output_ip_payload_tvalid_reg <= 0;
end
STATE_WRITE_PAYLOAD_TRANSFER: begin
// write payload; data in output register; accept new data
input_udp_hdr_ready_reg <= 0;
input_udp_payload_tready_reg <= 1;
output_ip_payload_tvalid_reg <= 1;
end
STATE_WRITE_PAYLOAD_TRANSFER_WAIT: begin
// write payload; data in output and temp registers; do not accept new data
input_udp_hdr_ready_reg <= 0;
input_udp_payload_tready_reg <= 0;
output_ip_payload_tvalid_reg <= 1;
end
STATE_WRITE_PAYLOAD_TRANSFER_LAST: begin
// write last payload word; data in output register; do not accept new data
input_udp_hdr_ready_reg <= 0;
input_udp_payload_tready_reg <= 0;
output_ip_payload_tvalid_reg <= 1;
end
STATE_WRITE_PAYLOAD_TRANSFER_WAIT_LAST: begin
// wait for end of frame; data in output register; read and discard
input_udp_hdr_ready_reg <= 0;
input_udp_payload_tready_reg <= 1;
output_ip_payload_tvalid_reg <= 0;
end
STATE_WRITE_PAYLOAD_TRANSFER_WAIT_LAST_WAIT: begin
// wait for end of frame; data in output and temp registers; do not accept new data
input_udp_hdr_ready_reg <= 0;
input_udp_payload_tready_reg <= 0;
output_ip_payload_tvalid_reg <= 1;
end
STATE_WAIT_LAST: begin
// wait for end of frame; read and discard
input_udp_hdr_ready_reg <= 0;
input_udp_payload_tready_reg <= 1;
output_ip_payload_tvalid_reg <= 0;
end
endcase
// datapath
if (store_udp_hdr) begin
output_eth_dest_mac_reg <= input_eth_dest_mac;
output_eth_src_mac_reg <= input_eth_src_mac;
@ -593,30 +480,82 @@ always @(posedge clk or posedge rst) begin
udp_checksum_reg <= input_udp_checksum;
end
if (write_hdr_out) begin
output_ip_payload_tdata_reg <= write_hdr_data;
output_ip_payload_tkeep_reg <= write_hdr_keep & tkeep_mask;
output_ip_payload_tlast_reg <= write_hdr_last;
output_ip_payload_tuser_reg <= write_hdr_user;
end else if (transfer_in_out) begin
output_ip_payload_tdata_reg <= input_udp_payload_tdata;
output_ip_payload_tkeep_reg <= input_udp_payload_tkeep & tkeep_mask;
output_ip_payload_tlast_reg <= input_udp_payload_tlast;
output_ip_payload_tuser_reg <= input_udp_payload_tuser;
end else if (transfer_in_temp) begin
temp_ip_payload_tdata_reg <= input_udp_payload_tdata;
temp_ip_payload_tkeep_reg <= input_udp_payload_tkeep & tkeep_mask;
temp_ip_payload_tlast_reg <= input_udp_payload_tlast;
temp_ip_payload_tuser_reg <= input_udp_payload_tuser;
end else if (transfer_temp_out) begin
if (store_last_word) begin
last_word_data_reg <= output_ip_payload_tdata_int;
last_word_keep_reg <= output_ip_payload_tkeep_int;
end
end
end
// output datapath logic
reg [63:0] output_ip_payload_tdata_reg = 0;
reg [7:0] output_ip_payload_tkeep_reg = 0;
reg output_ip_payload_tvalid_reg = 0;
reg output_ip_payload_tlast_reg = 0;
reg output_ip_payload_tuser_reg = 0;
reg [63:0] temp_ip_payload_tdata_reg = 0;
reg [7:0] temp_ip_payload_tkeep_reg = 0;
reg temp_ip_payload_tvalid_reg = 0;
reg temp_ip_payload_tlast_reg = 0;
reg temp_ip_payload_tuser_reg = 0;
// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle
assign output_ip_payload_tready_int_early = output_ip_payload_tready | (~temp_ip_payload_tvalid_reg & ~output_ip_payload_tvalid_reg) | (~temp_ip_payload_tvalid_reg & ~output_ip_payload_tvalid_int);
assign output_ip_payload_tdata = output_ip_payload_tdata_reg;
assign output_ip_payload_tkeep = output_ip_payload_tkeep_reg;
assign output_ip_payload_tvalid = output_ip_payload_tvalid_reg;
assign output_ip_payload_tlast = output_ip_payload_tlast_reg;
assign output_ip_payload_tuser = output_ip_payload_tuser_reg;
always @(posedge clk or posedge rst) begin
if (rst) begin
output_ip_payload_tdata_reg <= 0;
output_ip_payload_tkeep_reg <= 0;
output_ip_payload_tvalid_reg <= 0;
output_ip_payload_tlast_reg <= 0;
output_ip_payload_tuser_reg <= 0;
output_ip_payload_tready_int <= 0;
temp_ip_payload_tdata_reg <= 0;
temp_ip_payload_tkeep_reg <= 0;
temp_ip_payload_tvalid_reg <= 0;
temp_ip_payload_tlast_reg <= 0;
temp_ip_payload_tuser_reg <= 0;
end else begin
// transfer sink ready state to source
output_ip_payload_tready_int <= output_ip_payload_tready_int_early;
if (output_ip_payload_tready_int) begin
// input is ready
if (output_ip_payload_tready | ~output_ip_payload_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
output_ip_payload_tdata_reg <= output_ip_payload_tdata_int;
output_ip_payload_tkeep_reg <= output_ip_payload_tkeep_int;
output_ip_payload_tvalid_reg <= output_ip_payload_tvalid_int;
output_ip_payload_tlast_reg <= output_ip_payload_tlast_int;
output_ip_payload_tuser_reg <= output_ip_payload_tuser_int;
end else begin
// output is not ready and currently valid, store input in temp
temp_ip_payload_tdata_reg <= output_ip_payload_tdata_int;
temp_ip_payload_tkeep_reg <= output_ip_payload_tkeep_int;
temp_ip_payload_tvalid_reg <= output_ip_payload_tvalid_int;
temp_ip_payload_tlast_reg <= output_ip_payload_tlast_int;
temp_ip_payload_tuser_reg <= output_ip_payload_tuser_int;
end
end else if (output_ip_payload_tready) begin
// input is not ready, but output is ready
output_ip_payload_tdata_reg <= temp_ip_payload_tdata_reg;
output_ip_payload_tkeep_reg <= temp_ip_payload_tkeep_reg;
output_ip_payload_tvalid_reg <= temp_ip_payload_tvalid_reg;
output_ip_payload_tlast_reg <= temp_ip_payload_tlast_reg;
output_ip_payload_tuser_reg <= temp_ip_payload_tuser_reg;
temp_ip_payload_tdata_reg <= 0;
temp_ip_payload_tkeep_reg <= 0;
temp_ip_payload_tvalid_reg <= 0;
temp_ip_payload_tlast_reg <= 0;
temp_ip_payload_tuser_reg <= 0;
end
if (assert_tlast) output_ip_payload_tlast_reg <= 1;
if (assert_tuser) output_ip_payload_tuser_reg <= 1;
end
end