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Update lfsr.v
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
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rtl/lfsr.v
173
rtl/lfsr.v
@ -1,6 +1,6 @@
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/*
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Copyright (c) 2016-2018 Alex Forencich
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Copyright (c) 2016-2023 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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@ -184,6 +184,7 @@ Name Configuration Length Polynomial Initial value Note
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CRC16-IBM Galois, bit-reverse 16 16'h8005 16'hffff
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CRC16-CCITT Galois 16 16'h1021 16'h1d0f
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CRC32 Galois, bit-reverse 32 32'h04c11db7 32'hffffffff Ethernet FCS; invert final output
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CRC32C Galois, bit-reverse 32 32'h1edc6f41 32'hffffffff iSCSI, Intel CRC32 instruction; invert final output
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PRBS6 Fibonacci 6 6'h21 any
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PRBS7 Fibonacci 7 7'h41 any
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PRBS9 Fibonacci 9 9'h021 any ITU V.52
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@ -200,44 +201,47 @@ PRBS31 Fibonacci, inverted 31 31'h10000001 any
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*/
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reg [LFSR_WIDTH-1:0] lfsr_mask_state[LFSR_WIDTH-1:0];
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reg [DATA_WIDTH-1:0] lfsr_mask_data[LFSR_WIDTH-1:0];
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reg [LFSR_WIDTH-1:0] output_mask_state[DATA_WIDTH-1:0];
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reg [DATA_WIDTH-1:0] output_mask_data[DATA_WIDTH-1:0];
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function [LFSR_WIDTH+DATA_WIDTH-1:0] lfsr_mask(input [31:0] index);
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reg [LFSR_WIDTH-1:0] lfsr_mask_state[LFSR_WIDTH-1:0];
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reg [DATA_WIDTH-1:0] lfsr_mask_data[LFSR_WIDTH-1:0];
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reg [LFSR_WIDTH-1:0] output_mask_state[DATA_WIDTH-1:0];
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reg [DATA_WIDTH-1:0] output_mask_data[DATA_WIDTH-1:0];
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reg [LFSR_WIDTH-1:0] state_val = 0;
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reg [DATA_WIDTH-1:0] data_val = 0;
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reg [LFSR_WIDTH-1:0] state_val;
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reg [DATA_WIDTH-1:0] data_val;
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integer i, j, k;
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reg [DATA_WIDTH-1:0] data_mask;
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initial begin
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integer i, j;
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begin
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// init bit masks
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for (i = 0; i < LFSR_WIDTH; i = i + 1) begin
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lfsr_mask_state[i] = {LFSR_WIDTH{1'b0}};
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lfsr_mask_state[i] = 0;
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lfsr_mask_state[i][i] = 1'b1;
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lfsr_mask_data[i] = {DATA_WIDTH{1'b0}};
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lfsr_mask_data[i] = 0;
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end
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for (i = 0; i < DATA_WIDTH; i = i + 1) begin
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output_mask_state[i] = {LFSR_WIDTH{1'b0}};
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output_mask_state[i] = 0;
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if (i < LFSR_WIDTH) begin
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output_mask_state[i][i] = 1'b1;
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end
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output_mask_data[i] = {DATA_WIDTH{1'b0}};
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output_mask_data[i] = 0;
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end
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// simulate shift register
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if (LFSR_CONFIG == "FIBONACCI") begin
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// Fibonacci configuration
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for (i = DATA_WIDTH-1; i >= 0; i = i - 1) begin
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for (data_mask = {1'b1, {DATA_WIDTH-1{1'b0}}}; data_mask != 0; data_mask = data_mask >> 1) begin
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// determine shift in value
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// current value in last FF, XOR with input data bit (MSB first)
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state_val = lfsr_mask_state[LFSR_WIDTH-1];
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data_val = lfsr_mask_data[LFSR_WIDTH-1];
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data_val = data_val ^ (1 << i);
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data_val = data_val ^ data_mask;
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// add XOR inputs from correct indicies
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for (j = 1; j < LFSR_WIDTH; j = j + 1) begin
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if (LFSR_POLY & (1 << j)) begin
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if ((LFSR_POLY >> j) & 1) begin
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state_val = lfsr_mask_state[j-1] ^ state_val;
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data_val = lfsr_mask_data[j-1] ^ data_val;
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end
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@ -257,19 +261,19 @@ initial begin
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if (LFSR_FEED_FORWARD) begin
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// only shift in new input data
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state_val = {LFSR_WIDTH{1'b0}};
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data_val = 1 << i;
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data_val = data_mask;
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end
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lfsr_mask_state[0] = state_val;
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lfsr_mask_data[0] = data_val;
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end
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end else if (LFSR_CONFIG == "GALOIS") begin
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// Galois configuration
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for (i = DATA_WIDTH-1; i >= 0; i = i - 1) begin
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for (data_mask = {1'b1, {DATA_WIDTH-1{1'b0}}}; data_mask != 0; data_mask = data_mask >> 1) begin
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// determine shift in value
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// current value in last FF, XOR with input data bit (MSB first)
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state_val = lfsr_mask_state[LFSR_WIDTH-1];
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data_val = lfsr_mask_data[LFSR_WIDTH-1];
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data_val = data_val ^ (1 << i);
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data_val = data_val ^ data_mask;
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// shift
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for (j = LFSR_WIDTH-1; j > 0; j = j - 1) begin
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@ -285,14 +289,14 @@ initial begin
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if (LFSR_FEED_FORWARD) begin
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// only shift in new input data
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state_val = {LFSR_WIDTH{1'b0}};
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data_val = 1 << i;
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data_val = data_mask;
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end
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lfsr_mask_state[0] = state_val;
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lfsr_mask_data[0] = data_val;
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// add XOR inputs at correct indicies
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for (j = 1; j < LFSR_WIDTH; j = j + 1) begin
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if (LFSR_POLY & (1 << j)) begin
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if ((LFSR_POLY >> j) & 1) begin
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lfsr_mask_state[j] = lfsr_mask_state[j] ^ state_val;
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lfsr_mask_data[j] = lfsr_mask_data[j] ^ data_val;
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end
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@ -305,56 +309,39 @@ initial begin
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// reverse bits if selected
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if (REVERSE) begin
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// reverse order
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for (i = 0; i < LFSR_WIDTH/2; i = i + 1) begin
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state_val = lfsr_mask_state[i];
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data_val = lfsr_mask_data[i];
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lfsr_mask_state[i] = lfsr_mask_state[LFSR_WIDTH-i-1];
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lfsr_mask_data[i] = lfsr_mask_data[LFSR_WIDTH-i-1];
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lfsr_mask_state[LFSR_WIDTH-i-1] = state_val;
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lfsr_mask_data[LFSR_WIDTH-i-1] = data_val;
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end
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for (i = 0; i < DATA_WIDTH/2; i = i + 1) begin
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state_val = output_mask_state[i];
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data_val = output_mask_data[i];
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output_mask_state[i] = output_mask_state[DATA_WIDTH-i-1];
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output_mask_data[i] = output_mask_data[DATA_WIDTH-i-1];
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output_mask_state[DATA_WIDTH-i-1] = state_val;
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output_mask_data[DATA_WIDTH-i-1] = data_val;
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end
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// reverse bits
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if (index < LFSR_WIDTH) begin
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state_val = 0;
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for (i = 0; i < LFSR_WIDTH; i = i + 1) begin
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state_val = 0;
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for (j = 0; j < LFSR_WIDTH; j = j + 1) begin
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state_val[j] = lfsr_mask_state[i][LFSR_WIDTH-j-1];
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state_val[i] = lfsr_mask_state[LFSR_WIDTH-index-1][LFSR_WIDTH-i-1];
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end
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lfsr_mask_state[i] = state_val;
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data_val = 0;
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for (j = 0; j < DATA_WIDTH; j = j + 1) begin
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data_val[j] = lfsr_mask_data[i][DATA_WIDTH-j-1];
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end
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lfsr_mask_data[i] = data_val;
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end
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for (i = 0; i < DATA_WIDTH; i = i + 1) begin
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state_val = 0;
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for (j = 0; j < LFSR_WIDTH; j = j + 1) begin
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state_val[j] = output_mask_state[i][LFSR_WIDTH-j-1];
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data_val[i] = lfsr_mask_data[LFSR_WIDTH-index-1][DATA_WIDTH-i-1];
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end
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end else begin
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state_val = 0;
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for (i = 0; i < LFSR_WIDTH; i = i + 1) begin
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state_val[i] = output_mask_state[DATA_WIDTH-(index-LFSR_WIDTH)-1][LFSR_WIDTH-i-1];
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end
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output_mask_state[i] = state_val;
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data_val = 0;
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for (j = 0; j < DATA_WIDTH; j = j + 1) begin
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data_val[j] = output_mask_data[i][DATA_WIDTH-j-1];
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end
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output_mask_data[i] = data_val;
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for (i = 0; i < DATA_WIDTH; i = i + 1) begin
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data_val[i] = output_mask_data[DATA_WIDTH-(index-LFSR_WIDTH)-1][DATA_WIDTH-i-1];
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end
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end
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// for (i = 0; i < LFSR_WIDTH; i = i + 1) begin
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// $display("%b %b", lfsr_mask_state[i], lfsr_mask_data[i]);
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// end
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end
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end else begin
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if (index < LFSR_WIDTH) begin
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state_val = lfsr_mask_state[index];
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data_val = lfsr_mask_data[index];
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end else begin
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state_val = output_mask_state[index-LFSR_WIDTH];
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data_val = output_mask_data[index-LFSR_WIDTH];
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end
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end
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lfsr_mask = {data_val, state_val};
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end
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endfunction
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// synthesis translate_off
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`define SIMULATION
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@ -380,11 +367,13 @@ if (STYLE_INT == "REDUCTION") begin
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// slightly smaller than generated code with Quartus
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// --> better for simulation
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for (n = 0; n < LFSR_WIDTH; n = n + 1) begin : loop1
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assign state_out[n] = ^{(state_in & lfsr_mask_state[n]), (data_in & lfsr_mask_data[n])};
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for (n = 0; n < LFSR_WIDTH; n = n + 1) begin : lfsr_state
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wire [LFSR_WIDTH+DATA_WIDTH-1:0] mask = lfsr_mask(n);
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assign state_out[n] = ^({data_in, state_in} & mask);
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end
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for (n = 0; n < DATA_WIDTH; n = n + 1) begin : loop2
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assign data_out[n] = ^{(state_in & output_mask_state[n]), (data_in & output_mask_data[n])};
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for (n = 0; n < DATA_WIDTH; n = n + 1) begin : lfsr_data
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wire [LFSR_WIDTH+DATA_WIDTH-1:0] mask = lfsr_mask(n+LFSR_WIDTH);
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assign data_out[n] = ^({data_in, state_in} & mask);
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end
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end else if (STYLE_INT == "LOOP") begin
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@ -395,36 +384,48 @@ end else if (STYLE_INT == "LOOP") begin
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// same size as generated code with Quartus
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// --> better for synthesis
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reg [LFSR_WIDTH-1:0] state_out_reg = 0;
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reg [DATA_WIDTH-1:0] data_out_reg = 0;
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for (n = 0; n < LFSR_WIDTH; n = n + 1) begin : lfsr_state
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wire [LFSR_WIDTH+DATA_WIDTH-1:0] mask = lfsr_mask(n);
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assign state_out = state_out_reg;
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assign data_out = data_out_reg;
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reg state_reg;
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assign state_out[n] = state_reg;
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integer i;
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always @* begin
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state_reg = 1'b0;
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for (i = 0; i < LFSR_WIDTH; i = i + 1) begin
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state_out_reg[i] = 0;
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for (j = 0; j < LFSR_WIDTH; j = j + 1) begin
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if (lfsr_mask_state[i][j]) begin
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state_out_reg[i] = state_out_reg[i] ^ state_in[j];
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end
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end
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for (j = 0; j < DATA_WIDTH; j = j + 1) begin
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if (lfsr_mask_data[i][j]) begin
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state_out_reg[i] = state_out_reg[i] ^ data_in[j];
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end
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if (mask[i]) begin
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state_reg = state_reg ^ state_in[i];
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end
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end
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for (i = 0; i < DATA_WIDTH; i = i + 1) begin
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data_out_reg[i] = 0;
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for (j = 0; j < LFSR_WIDTH; j = j + 1) begin
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if (output_mask_state[i][j]) begin
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data_out_reg[i] = data_out_reg[i] ^ state_in[j];
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if (mask[i+LFSR_WIDTH]) begin
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state_reg = state_reg ^ data_in[i];
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end
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end
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for (j = 0; j < DATA_WIDTH; j = j + 1) begin
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if (output_mask_data[i][j]) begin
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data_out_reg[i] = data_out_reg[i] ^ data_in[j];
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end
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end
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for (n = 0; n < DATA_WIDTH; n = n + 1) begin : lfsr_data
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wire [LFSR_WIDTH+DATA_WIDTH-1:0] mask = lfsr_mask(n+LFSR_WIDTH);
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reg data_reg;
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assign data_out[n] = data_reg;
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integer i;
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always @* begin
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data_reg = 1'b0;
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for (i = 0; i < LFSR_WIDTH; i = i + 1) begin
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if (mask[i]) begin
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data_reg = data_reg ^ state_in[i];
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end
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end
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for (i = 0; i < DATA_WIDTH; i = i + 1) begin
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if (mask[i+LFSR_WIDTH]) begin
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data_reg = data_reg ^ data_in[i];
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end
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end
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end
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