FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-14 06:43:18 +08:00
Code Issues Projects Releases Wiki Activity

Replace eth_crc modules for generic lfsr module

Browse Source
This commit is contained in:
Alex Forencich 2016-06-28 17:31:58 -07:00
parent ccd8cd8c2e
commit 47ca9a8725
32 changed files with 490 additions and 262 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
example/ATLYS/fpga/fpga/Makefile
View File

@ -19,7 +19,7 @@ SYN_FILES += lib/eth/rtl/eth_mac_1g_fifo.v
SYN_FILES += lib/eth/rtl/eth_mac_1g.v
SYN_FILES += lib/eth/rtl/eth_mac_1g_rx.v
SYN_FILES += lib/eth/rtl/eth_mac_1g_tx.v
SYN_FILES += lib/eth/rtl/eth_crc_8.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/eth_axis_rx.v
SYN_FILES += lib/eth/rtl/eth_axis_tx.v
SYN_FILES += lib/eth/rtl/udp_complete.v

2
example/ATLYS/fpga/tb/test_fpga_core.py
View File

@ -46,7 +46,7 @@ srcs.append("../lib/eth/rtl/eth_mac_1g_fifo.v")
srcs.append("../lib/eth/rtl/eth_mac_1g.v")
srcs.append("../lib/eth/rtl/eth_mac_1g_rx.v")
srcs.append("../lib/eth/rtl/eth_mac_1g_tx.v")
srcs.append("../lib/eth/rtl/eth_crc_8.v")
srcs.append("../lib/eth/rtl/lfsr.v")
srcs.append("../lib/eth/rtl/eth_axis_rx.v")
srcs.append("../lib/eth/rtl/eth_axis_tx.v")
srcs.append("../lib/eth/rtl/udp_complete.v")

9
example/DE5-Net/fpga/fpga/Makefile
View File

@ -16,14 +16,7 @@ SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
SYN_FILES += lib/eth/rtl/eth_mac_10g_rx.v
SYN_FILES += lib/eth/rtl/eth_mac_10g_tx.v
SYN_FILES += lib/eth/rtl/eth_crc_8.v
SYN_FILES += lib/eth/rtl/eth_crc_16.v
SYN_FILES += lib/eth/rtl/eth_crc_24.v
SYN_FILES += lib/eth/rtl/eth_crc_32.v
SYN_FILES += lib/eth/rtl/eth_crc_40.v
SYN_FILES += lib/eth/rtl/eth_crc_48.v
SYN_FILES += lib/eth/rtl/eth_crc_56.v
SYN_FILES += lib/eth/rtl/eth_crc_64.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/eth_axis_rx_64.v
SYN_FILES += lib/eth/rtl/eth_axis_tx_64.v
SYN_FILES += lib/eth/rtl/udp_complete_64.v

9
example/DE5-Net/fpga/tb/test_fpga_core.py
View File

@ -45,14 +45,7 @@ srcs.append("../lib/eth/rtl/eth_mac_10g_fifo.v")
srcs.append("../lib/eth/rtl/eth_mac_10g.v")
srcs.append("../lib/eth/rtl/eth_mac_10g_rx.v")
srcs.append("../lib/eth/rtl/eth_mac_10g_tx.v")
srcs.append("../lib/eth/rtl/eth_crc_8.v")
srcs.append("../lib/eth/rtl/eth_crc_16.v")
srcs.append("../lib/eth/rtl/eth_crc_24.v")
srcs.append("../lib/eth/rtl/eth_crc_32.v")
srcs.append("../lib/eth/rtl/eth_crc_40.v")
srcs.append("../lib/eth/rtl/eth_crc_48.v")
srcs.append("../lib/eth/rtl/eth_crc_56.v")
srcs.append("../lib/eth/rtl/eth_crc_64.v")
srcs.append("../lib/eth/rtl/lfsr.v")
srcs.append("../lib/eth/rtl/eth_axis_rx_64.v")
srcs.append("../lib/eth/rtl/eth_axis_tx_64.v")
srcs.append("../lib/eth/rtl/udp_complete_64.v")

9
example/HXT100G/fpga/fpga/Makefile
View File

@ -21,14 +21,7 @@ SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
SYN_FILES += lib/eth/rtl/eth_mac_10g_rx.v
SYN_FILES += lib/eth/rtl/eth_mac_10g_tx.v
SYN_FILES += lib/eth/rtl/eth_crc_8.v
SYN_FILES += lib/eth/rtl/eth_crc_16.v
SYN_FILES += lib/eth/rtl/eth_crc_24.v
SYN_FILES += lib/eth/rtl/eth_crc_32.v
SYN_FILES += lib/eth/rtl/eth_crc_40.v
SYN_FILES += lib/eth/rtl/eth_crc_48.v
SYN_FILES += lib/eth/rtl/eth_crc_56.v
SYN_FILES += lib/eth/rtl/eth_crc_64.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/eth_axis_rx_64.v
SYN_FILES += lib/eth/rtl/eth_axis_tx_64.v
SYN_FILES += lib/eth/rtl/udp_complete_64.v

9
example/HXT100G/fpga/tb/test_fpga_core.py
View File

@ -45,14 +45,7 @@ srcs.append("../lib/eth/rtl/eth_mac_10g_fifo.v")
srcs.append("../lib/eth/rtl/eth_mac_10g.v")
srcs.append("../lib/eth/rtl/eth_mac_10g_rx.v")
srcs.append("../lib/eth/rtl/eth_mac_10g_tx.v")
srcs.append("../lib/eth/rtl/eth_crc_8.v")
srcs.append("../lib/eth/rtl/eth_crc_16.v")
srcs.append("../lib/eth/rtl/eth_crc_24.v")
srcs.append("../lib/eth/rtl/eth_crc_32.v")
srcs.append("../lib/eth/rtl/eth_crc_40.v")
srcs.append("../lib/eth/rtl/eth_crc_48.v")
srcs.append("../lib/eth/rtl/eth_crc_56.v")
srcs.append("../lib/eth/rtl/eth_crc_64.v")
srcs.append("../lib/eth/rtl/lfsr.v")
srcs.append("../lib/eth/rtl/eth_axis_rx_64.v")
srcs.append("../lib/eth/rtl/eth_axis_tx_64.v")
srcs.append("../lib/eth/rtl/udp_complete_64.v")

16
rtl/axis_eth_fcs.v
View File

@ -60,11 +60,19 @@ assign input_axis_tready = 1;
assign output_fcs = fcs_reg;
assign output_fcs_valid = fcs_valid_reg;
eth_crc_8
eth_crc_8_inst (
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.REVERSE(1),
.DATA_WIDTH(8),
.OUTPUT_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_8 (
.data_in(input_axis_tdata),
.crc_state(crc_state),
.crc_next(crc_next)
.lfsr_in(crc_state),
.lfsr_out(crc_next)
);
always @(posedge clk) begin

128
rtl/axis_eth_fcs_64.v
View File

@ -68,60 +68,124 @@ assign input_axis_tready = 1'b1;
assign output_fcs = fcs_reg;
assign output_fcs_valid = fcs_valid_reg;
eth_crc_8
eth_crc_8_inst (
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.REVERSE(1),
.DATA_WIDTH(8),
.OUTPUT_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_8 (
.data_in(input_axis_tdata[7:0]),
.crc_state(crc_state),
.crc_next(crc_next0)
.lfsr_in(crc_state),
.lfsr_out(crc_next0)
);
eth_crc_16
eth_crc_16_inst (
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.REVERSE(1),
.DATA_WIDTH(16),
.OUTPUT_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_16 (
.data_in(input_axis_tdata[15:0]),
.crc_state(crc_state),
.crc_next(crc_next1)
.lfsr_in(crc_state),
.lfsr_out(crc_next1)
);
eth_crc_24
eth_crc_24_inst (
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.REVERSE(1),
.DATA_WIDTH(24),
.OUTPUT_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_24 (
.data_in(input_axis_tdata[23:0]),
.crc_state(crc_state),
.crc_next(crc_next2)
.lfsr_in(crc_state),
.lfsr_out(crc_next2)
);
eth_crc_32
eth_crc_32_inst (
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.REVERSE(1),
.DATA_WIDTH(32),
.OUTPUT_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_32 (
.data_in(input_axis_tdata[31:0]),
.crc_state(crc_state),
.crc_next(crc_next3)
.lfsr_in(crc_state),
.lfsr_out(crc_next3)
);
eth_crc_40
eth_crc_40_inst (
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.REVERSE(1),
.DATA_WIDTH(40),
.OUTPUT_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_40 (
.data_in(input_axis_tdata[39:0]),
.crc_state(crc_state),
.crc_next(crc_next4)
.lfsr_in(crc_state),
.lfsr_out(crc_next4)
);
eth_crc_48
eth_crc_48_inst (
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.REVERSE(1),
.DATA_WIDTH(48),
.OUTPUT_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_48 (
.data_in(input_axis_tdata[47:0]),
.crc_state(crc_state),
.crc_next(crc_next5)
.lfsr_in(crc_state),
.lfsr_out(crc_next5)
);
eth_crc_56
eth_crc_56_inst (
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.REVERSE(1),
.DATA_WIDTH(56),
.OUTPUT_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_56 (
.data_in(input_axis_tdata[55:0]),
.crc_state(crc_state),
.crc_next(crc_next6)
.lfsr_in(crc_state),
.lfsr_out(crc_next6)
);
eth_crc_64
eth_crc_64_inst (
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.REVERSE(1),
.DATA_WIDTH(64),
.OUTPUT_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_64 (
.data_in(input_axis_tdata[63:0]),
.crc_state(crc_state),
.crc_next(crc_next7)
.lfsr_in(crc_state),
.lfsr_out(crc_next7)
);
always @(posedge clk) begin

16
rtl/axis_eth_fcs_check.v
View File

@ -102,11 +102,19 @@ assign input_axis_tready = input_axis_tready_reg;
assign busy = busy_reg;
assign error_bad_fcs = error_bad_fcs_reg;
eth_crc_8
eth_crc_8_inst (
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.REVERSE(1),
.DATA_WIDTH(8),
.OUTPUT_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_8 (
.data_in(input_axis_tdata_d3),
.crc_state(crc_state),
.crc_next(crc_next)
.lfsr_in(crc_state),
.lfsr_out(crc_next)
);
always @* begin

80
rtl/axis_eth_fcs_check_64.v
View File

@ -117,39 +117,79 @@ assign error_bad_fcs = error_bad_fcs_reg;
wire last_cycle = state_reg == STATE_LAST;
eth_crc_8
eth_crc_8_inst (
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.REVERSE(1),
.DATA_WIDTH(8),
.OUTPUT_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_8 (
.data_in(last_cycle ? input_axis_tdata_d0[39:32] : input_axis_tdata[7:0]),
.crc_state(last_cycle ? crc_state3 : crc_state),
.crc_next(crc_next0)
.lfsr_in(last_cycle ? crc_state3 : crc_state),
.lfsr_out(crc_next0)
);
eth_crc_16
eth_crc_16_inst (
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.REVERSE(1),
.DATA_WIDTH(16),
.OUTPUT_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_16 (
.data_in(last_cycle ? input_axis_tdata_d0[47:32] : input_axis_tdata[15:0]),
.crc_state(last_cycle ? crc_state3 : crc_state),
.crc_next(crc_next1)
.lfsr_in(last_cycle ? crc_state3 : crc_state),
.lfsr_out(crc_next1)
);
eth_crc_24
eth_crc_24_inst (
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.REVERSE(1),
.DATA_WIDTH(24),
.OUTPUT_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_24 (
.data_in(last_cycle ? input_axis_tdata_d0[55:32] : input_axis_tdata[23:0]),
.crc_state(last_cycle ? crc_state3 : crc_state),
.crc_next(crc_next2)
.lfsr_in(last_cycle ? crc_state3 : crc_state),
.lfsr_out(crc_next2)
);
eth_crc_32
eth_crc_32_inst (
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.REVERSE(1),
.DATA_WIDTH(32),
.OUTPUT_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_32 (
.data_in(last_cycle ? input_axis_tdata_d0[63:32] : input_axis_tdata[31:0]),
.crc_state(last_cycle ? crc_state3 : crc_state),
.crc_next(crc_next3)
.lfsr_in(last_cycle ? crc_state3 : crc_state),
.lfsr_out(crc_next3)
);
eth_crc_64
eth_crc_64_inst (
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.REVERSE(1),
.DATA_WIDTH(64),
.OUTPUT_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_64 (
.data_in(input_axis_tdata[63:0]),
.crc_state(crc_state),
.crc_next(crc_next7)
.lfsr_in(crc_state),
.lfsr_out(crc_next7)
);
always @* begin

16
rtl/axis_eth_fcs_insert.v
View File

@ -95,11 +95,19 @@ assign input_axis_tready = input_axis_tready_reg;
assign busy = busy_reg;
eth_crc_8
eth_crc_8_inst (
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.REVERSE(1),
.DATA_WIDTH(8),
.OUTPUT_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_8 (
.data_in(output_axis_tdata_int),
.crc_state(crc_state),
.crc_next(crc_next)
.lfsr_in(crc_state),
.lfsr_out(crc_next)
);
always @* begin

128
rtl/axis_eth_fcs_insert_64.v
View File

@ -119,60 +119,124 @@ assign input_axis_tready = input_axis_tready_reg;
assign busy = busy_reg;
eth_crc_8
eth_crc_8_inst (
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.REVERSE(1),
.DATA_WIDTH(8),
.OUTPUT_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_8 (
.data_in(fcs_input_tdata[7:0]),
.crc_state(crc_state),
.crc_next(crc_next0)
.lfsr_in(crc_state),
.lfsr_out(crc_next0)
);
eth_crc_16
eth_crc_16_inst (
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.REVERSE(1),
.DATA_WIDTH(16),
.OUTPUT_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_16 (
.data_in(fcs_input_tdata[15:0]),
.crc_state(crc_state),
.crc_next(crc_next1)
.lfsr_in(crc_state),
.lfsr_out(crc_next1)
);
eth_crc_24
eth_crc_24_inst (
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.REVERSE(1),
.DATA_WIDTH(24),
.OUTPUT_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_24 (
.data_in(fcs_input_tdata[23:0]),
.crc_state(crc_state),
.crc_next(crc_next2)
.lfsr_in(crc_state),
.lfsr_out(crc_next2)
);
eth_crc_32
eth_crc_32_inst (
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.REVERSE(1),
.DATA_WIDTH(32),
.OUTPUT_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_32 (
.data_in(fcs_input_tdata[31:0]),
.crc_state(crc_state),
.crc_next(crc_next3)
.lfsr_in(crc_state),
.lfsr_out(crc_next3)
);
eth_crc_40
eth_crc_40_inst (
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.REVERSE(1),
.DATA_WIDTH(40),
.OUTPUT_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_40 (
.data_in(fcs_input_tdata[39:0]),
.crc_state(crc_state),
.crc_next(crc_next4)
.lfsr_in(crc_state),
.lfsr_out(crc_next4)
);
eth_crc_48
eth_crc_48_inst (
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.REVERSE(1),
.DATA_WIDTH(48),
.OUTPUT_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_48 (
.data_in(fcs_input_tdata[47:0]),
.crc_state(crc_state),
.crc_next(crc_next5)
.lfsr_in(crc_state),
.lfsr_out(crc_next5)
);
eth_crc_56
eth_crc_56_inst (
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.REVERSE(1),
.DATA_WIDTH(56),
.OUTPUT_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_56 (
.data_in(fcs_input_tdata[55:0]),
.crc_state(crc_state),
.crc_next(crc_next6)
.lfsr_in(crc_state),
.lfsr_out(crc_next6)
);
eth_crc_64
eth_crc_64_inst (
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.REVERSE(1),
.DATA_WIDTH(64),
.OUTPUT_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_64 (
.data_in(fcs_input_tdata[63:0]),
.crc_state(crc_state),
.crc_next(crc_next7)
.lfsr_in(crc_state),
.lfsr_out(crc_next7)
);
function [3:0] keep2count;

80
rtl/eth_mac_10g_rx.v
View File

@ -116,39 +116,79 @@ assign error_bad_fcs = error_bad_fcs_reg;
wire last_cycle = state_reg == STATE_LAST;
eth_crc_8
eth_crc_8_inst (
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.REVERSE(1),
.DATA_WIDTH(8),
.OUTPUT_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_8 (
.data_in(last_cycle ? xgmii_rxd_d1[39:32] : xgmii_rxd_d0[7:0]),
.crc_state(last_cycle ? crc_state3 : crc_state),
.crc_next(crc_next0)
.lfsr_in(last_cycle ? crc_state3 : crc_state),
.lfsr_out(crc_next0)
);
eth_crc_16
eth_crc_16_inst (
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.REVERSE(1),
.DATA_WIDTH(16),
.OUTPUT_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_16 (
.data_in(last_cycle ? xgmii_rxd_d1[47:32] : xgmii_rxd_d0[15:0]),
.crc_state(last_cycle ? crc_state3 : crc_state),
.crc_next(crc_next1)
.lfsr_in(last_cycle ? crc_state3 : crc_state),
.lfsr_out(crc_next1)
);
eth_crc_24
eth_crc_24_inst (
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.REVERSE(1),
.DATA_WIDTH(24),
.OUTPUT_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_24 (
.data_in(last_cycle ? xgmii_rxd_d1[55:32] : xgmii_rxd_d0[23:0]),
.crc_state(last_cycle ? crc_state3 : crc_state),
.crc_next(crc_next2)
.lfsr_in(last_cycle ? crc_state3 : crc_state),
.lfsr_out(crc_next2)
);
eth_crc_32
eth_crc_32_inst (
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.REVERSE(1),
.DATA_WIDTH(32),
.OUTPUT_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_32 (
.data_in(last_cycle ? xgmii_rxd_d1[63:32] : xgmii_rxd_d0[31:0]),
.crc_state(last_cycle ? crc_state3 : crc_state),
.crc_next(crc_next3)
.lfsr_in(last_cycle ? crc_state3 : crc_state),
.lfsr_out(crc_next3)
);
eth_crc_64
eth_crc_64_inst (
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.REVERSE(1),
.DATA_WIDTH(64),
.OUTPUT_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_64 (
.data_in(xgmii_rxd_d0[63:0]),
.crc_state(crc_state),
.crc_next(crc_next7)
.lfsr_in(crc_state),
.lfsr_out(crc_next7)
);
// detect control characters

128
rtl/eth_mac_10g_tx.v
View File

@ -125,60 +125,124 @@ assign input_axis_tready = input_axis_tready_reg;
assign xgmii_txd = xgmii_txd_reg;
assign xgmii_txc = xgmii_txc_reg;
eth_crc_8
eth_crc_8_inst (
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.REVERSE(1),
.DATA_WIDTH(8),
.OUTPUT_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_8 (
.data_in(input_tdata_reg[7:0]),
.crc_state(crc_state),
.crc_next(crc_next0)
.lfsr_in(crc_state),
.lfsr_out(crc_next0)
);
eth_crc_16
eth_crc_16_inst (
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.REVERSE(1),
.DATA_WIDTH(16),
.OUTPUT_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_16 (
.data_in(input_tdata_reg[15:0]),
.crc_state(crc_state),
.crc_next(crc_next1)
.lfsr_in(crc_state),
.lfsr_out(crc_next1)
);
eth_crc_24
eth_crc_24_inst (
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.REVERSE(1),
.DATA_WIDTH(24),
.OUTPUT_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_24 (
.data_in(input_tdata_reg[23:0]),
.crc_state(crc_state),
.crc_next(crc_next2)
.lfsr_in(crc_state),
.lfsr_out(crc_next2)
);
eth_crc_32
eth_crc_32_inst (
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.REVERSE(1),
.DATA_WIDTH(32),
.OUTPUT_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_32 (
.data_in(input_tdata_reg[31:0]),
.crc_state(crc_state),
.crc_next(crc_next3)
.lfsr_in(crc_state),
.lfsr_out(crc_next3)
);
eth_crc_40
eth_crc_40_inst (
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.REVERSE(1),
.DATA_WIDTH(40),
.OUTPUT_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_40 (
.data_in(input_tdata_reg[39:0]),
.crc_state(crc_state),
.crc_next(crc_next4)
.lfsr_in(crc_state),
.lfsr_out(crc_next4)
);
eth_crc_48
eth_crc_48_inst (
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.REVERSE(1),
.DATA_WIDTH(48),
.OUTPUT_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_48 (
.data_in(input_tdata_reg[47:0]),
.crc_state(crc_state),
.crc_next(crc_next5)
.lfsr_in(crc_state),
.lfsr_out(crc_next5)
);
eth_crc_56
eth_crc_56_inst (
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.REVERSE(1),
.DATA_WIDTH(56),
.OUTPUT_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_56 (
.data_in(input_tdata_reg[55:0]),
.crc_state(crc_state),
.crc_next(crc_next6)
.lfsr_in(crc_state),
.lfsr_out(crc_next6)
);
eth_crc_64
eth_crc_64_inst (
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.REVERSE(1),
.DATA_WIDTH(64),
.OUTPUT_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_64 (
.data_in(input_tdata_reg[63:0]),
.crc_state(crc_state),
.crc_next(crc_next7)
.lfsr_in(crc_state),
.lfsr_out(crc_next7)
);
function [3:0] keep2count;

16
rtl/eth_mac_1g_rx.v
View File

@ -104,11 +104,19 @@ assign output_axis_tuser = output_axis_tuser_reg;
assign error_bad_frame = error_bad_frame_reg;
assign error_bad_fcs = error_bad_fcs_reg;
eth_crc_8
eth_crc_8_inst (
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.REVERSE(1),
.DATA_WIDTH(8),
.OUTPUT_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_8 (
.data_in(gmii_rxd_d4),
.crc_state(crc_state),
.crc_next(crc_next)
.lfsr_in(crc_state),
.lfsr_out(crc_next)
);
always @* begin

16
rtl/eth_mac_1g_tx.v
View File

@ -92,11 +92,19 @@ assign gmii_txd = gmii_txd_reg;
assign gmii_tx_en = gmii_tx_en_reg;
assign gmii_tx_er = gmii_tx_er_reg;
eth_crc_8
eth_crc_8_inst (
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.REVERSE(1),
.DATA_WIDTH(8),
.OUTPUT_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_8 (
.data_in(gmii_txd_next),
.crc_state(crc_state),
.crc_next(crc_next)
.lfsr_in(crc_state),
.lfsr_out(crc_next)
);
always @* begin

2
tb/test_axis_eth_fcs.py
View File

@ -39,7 +39,7 @@ module = 'axis_eth_fcs'
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/eth_crc_8.v")
srcs.append("../rtl/lfsr.v")
srcs.append("test_%s.v" % module)
src = ' '.join(srcs)

9
tb/test_axis_eth_fcs_64.py
View File

@ -39,14 +39,7 @@ module = 'axis_eth_fcs_64'
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/eth_crc_8.v")
srcs.append("../rtl/eth_crc_16.v")
srcs.append("../rtl/eth_crc_24.v")
srcs.append("../rtl/eth_crc_32.v")
srcs.append("../rtl/eth_crc_40.v")
srcs.append("../rtl/eth_crc_48.v")
srcs.append("../rtl/eth_crc_56.v")
srcs.append("../rtl/eth_crc_64.v")
srcs.append("../rtl/lfsr.v")
srcs.append("test_%s.v" % module)
src = ' '.join(srcs)

2
tb/test_axis_eth_fcs_check.py
View File

@ -41,7 +41,7 @@ module = 'axis_eth_fcs_check'
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/eth_crc_8.v")
srcs.append("../rtl/lfsr.v")
srcs.append("test_%s.v" % module)
src = ' '.join(srcs)

9
tb/test_axis_eth_fcs_check_64.py
View File

@ -41,14 +41,7 @@ module = 'axis_eth_fcs_check_64'
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/eth_crc_8.v")
srcs.append("../rtl/eth_crc_16.v")
srcs.append("../rtl/eth_crc_24.v")
srcs.append("../rtl/eth_crc_32.v")
srcs.append("../rtl/eth_crc_40.v")
srcs.append("../rtl/eth_crc_48.v")
srcs.append("../rtl/eth_crc_56.v")
srcs.append("../rtl/eth_crc_64.v")
srcs.append("../rtl/lfsr.v")
srcs.append("test_%s.v" % module)
src = ' '.join(srcs)

2
tb/test_axis_eth_fcs_insert.py
View File

@ -41,7 +41,7 @@ module = 'axis_eth_fcs_insert'
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/eth_crc_8.v")
srcs.append("../rtl/lfsr.v")
srcs.append("test_%s.v" % module)
src = ' '.join(srcs)

9
tb/test_axis_eth_fcs_insert_64.py
View File

@ -41,14 +41,7 @@ module = 'axis_eth_fcs_insert_64'
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/eth_crc_8.v")
srcs.append("../rtl/eth_crc_16.v")
srcs.append("../rtl/eth_crc_24.v")
srcs.append("../rtl/eth_crc_32.v")
srcs.append("../rtl/eth_crc_40.v")
srcs.append("../rtl/eth_crc_48.v")
srcs.append("../rtl/eth_crc_56.v")
srcs.append("../rtl/eth_crc_64.v")
srcs.append("../rtl/lfsr.v")
srcs.append("test_%s.v" % module)
src = ' '.join(srcs)

9
tb/test_axis_eth_fcs_insert_64_pad.py
View File

@ -41,14 +41,7 @@ module = 'axis_eth_fcs_insert_64'
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/eth_crc_8.v")
srcs.append("../rtl/eth_crc_16.v")
srcs.append("../rtl/eth_crc_24.v")
srcs.append("../rtl/eth_crc_32.v")
srcs.append("../rtl/eth_crc_40.v")
srcs.append("../rtl/eth_crc_48.v")
srcs.append("../rtl/eth_crc_56.v")
srcs.append("../rtl/eth_crc_64.v")
srcs.append("../rtl/lfsr.v")
srcs.append("test_%s_pad.v" % module)
src = ' '.join(srcs)

2
tb/test_axis_eth_fcs_insert_pad.py
View File

@ -41,7 +41,7 @@ module = 'axis_eth_fcs_insert'
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/eth_crc_8.v")
srcs.append("../rtl/lfsr.v")
srcs.append("test_%s_pad.v" % module)
src = ' '.join(srcs)

9
tb/test_eth_mac_10g.py
View File

@ -40,14 +40,7 @@ module = 'eth_mac_10g'
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/eth_crc_8.v")
srcs.append("../rtl/eth_crc_16.v")
srcs.append("../rtl/eth_crc_24.v")
srcs.append("../rtl/eth_crc_32.v")
srcs.append("../rtl/eth_crc_40.v")
srcs.append("../rtl/eth_crc_48.v")
srcs.append("../rtl/eth_crc_56.v")
srcs.append("../rtl/eth_crc_64.v")
srcs.append("../rtl/lfsr.v")
srcs.append("../rtl/eth_mac_10g_rx.v")
srcs.append("../rtl/eth_mac_10g_tx.v")
srcs.append("test_%s.v" % module)

9
tb/test_eth_mac_10g_fifo.py
View File

@ -40,14 +40,7 @@ module = 'eth_mac_10g_fifo'
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/eth_crc_8.v")
srcs.append("../rtl/eth_crc_16.v")
srcs.append("../rtl/eth_crc_24.v")
srcs.append("../rtl/eth_crc_32.v")
srcs.append("../rtl/eth_crc_40.v")
srcs.append("../rtl/eth_crc_48.v")
srcs.append("../rtl/eth_crc_56.v")
srcs.append("../rtl/eth_crc_64.v")
srcs.append("../rtl/lfsr.v")
srcs.append("../rtl/eth_mac_10g_rx.v")
srcs.append("../rtl/eth_mac_10g_tx.v")
srcs.append("../rtl/eth_mac_10g.v")

9
tb/test_eth_mac_10g_rx.py
View File

@ -42,14 +42,7 @@ module = 'eth_mac_10g_rx'
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/eth_crc_8.v")
srcs.append("../rtl/eth_crc_16.v")
srcs.append("../rtl/eth_crc_24.v")
srcs.append("../rtl/eth_crc_32.v")
srcs.append("../rtl/eth_crc_40.v")
srcs.append("../rtl/eth_crc_48.v")
srcs.append("../rtl/eth_crc_56.v")
srcs.append("../rtl/eth_crc_64.v")
srcs.append("../rtl/lfsr.v")
srcs.append("test_%s.v" % module)
src = ' '.join(srcs)

9
tb/test_eth_mac_10g_tx.py
View File

@ -40,14 +40,7 @@ module = 'eth_mac_10g_tx'
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/eth_crc_8.v")
srcs.append("../rtl/eth_crc_16.v")
srcs.append("../rtl/eth_crc_24.v")
srcs.append("../rtl/eth_crc_32.v")
srcs.append("../rtl/eth_crc_40.v")
srcs.append("../rtl/eth_crc_48.v")
srcs.append("../rtl/eth_crc_56.v")
srcs.append("../rtl/eth_crc_64.v")
srcs.append("../rtl/lfsr.v")
srcs.append("test_%s.v" % module)
src = ' '.join(srcs)

2
tb/test_eth_mac_1g.py
View File

@ -40,7 +40,7 @@ module = 'eth_mac_1g'
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/eth_crc_8.v")
srcs.append("../rtl/lfsr.v")
srcs.append("../rtl/eth_mac_1g_rx.v")
srcs.append("../rtl/eth_mac_1g_tx.v")
srcs.append("test_%s.v" % module)

2
tb/test_eth_mac_1g_fifo.py
View File

@ -40,7 +40,7 @@ module = 'eth_mac_1g_fifo'
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/eth_crc_8.v")
srcs.append("../rtl/lfsr.v")
srcs.append("../rtl/eth_mac_1g_rx.v")
srcs.append("../rtl/eth_mac_1g_tx.v")
srcs.append("../rtl/eth_mac_1g.v")

2
tb/test_eth_mac_1g_rx.py
View File

@ -40,7 +40,7 @@ module = 'eth_mac_1g_rx'
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/eth_crc_8.v")
srcs.append("../rtl/lfsr.v")
srcs.append("test_%s.v" % module)
src = ' '.join(srcs)

2
tb/test_eth_mac_1g_tx.py
View File

@ -40,7 +40,7 @@ module = 'eth_mac_1g_tx'
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/eth_crc_8.v")
srcs.append("../rtl/lfsr.v")
srcs.append("test_%s.v" % module)
src = ' '.join(srcs)