diff --git a/example/ATLYS/fpga/fpga/Makefile b/example/ATLYS/fpga/fpga/Makefile index 648dbf88..9745f688 100644 --- a/example/ATLYS/fpga/fpga/Makefile +++ b/example/ATLYS/fpga/fpga/Makefile @@ -19,7 +19,7 @@ SYN_FILES += lib/eth/rtl/eth_mac_1g_fifo.v SYN_FILES += lib/eth/rtl/eth_mac_1g.v SYN_FILES += lib/eth/rtl/eth_mac_1g_rx.v SYN_FILES += lib/eth/rtl/eth_mac_1g_tx.v -SYN_FILES += lib/eth/rtl/eth_crc_8.v +SYN_FILES += lib/eth/rtl/lfsr.v SYN_FILES += lib/eth/rtl/eth_axis_rx.v SYN_FILES += lib/eth/rtl/eth_axis_tx.v SYN_FILES += lib/eth/rtl/udp_complete.v diff --git a/example/ATLYS/fpga/tb/test_fpga_core.py b/example/ATLYS/fpga/tb/test_fpga_core.py index 2a847ed8..0f03d4a8 100755 --- a/example/ATLYS/fpga/tb/test_fpga_core.py +++ b/example/ATLYS/fpga/tb/test_fpga_core.py @@ -46,7 +46,7 @@ srcs.append("../lib/eth/rtl/eth_mac_1g_fifo.v") srcs.append("../lib/eth/rtl/eth_mac_1g.v") srcs.append("../lib/eth/rtl/eth_mac_1g_rx.v") srcs.append("../lib/eth/rtl/eth_mac_1g_tx.v") -srcs.append("../lib/eth/rtl/eth_crc_8.v") +srcs.append("../lib/eth/rtl/lfsr.v") srcs.append("../lib/eth/rtl/eth_axis_rx.v") srcs.append("../lib/eth/rtl/eth_axis_tx.v") srcs.append("../lib/eth/rtl/udp_complete.v") diff --git a/example/DE5-Net/fpga/fpga/Makefile b/example/DE5-Net/fpga/fpga/Makefile index b4725044..713bd0de 100644 --- a/example/DE5-Net/fpga/fpga/Makefile +++ b/example/DE5-Net/fpga/fpga/Makefile @@ -16,14 +16,7 @@ SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v SYN_FILES += lib/eth/rtl/eth_mac_10g.v SYN_FILES += lib/eth/rtl/eth_mac_10g_rx.v SYN_FILES += lib/eth/rtl/eth_mac_10g_tx.v -SYN_FILES += lib/eth/rtl/eth_crc_8.v -SYN_FILES += lib/eth/rtl/eth_crc_16.v -SYN_FILES += lib/eth/rtl/eth_crc_24.v -SYN_FILES += lib/eth/rtl/eth_crc_32.v -SYN_FILES += lib/eth/rtl/eth_crc_40.v -SYN_FILES += lib/eth/rtl/eth_crc_48.v -SYN_FILES += lib/eth/rtl/eth_crc_56.v -SYN_FILES += lib/eth/rtl/eth_crc_64.v +SYN_FILES += lib/eth/rtl/lfsr.v SYN_FILES += lib/eth/rtl/eth_axis_rx_64.v SYN_FILES += lib/eth/rtl/eth_axis_tx_64.v SYN_FILES += lib/eth/rtl/udp_complete_64.v diff --git a/example/DE5-Net/fpga/tb/test_fpga_core.py b/example/DE5-Net/fpga/tb/test_fpga_core.py index e6cf9842..2d95e580 100755 --- a/example/DE5-Net/fpga/tb/test_fpga_core.py +++ b/example/DE5-Net/fpga/tb/test_fpga_core.py @@ -45,14 +45,7 @@ srcs.append("../lib/eth/rtl/eth_mac_10g_fifo.v") srcs.append("../lib/eth/rtl/eth_mac_10g.v") srcs.append("../lib/eth/rtl/eth_mac_10g_rx.v") srcs.append("../lib/eth/rtl/eth_mac_10g_tx.v") -srcs.append("../lib/eth/rtl/eth_crc_8.v") -srcs.append("../lib/eth/rtl/eth_crc_16.v") -srcs.append("../lib/eth/rtl/eth_crc_24.v") -srcs.append("../lib/eth/rtl/eth_crc_32.v") -srcs.append("../lib/eth/rtl/eth_crc_40.v") -srcs.append("../lib/eth/rtl/eth_crc_48.v") -srcs.append("../lib/eth/rtl/eth_crc_56.v") -srcs.append("../lib/eth/rtl/eth_crc_64.v") +srcs.append("../lib/eth/rtl/lfsr.v") srcs.append("../lib/eth/rtl/eth_axis_rx_64.v") srcs.append("../lib/eth/rtl/eth_axis_tx_64.v") srcs.append("../lib/eth/rtl/udp_complete_64.v") diff --git a/example/HXT100G/fpga/fpga/Makefile b/example/HXT100G/fpga/fpga/Makefile index 838b74de..1f2d7375 100644 --- a/example/HXT100G/fpga/fpga/Makefile +++ b/example/HXT100G/fpga/fpga/Makefile @@ -21,14 +21,7 @@ SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v SYN_FILES += lib/eth/rtl/eth_mac_10g.v SYN_FILES += lib/eth/rtl/eth_mac_10g_rx.v SYN_FILES += lib/eth/rtl/eth_mac_10g_tx.v -SYN_FILES += lib/eth/rtl/eth_crc_8.v -SYN_FILES += lib/eth/rtl/eth_crc_16.v -SYN_FILES += lib/eth/rtl/eth_crc_24.v -SYN_FILES += lib/eth/rtl/eth_crc_32.v -SYN_FILES += lib/eth/rtl/eth_crc_40.v -SYN_FILES += lib/eth/rtl/eth_crc_48.v -SYN_FILES += lib/eth/rtl/eth_crc_56.v -SYN_FILES += lib/eth/rtl/eth_crc_64.v +SYN_FILES += lib/eth/rtl/lfsr.v SYN_FILES += lib/eth/rtl/eth_axis_rx_64.v SYN_FILES += lib/eth/rtl/eth_axis_tx_64.v SYN_FILES += lib/eth/rtl/udp_complete_64.v diff --git a/example/HXT100G/fpga/tb/test_fpga_core.py b/example/HXT100G/fpga/tb/test_fpga_core.py index ffad6660..d70b1ff3 100755 --- a/example/HXT100G/fpga/tb/test_fpga_core.py +++ b/example/HXT100G/fpga/tb/test_fpga_core.py @@ -45,14 +45,7 @@ srcs.append("../lib/eth/rtl/eth_mac_10g_fifo.v") srcs.append("../lib/eth/rtl/eth_mac_10g.v") srcs.append("../lib/eth/rtl/eth_mac_10g_rx.v") srcs.append("../lib/eth/rtl/eth_mac_10g_tx.v") -srcs.append("../lib/eth/rtl/eth_crc_8.v") -srcs.append("../lib/eth/rtl/eth_crc_16.v") -srcs.append("../lib/eth/rtl/eth_crc_24.v") -srcs.append("../lib/eth/rtl/eth_crc_32.v") -srcs.append("../lib/eth/rtl/eth_crc_40.v") -srcs.append("../lib/eth/rtl/eth_crc_48.v") -srcs.append("../lib/eth/rtl/eth_crc_56.v") -srcs.append("../lib/eth/rtl/eth_crc_64.v") +srcs.append("../lib/eth/rtl/lfsr.v") srcs.append("../lib/eth/rtl/eth_axis_rx_64.v") srcs.append("../lib/eth/rtl/eth_axis_tx_64.v") srcs.append("../lib/eth/rtl/udp_complete_64.v") diff --git a/rtl/axis_eth_fcs.v b/rtl/axis_eth_fcs.v index eed18b78..724d095c 100644 --- a/rtl/axis_eth_fcs.v +++ b/rtl/axis_eth_fcs.v @@ -60,11 +60,19 @@ assign input_axis_tready = 1; assign output_fcs = fcs_reg; assign output_fcs_valid = fcs_valid_reg; -eth_crc_8 -eth_crc_8_inst ( +lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .REVERSE(1), + .DATA_WIDTH(8), + .OUTPUT_WIDTH(32), + .STYLE("AUTO") +) +eth_crc_8 ( .data_in(input_axis_tdata), - .crc_state(crc_state), - .crc_next(crc_next) + .lfsr_in(crc_state), + .lfsr_out(crc_next) ); always @(posedge clk) begin diff --git a/rtl/axis_eth_fcs_64.v b/rtl/axis_eth_fcs_64.v index 71100681..b4390ffb 100644 --- a/rtl/axis_eth_fcs_64.v +++ b/rtl/axis_eth_fcs_64.v @@ -68,60 +68,124 @@ assign input_axis_tready = 1'b1; assign output_fcs = fcs_reg; assign output_fcs_valid = fcs_valid_reg; -eth_crc_8 -eth_crc_8_inst ( +lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .REVERSE(1), + .DATA_WIDTH(8), + .OUTPUT_WIDTH(32), + .STYLE("AUTO") +) +eth_crc_8 ( .data_in(input_axis_tdata[7:0]), - .crc_state(crc_state), - .crc_next(crc_next0) + .lfsr_in(crc_state), + .lfsr_out(crc_next0) ); -eth_crc_16 -eth_crc_16_inst ( +lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .REVERSE(1), + .DATA_WIDTH(16), + .OUTPUT_WIDTH(32), + .STYLE("AUTO") +) +eth_crc_16 ( .data_in(input_axis_tdata[15:0]), - .crc_state(crc_state), - .crc_next(crc_next1) + .lfsr_in(crc_state), + .lfsr_out(crc_next1) ); -eth_crc_24 -eth_crc_24_inst ( +lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .REVERSE(1), + .DATA_WIDTH(24), + .OUTPUT_WIDTH(32), + .STYLE("AUTO") +) +eth_crc_24 ( .data_in(input_axis_tdata[23:0]), - .crc_state(crc_state), - .crc_next(crc_next2) + .lfsr_in(crc_state), + .lfsr_out(crc_next2) ); -eth_crc_32 -eth_crc_32_inst ( +lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .REVERSE(1), + .DATA_WIDTH(32), + .OUTPUT_WIDTH(32), + .STYLE("AUTO") +) +eth_crc_32 ( .data_in(input_axis_tdata[31:0]), - .crc_state(crc_state), - .crc_next(crc_next3) + .lfsr_in(crc_state), + .lfsr_out(crc_next3) ); -eth_crc_40 -eth_crc_40_inst ( +lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .REVERSE(1), + .DATA_WIDTH(40), + .OUTPUT_WIDTH(32), + .STYLE("AUTO") +) +eth_crc_40 ( .data_in(input_axis_tdata[39:0]), - .crc_state(crc_state), - .crc_next(crc_next4) + .lfsr_in(crc_state), + .lfsr_out(crc_next4) ); -eth_crc_48 -eth_crc_48_inst ( +lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .REVERSE(1), + .DATA_WIDTH(48), + .OUTPUT_WIDTH(32), + .STYLE("AUTO") +) +eth_crc_48 ( .data_in(input_axis_tdata[47:0]), - .crc_state(crc_state), - .crc_next(crc_next5) + .lfsr_in(crc_state), + .lfsr_out(crc_next5) ); -eth_crc_56 -eth_crc_56_inst ( +lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .REVERSE(1), + .DATA_WIDTH(56), + .OUTPUT_WIDTH(32), + .STYLE("AUTO") +) +eth_crc_56 ( .data_in(input_axis_tdata[55:0]), - .crc_state(crc_state), - .crc_next(crc_next6) + .lfsr_in(crc_state), + .lfsr_out(crc_next6) ); -eth_crc_64 -eth_crc_64_inst ( +lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .REVERSE(1), + .DATA_WIDTH(64), + .OUTPUT_WIDTH(32), + .STYLE("AUTO") +) +eth_crc_64 ( .data_in(input_axis_tdata[63:0]), - .crc_state(crc_state), - .crc_next(crc_next7) + .lfsr_in(crc_state), + .lfsr_out(crc_next7) ); always @(posedge clk) begin diff --git a/rtl/axis_eth_fcs_check.v b/rtl/axis_eth_fcs_check.v index bbe78838..23412dc2 100644 --- a/rtl/axis_eth_fcs_check.v +++ b/rtl/axis_eth_fcs_check.v @@ -102,11 +102,19 @@ assign input_axis_tready = input_axis_tready_reg; assign busy = busy_reg; assign error_bad_fcs = error_bad_fcs_reg; -eth_crc_8 -eth_crc_8_inst ( +lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .REVERSE(1), + .DATA_WIDTH(8), + .OUTPUT_WIDTH(32), + .STYLE("AUTO") +) +eth_crc_8 ( .data_in(input_axis_tdata_d3), - .crc_state(crc_state), - .crc_next(crc_next) + .lfsr_in(crc_state), + .lfsr_out(crc_next) ); always @* begin diff --git a/rtl/axis_eth_fcs_check_64.v b/rtl/axis_eth_fcs_check_64.v index bdcb01d0..9a104eb0 100644 --- a/rtl/axis_eth_fcs_check_64.v +++ b/rtl/axis_eth_fcs_check_64.v @@ -117,39 +117,79 @@ assign error_bad_fcs = error_bad_fcs_reg; wire last_cycle = state_reg == STATE_LAST; -eth_crc_8 -eth_crc_8_inst ( +lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .REVERSE(1), + .DATA_WIDTH(8), + .OUTPUT_WIDTH(32), + .STYLE("AUTO") +) +eth_crc_8 ( .data_in(last_cycle ? input_axis_tdata_d0[39:32] : input_axis_tdata[7:0]), - .crc_state(last_cycle ? crc_state3 : crc_state), - .crc_next(crc_next0) + .lfsr_in(last_cycle ? crc_state3 : crc_state), + .lfsr_out(crc_next0) ); -eth_crc_16 -eth_crc_16_inst ( +lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .REVERSE(1), + .DATA_WIDTH(16), + .OUTPUT_WIDTH(32), + .STYLE("AUTO") +) +eth_crc_16 ( .data_in(last_cycle ? input_axis_tdata_d0[47:32] : input_axis_tdata[15:0]), - .crc_state(last_cycle ? crc_state3 : crc_state), - .crc_next(crc_next1) + .lfsr_in(last_cycle ? crc_state3 : crc_state), + .lfsr_out(crc_next1) ); -eth_crc_24 -eth_crc_24_inst ( +lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .REVERSE(1), + .DATA_WIDTH(24), + .OUTPUT_WIDTH(32), + .STYLE("AUTO") +) +eth_crc_24 ( .data_in(last_cycle ? input_axis_tdata_d0[55:32] : input_axis_tdata[23:0]), - .crc_state(last_cycle ? crc_state3 : crc_state), - .crc_next(crc_next2) + .lfsr_in(last_cycle ? crc_state3 : crc_state), + .lfsr_out(crc_next2) ); -eth_crc_32 -eth_crc_32_inst ( +lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .REVERSE(1), + .DATA_WIDTH(32), + .OUTPUT_WIDTH(32), + .STYLE("AUTO") +) +eth_crc_32 ( .data_in(last_cycle ? input_axis_tdata_d0[63:32] : input_axis_tdata[31:0]), - .crc_state(last_cycle ? crc_state3 : crc_state), - .crc_next(crc_next3) + .lfsr_in(last_cycle ? crc_state3 : crc_state), + .lfsr_out(crc_next3) ); -eth_crc_64 -eth_crc_64_inst ( +lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .REVERSE(1), + .DATA_WIDTH(64), + .OUTPUT_WIDTH(32), + .STYLE("AUTO") +) +eth_crc_64 ( .data_in(input_axis_tdata[63:0]), - .crc_state(crc_state), - .crc_next(crc_next7) + .lfsr_in(crc_state), + .lfsr_out(crc_next7) ); always @* begin diff --git a/rtl/axis_eth_fcs_insert.v b/rtl/axis_eth_fcs_insert.v index e6e381c3..1d7b8174 100644 --- a/rtl/axis_eth_fcs_insert.v +++ b/rtl/axis_eth_fcs_insert.v @@ -95,11 +95,19 @@ assign input_axis_tready = input_axis_tready_reg; assign busy = busy_reg; -eth_crc_8 -eth_crc_8_inst ( +lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .REVERSE(1), + .DATA_WIDTH(8), + .OUTPUT_WIDTH(32), + .STYLE("AUTO") +) +eth_crc_8 ( .data_in(output_axis_tdata_int), - .crc_state(crc_state), - .crc_next(crc_next) + .lfsr_in(crc_state), + .lfsr_out(crc_next) ); always @* begin diff --git a/rtl/axis_eth_fcs_insert_64.v b/rtl/axis_eth_fcs_insert_64.v index 034ad3c0..107f82d1 100644 --- a/rtl/axis_eth_fcs_insert_64.v +++ b/rtl/axis_eth_fcs_insert_64.v @@ -119,60 +119,124 @@ assign input_axis_tready = input_axis_tready_reg; assign busy = busy_reg; -eth_crc_8 -eth_crc_8_inst ( +lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .REVERSE(1), + .DATA_WIDTH(8), + .OUTPUT_WIDTH(32), + .STYLE("AUTO") +) +eth_crc_8 ( .data_in(fcs_input_tdata[7:0]), - .crc_state(crc_state), - .crc_next(crc_next0) + .lfsr_in(crc_state), + .lfsr_out(crc_next0) ); -eth_crc_16 -eth_crc_16_inst ( +lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .REVERSE(1), + .DATA_WIDTH(16), + .OUTPUT_WIDTH(32), + .STYLE("AUTO") +) +eth_crc_16 ( .data_in(fcs_input_tdata[15:0]), - .crc_state(crc_state), - .crc_next(crc_next1) + .lfsr_in(crc_state), + .lfsr_out(crc_next1) ); -eth_crc_24 -eth_crc_24_inst ( +lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .REVERSE(1), + .DATA_WIDTH(24), + .OUTPUT_WIDTH(32), + .STYLE("AUTO") +) +eth_crc_24 ( .data_in(fcs_input_tdata[23:0]), - .crc_state(crc_state), - .crc_next(crc_next2) + .lfsr_in(crc_state), + .lfsr_out(crc_next2) ); -eth_crc_32 -eth_crc_32_inst ( +lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .REVERSE(1), + .DATA_WIDTH(32), + .OUTPUT_WIDTH(32), + .STYLE("AUTO") +) +eth_crc_32 ( .data_in(fcs_input_tdata[31:0]), - .crc_state(crc_state), - .crc_next(crc_next3) + .lfsr_in(crc_state), + .lfsr_out(crc_next3) ); -eth_crc_40 -eth_crc_40_inst ( +lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .REVERSE(1), + .DATA_WIDTH(40), + .OUTPUT_WIDTH(32), + .STYLE("AUTO") +) +eth_crc_40 ( .data_in(fcs_input_tdata[39:0]), - .crc_state(crc_state), - .crc_next(crc_next4) + .lfsr_in(crc_state), + .lfsr_out(crc_next4) ); -eth_crc_48 -eth_crc_48_inst ( +lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .REVERSE(1), + .DATA_WIDTH(48), + .OUTPUT_WIDTH(32), + .STYLE("AUTO") +) +eth_crc_48 ( .data_in(fcs_input_tdata[47:0]), - .crc_state(crc_state), - .crc_next(crc_next5) + .lfsr_in(crc_state), + .lfsr_out(crc_next5) ); -eth_crc_56 -eth_crc_56_inst ( +lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .REVERSE(1), + .DATA_WIDTH(56), + .OUTPUT_WIDTH(32), + .STYLE("AUTO") +) +eth_crc_56 ( .data_in(fcs_input_tdata[55:0]), - .crc_state(crc_state), - .crc_next(crc_next6) + .lfsr_in(crc_state), + .lfsr_out(crc_next6) ); -eth_crc_64 -eth_crc_64_inst ( +lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .REVERSE(1), + .DATA_WIDTH(64), + .OUTPUT_WIDTH(32), + .STYLE("AUTO") +) +eth_crc_64 ( .data_in(fcs_input_tdata[63:0]), - .crc_state(crc_state), - .crc_next(crc_next7) + .lfsr_in(crc_state), + .lfsr_out(crc_next7) ); function [3:0] keep2count; diff --git a/rtl/eth_mac_10g_rx.v b/rtl/eth_mac_10g_rx.v index 7118f727..b8b098fc 100644 --- a/rtl/eth_mac_10g_rx.v +++ b/rtl/eth_mac_10g_rx.v @@ -116,39 +116,79 @@ assign error_bad_fcs = error_bad_fcs_reg; wire last_cycle = state_reg == STATE_LAST; -eth_crc_8 -eth_crc_8_inst ( +lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .REVERSE(1), + .DATA_WIDTH(8), + .OUTPUT_WIDTH(32), + .STYLE("AUTO") +) +eth_crc_8 ( .data_in(last_cycle ? xgmii_rxd_d1[39:32] : xgmii_rxd_d0[7:0]), - .crc_state(last_cycle ? crc_state3 : crc_state), - .crc_next(crc_next0) + .lfsr_in(last_cycle ? crc_state3 : crc_state), + .lfsr_out(crc_next0) ); -eth_crc_16 -eth_crc_16_inst ( +lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .REVERSE(1), + .DATA_WIDTH(16), + .OUTPUT_WIDTH(32), + .STYLE("AUTO") +) +eth_crc_16 ( .data_in(last_cycle ? xgmii_rxd_d1[47:32] : xgmii_rxd_d0[15:0]), - .crc_state(last_cycle ? crc_state3 : crc_state), - .crc_next(crc_next1) + .lfsr_in(last_cycle ? crc_state3 : crc_state), + .lfsr_out(crc_next1) ); -eth_crc_24 -eth_crc_24_inst ( +lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .REVERSE(1), + .DATA_WIDTH(24), + .OUTPUT_WIDTH(32), + .STYLE("AUTO") +) +eth_crc_24 ( .data_in(last_cycle ? xgmii_rxd_d1[55:32] : xgmii_rxd_d0[23:0]), - .crc_state(last_cycle ? crc_state3 : crc_state), - .crc_next(crc_next2) + .lfsr_in(last_cycle ? crc_state3 : crc_state), + .lfsr_out(crc_next2) ); -eth_crc_32 -eth_crc_32_inst ( +lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .REVERSE(1), + .DATA_WIDTH(32), + .OUTPUT_WIDTH(32), + .STYLE("AUTO") +) +eth_crc_32 ( .data_in(last_cycle ? xgmii_rxd_d1[63:32] : xgmii_rxd_d0[31:0]), - .crc_state(last_cycle ? crc_state3 : crc_state), - .crc_next(crc_next3) + .lfsr_in(last_cycle ? crc_state3 : crc_state), + .lfsr_out(crc_next3) ); -eth_crc_64 -eth_crc_64_inst ( +lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .REVERSE(1), + .DATA_WIDTH(64), + .OUTPUT_WIDTH(32), + .STYLE("AUTO") +) +eth_crc_64 ( .data_in(xgmii_rxd_d0[63:0]), - .crc_state(crc_state), - .crc_next(crc_next7) + .lfsr_in(crc_state), + .lfsr_out(crc_next7) ); // detect control characters diff --git a/rtl/eth_mac_10g_tx.v b/rtl/eth_mac_10g_tx.v index 20f63c96..72e7c9a6 100644 --- a/rtl/eth_mac_10g_tx.v +++ b/rtl/eth_mac_10g_tx.v @@ -125,60 +125,124 @@ assign input_axis_tready = input_axis_tready_reg; assign xgmii_txd = xgmii_txd_reg; assign xgmii_txc = xgmii_txc_reg; -eth_crc_8 -eth_crc_8_inst ( +lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .REVERSE(1), + .DATA_WIDTH(8), + .OUTPUT_WIDTH(32), + .STYLE("AUTO") +) +eth_crc_8 ( .data_in(input_tdata_reg[7:0]), - .crc_state(crc_state), - .crc_next(crc_next0) + .lfsr_in(crc_state), + .lfsr_out(crc_next0) ); -eth_crc_16 -eth_crc_16_inst ( +lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .REVERSE(1), + .DATA_WIDTH(16), + .OUTPUT_WIDTH(32), + .STYLE("AUTO") +) +eth_crc_16 ( .data_in(input_tdata_reg[15:0]), - .crc_state(crc_state), - .crc_next(crc_next1) + .lfsr_in(crc_state), + .lfsr_out(crc_next1) ); -eth_crc_24 -eth_crc_24_inst ( +lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .REVERSE(1), + .DATA_WIDTH(24), + .OUTPUT_WIDTH(32), + .STYLE("AUTO") +) +eth_crc_24 ( .data_in(input_tdata_reg[23:0]), - .crc_state(crc_state), - .crc_next(crc_next2) + .lfsr_in(crc_state), + .lfsr_out(crc_next2) ); -eth_crc_32 -eth_crc_32_inst ( +lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .REVERSE(1), + .DATA_WIDTH(32), + .OUTPUT_WIDTH(32), + .STYLE("AUTO") +) +eth_crc_32 ( .data_in(input_tdata_reg[31:0]), - .crc_state(crc_state), - .crc_next(crc_next3) + .lfsr_in(crc_state), + .lfsr_out(crc_next3) ); -eth_crc_40 -eth_crc_40_inst ( +lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .REVERSE(1), + .DATA_WIDTH(40), + .OUTPUT_WIDTH(32), + .STYLE("AUTO") +) +eth_crc_40 ( .data_in(input_tdata_reg[39:0]), - .crc_state(crc_state), - .crc_next(crc_next4) + .lfsr_in(crc_state), + .lfsr_out(crc_next4) ); -eth_crc_48 -eth_crc_48_inst ( +lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .REVERSE(1), + .DATA_WIDTH(48), + .OUTPUT_WIDTH(32), + .STYLE("AUTO") +) +eth_crc_48 ( .data_in(input_tdata_reg[47:0]), - .crc_state(crc_state), - .crc_next(crc_next5) + .lfsr_in(crc_state), + .lfsr_out(crc_next5) ); -eth_crc_56 -eth_crc_56_inst ( +lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .REVERSE(1), + .DATA_WIDTH(56), + .OUTPUT_WIDTH(32), + .STYLE("AUTO") +) +eth_crc_56 ( .data_in(input_tdata_reg[55:0]), - .crc_state(crc_state), - .crc_next(crc_next6) + .lfsr_in(crc_state), + .lfsr_out(crc_next6) ); -eth_crc_64 -eth_crc_64_inst ( +lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .REVERSE(1), + .DATA_WIDTH(64), + .OUTPUT_WIDTH(32), + .STYLE("AUTO") +) +eth_crc_64 ( .data_in(input_tdata_reg[63:0]), - .crc_state(crc_state), - .crc_next(crc_next7) + .lfsr_in(crc_state), + .lfsr_out(crc_next7) ); function [3:0] keep2count; diff --git a/rtl/eth_mac_1g_rx.v b/rtl/eth_mac_1g_rx.v index fd7128b9..9a013016 100644 --- a/rtl/eth_mac_1g_rx.v +++ b/rtl/eth_mac_1g_rx.v @@ -104,11 +104,19 @@ assign output_axis_tuser = output_axis_tuser_reg; assign error_bad_frame = error_bad_frame_reg; assign error_bad_fcs = error_bad_fcs_reg; -eth_crc_8 -eth_crc_8_inst ( +lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .REVERSE(1), + .DATA_WIDTH(8), + .OUTPUT_WIDTH(32), + .STYLE("AUTO") +) +eth_crc_8 ( .data_in(gmii_rxd_d4), - .crc_state(crc_state), - .crc_next(crc_next) + .lfsr_in(crc_state), + .lfsr_out(crc_next) ); always @* begin diff --git a/rtl/eth_mac_1g_tx.v b/rtl/eth_mac_1g_tx.v index b101ec09..6c8b62b5 100644 --- a/rtl/eth_mac_1g_tx.v +++ b/rtl/eth_mac_1g_tx.v @@ -92,11 +92,19 @@ assign gmii_txd = gmii_txd_reg; assign gmii_tx_en = gmii_tx_en_reg; assign gmii_tx_er = gmii_tx_er_reg; -eth_crc_8 -eth_crc_8_inst ( +lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .REVERSE(1), + .DATA_WIDTH(8), + .OUTPUT_WIDTH(32), + .STYLE("AUTO") +) +eth_crc_8 ( .data_in(gmii_txd_next), - .crc_state(crc_state), - .crc_next(crc_next) + .lfsr_in(crc_state), + .lfsr_out(crc_next) ); always @* begin diff --git a/tb/test_axis_eth_fcs.py b/tb/test_axis_eth_fcs.py index 7da6f103..c216acb0 100755 --- a/tb/test_axis_eth_fcs.py +++ b/tb/test_axis_eth_fcs.py @@ -39,7 +39,7 @@ module = 'axis_eth_fcs' srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/eth_crc_8.v") +srcs.append("../rtl/lfsr.v") srcs.append("test_%s.v" % module) src = ' '.join(srcs) diff --git a/tb/test_axis_eth_fcs_64.py b/tb/test_axis_eth_fcs_64.py index 7432e2ab..05e9f9eb 100755 --- a/tb/test_axis_eth_fcs_64.py +++ b/tb/test_axis_eth_fcs_64.py @@ -39,14 +39,7 @@ module = 'axis_eth_fcs_64' srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/eth_crc_8.v") -srcs.append("../rtl/eth_crc_16.v") -srcs.append("../rtl/eth_crc_24.v") -srcs.append("../rtl/eth_crc_32.v") -srcs.append("../rtl/eth_crc_40.v") -srcs.append("../rtl/eth_crc_48.v") -srcs.append("../rtl/eth_crc_56.v") -srcs.append("../rtl/eth_crc_64.v") +srcs.append("../rtl/lfsr.v") srcs.append("test_%s.v" % module) src = ' '.join(srcs) diff --git a/tb/test_axis_eth_fcs_check.py b/tb/test_axis_eth_fcs_check.py index 7f55d5bc..c4bdd2f3 100755 --- a/tb/test_axis_eth_fcs_check.py +++ b/tb/test_axis_eth_fcs_check.py @@ -41,7 +41,7 @@ module = 'axis_eth_fcs_check' srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/eth_crc_8.v") +srcs.append("../rtl/lfsr.v") srcs.append("test_%s.v" % module) src = ' '.join(srcs) diff --git a/tb/test_axis_eth_fcs_check_64.py b/tb/test_axis_eth_fcs_check_64.py index 7431d5e9..13f84167 100755 --- a/tb/test_axis_eth_fcs_check_64.py +++ b/tb/test_axis_eth_fcs_check_64.py @@ -41,14 +41,7 @@ module = 'axis_eth_fcs_check_64' srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/eth_crc_8.v") -srcs.append("../rtl/eth_crc_16.v") -srcs.append("../rtl/eth_crc_24.v") -srcs.append("../rtl/eth_crc_32.v") -srcs.append("../rtl/eth_crc_40.v") -srcs.append("../rtl/eth_crc_48.v") -srcs.append("../rtl/eth_crc_56.v") -srcs.append("../rtl/eth_crc_64.v") +srcs.append("../rtl/lfsr.v") srcs.append("test_%s.v" % module) src = ' '.join(srcs) diff --git a/tb/test_axis_eth_fcs_insert.py b/tb/test_axis_eth_fcs_insert.py index 5c14a407..249ffd63 100755 --- a/tb/test_axis_eth_fcs_insert.py +++ b/tb/test_axis_eth_fcs_insert.py @@ -41,7 +41,7 @@ module = 'axis_eth_fcs_insert' srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/eth_crc_8.v") +srcs.append("../rtl/lfsr.v") srcs.append("test_%s.v" % module) src = ' '.join(srcs) diff --git a/tb/test_axis_eth_fcs_insert_64.py b/tb/test_axis_eth_fcs_insert_64.py index 45546b4b..aa58f3b8 100755 --- a/tb/test_axis_eth_fcs_insert_64.py +++ b/tb/test_axis_eth_fcs_insert_64.py @@ -41,14 +41,7 @@ module = 'axis_eth_fcs_insert_64' srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/eth_crc_8.v") -srcs.append("../rtl/eth_crc_16.v") -srcs.append("../rtl/eth_crc_24.v") -srcs.append("../rtl/eth_crc_32.v") -srcs.append("../rtl/eth_crc_40.v") -srcs.append("../rtl/eth_crc_48.v") -srcs.append("../rtl/eth_crc_56.v") -srcs.append("../rtl/eth_crc_64.v") +srcs.append("../rtl/lfsr.v") srcs.append("test_%s.v" % module) src = ' '.join(srcs) diff --git a/tb/test_axis_eth_fcs_insert_64_pad.py b/tb/test_axis_eth_fcs_insert_64_pad.py index 4eeacdb2..e1ae380a 100755 --- a/tb/test_axis_eth_fcs_insert_64_pad.py +++ b/tb/test_axis_eth_fcs_insert_64_pad.py @@ -41,14 +41,7 @@ module = 'axis_eth_fcs_insert_64' srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/eth_crc_8.v") -srcs.append("../rtl/eth_crc_16.v") -srcs.append("../rtl/eth_crc_24.v") -srcs.append("../rtl/eth_crc_32.v") -srcs.append("../rtl/eth_crc_40.v") -srcs.append("../rtl/eth_crc_48.v") -srcs.append("../rtl/eth_crc_56.v") -srcs.append("../rtl/eth_crc_64.v") +srcs.append("../rtl/lfsr.v") srcs.append("test_%s_pad.v" % module) src = ' '.join(srcs) diff --git a/tb/test_axis_eth_fcs_insert_pad.py b/tb/test_axis_eth_fcs_insert_pad.py index 811b1fe6..5d537fdd 100755 --- a/tb/test_axis_eth_fcs_insert_pad.py +++ b/tb/test_axis_eth_fcs_insert_pad.py @@ -41,7 +41,7 @@ module = 'axis_eth_fcs_insert' srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/eth_crc_8.v") +srcs.append("../rtl/lfsr.v") srcs.append("test_%s_pad.v" % module) src = ' '.join(srcs) diff --git a/tb/test_eth_mac_10g.py b/tb/test_eth_mac_10g.py index bccb9827..15bdf246 100755 --- a/tb/test_eth_mac_10g.py +++ b/tb/test_eth_mac_10g.py @@ -40,14 +40,7 @@ module = 'eth_mac_10g' srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/eth_crc_8.v") -srcs.append("../rtl/eth_crc_16.v") -srcs.append("../rtl/eth_crc_24.v") -srcs.append("../rtl/eth_crc_32.v") -srcs.append("../rtl/eth_crc_40.v") -srcs.append("../rtl/eth_crc_48.v") -srcs.append("../rtl/eth_crc_56.v") -srcs.append("../rtl/eth_crc_64.v") +srcs.append("../rtl/lfsr.v") srcs.append("../rtl/eth_mac_10g_rx.v") srcs.append("../rtl/eth_mac_10g_tx.v") srcs.append("test_%s.v" % module) diff --git a/tb/test_eth_mac_10g_fifo.py b/tb/test_eth_mac_10g_fifo.py index f7689baf..f647fe51 100755 --- a/tb/test_eth_mac_10g_fifo.py +++ b/tb/test_eth_mac_10g_fifo.py @@ -40,14 +40,7 @@ module = 'eth_mac_10g_fifo' srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/eth_crc_8.v") -srcs.append("../rtl/eth_crc_16.v") -srcs.append("../rtl/eth_crc_24.v") -srcs.append("../rtl/eth_crc_32.v") -srcs.append("../rtl/eth_crc_40.v") -srcs.append("../rtl/eth_crc_48.v") -srcs.append("../rtl/eth_crc_56.v") -srcs.append("../rtl/eth_crc_64.v") +srcs.append("../rtl/lfsr.v") srcs.append("../rtl/eth_mac_10g_rx.v") srcs.append("../rtl/eth_mac_10g_tx.v") srcs.append("../rtl/eth_mac_10g.v") diff --git a/tb/test_eth_mac_10g_rx.py b/tb/test_eth_mac_10g_rx.py index 21e1e2a2..e2cf1a68 100755 --- a/tb/test_eth_mac_10g_rx.py +++ b/tb/test_eth_mac_10g_rx.py @@ -42,14 +42,7 @@ module = 'eth_mac_10g_rx' srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/eth_crc_8.v") -srcs.append("../rtl/eth_crc_16.v") -srcs.append("../rtl/eth_crc_24.v") -srcs.append("../rtl/eth_crc_32.v") -srcs.append("../rtl/eth_crc_40.v") -srcs.append("../rtl/eth_crc_48.v") -srcs.append("../rtl/eth_crc_56.v") -srcs.append("../rtl/eth_crc_64.v") +srcs.append("../rtl/lfsr.v") srcs.append("test_%s.v" % module) src = ' '.join(srcs) diff --git a/tb/test_eth_mac_10g_tx.py b/tb/test_eth_mac_10g_tx.py index 92167022..a5bdecff 100755 --- a/tb/test_eth_mac_10g_tx.py +++ b/tb/test_eth_mac_10g_tx.py @@ -40,14 +40,7 @@ module = 'eth_mac_10g_tx' srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/eth_crc_8.v") -srcs.append("../rtl/eth_crc_16.v") -srcs.append("../rtl/eth_crc_24.v") -srcs.append("../rtl/eth_crc_32.v") -srcs.append("../rtl/eth_crc_40.v") -srcs.append("../rtl/eth_crc_48.v") -srcs.append("../rtl/eth_crc_56.v") -srcs.append("../rtl/eth_crc_64.v") +srcs.append("../rtl/lfsr.v") srcs.append("test_%s.v" % module) src = ' '.join(srcs) diff --git a/tb/test_eth_mac_1g.py b/tb/test_eth_mac_1g.py index 6e446d59..88a75ff7 100755 --- a/tb/test_eth_mac_1g.py +++ b/tb/test_eth_mac_1g.py @@ -40,7 +40,7 @@ module = 'eth_mac_1g' srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/eth_crc_8.v") +srcs.append("../rtl/lfsr.v") srcs.append("../rtl/eth_mac_1g_rx.v") srcs.append("../rtl/eth_mac_1g_tx.v") srcs.append("test_%s.v" % module) diff --git a/tb/test_eth_mac_1g_fifo.py b/tb/test_eth_mac_1g_fifo.py index 3db86968..e67a52bd 100755 --- a/tb/test_eth_mac_1g_fifo.py +++ b/tb/test_eth_mac_1g_fifo.py @@ -40,7 +40,7 @@ module = 'eth_mac_1g_fifo' srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/eth_crc_8.v") +srcs.append("../rtl/lfsr.v") srcs.append("../rtl/eth_mac_1g_rx.v") srcs.append("../rtl/eth_mac_1g_tx.v") srcs.append("../rtl/eth_mac_1g.v") diff --git a/tb/test_eth_mac_1g_rx.py b/tb/test_eth_mac_1g_rx.py index 4bf2afca..de9a6300 100755 --- a/tb/test_eth_mac_1g_rx.py +++ b/tb/test_eth_mac_1g_rx.py @@ -40,7 +40,7 @@ module = 'eth_mac_1g_rx' srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/eth_crc_8.v") +srcs.append("../rtl/lfsr.v") srcs.append("test_%s.v" % module) src = ' '.join(srcs) diff --git a/tb/test_eth_mac_1g_tx.py b/tb/test_eth_mac_1g_tx.py index 2963ecad..d8cecb3d 100755 --- a/tb/test_eth_mac_1g_tx.py +++ b/tb/test_eth_mac_1g_tx.py @@ -40,7 +40,7 @@ module = 'eth_mac_1g_tx' srcs = [] srcs.append("../rtl/%s.v" % module) -srcs.append("../rtl/eth_crc_8.v") +srcs.append("../rtl/lfsr.v") srcs.append("test_%s.v" % module) src = ' '.join(srcs)