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https://github.com/alexforencich/verilog-ethernet.git
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Fix mixed assignments
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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@ -203,9 +203,9 @@ if (PIPELINE_OUTPUT > 0) begin
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if (output_rst) begin
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for (i = 0; i < PIPELINE_OUTPUT; i = i + 1) begin
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output_ts_reg[i] = 0;
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output_ts_step_reg[i] = 1'b0;
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output_pps_reg[i] = 1'b0;
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output_ts_reg[i] <= 0;
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output_ts_step_reg[i] <= 1'b0;
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output_pps_reg[i] <= 1'b0;
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end
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end
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end
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@ -800,11 +800,11 @@ always @(posedge output_clk) begin
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ptp_locked_reg <= 1'b0;
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for (i = 0; i < PIPELINE_OUTPUT; i = i + 1) begin
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ts_s_pipe_reg[i] = 0;
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ts_ns_pipe_reg[i] = 0;
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ts_fns_pipe_reg[i] = 0;
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ts_step_pipe_reg[i] = 1'b0;
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pps_pipe_reg[i] = 1'b0;
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ts_s_pipe_reg[i] <= 0;
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ts_ns_pipe_reg[i] <= 0;
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ts_fns_pipe_reg[i] <= 0;
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ts_step_pipe_reg[i] <= 1'b0;
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pps_pipe_reg[i] <= 1'b0;
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end
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end
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end
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