FPGA/verilog-ethernet
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Add defaults

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This commit is contained in:
Alex Forencich 2014-09-19 17:33:23 -07:00
parent fa72cc2035
commit 4ad302949f
2 changed files with 30 additions and 30 deletions
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48
tb/arp_ep.py
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@ -153,18 +153,18 @@ class ARPFrame(object):
def ARPFrameSource(clk, rst,
frame_valid=None,
frame_ready=None,
eth_dest_mac=None,
eth_src_mac=None,
eth_type=None,
arp_htype=None,
arp_ptype=None,
arp_hlen=Signal(intbv(0)[8:]),
arp_plen=Signal(intbv(0)[8:]),
arp_oper=None,
arp_sha=None,
arp_spa=None,
arp_tha=None,
arp_tpa=None,
eth_dest_mac=Signal(intbv(0)[48:]),
eth_src_mac=Signal(intbv(0)[48:]),
eth_type=Signal(intbv(0)[16:]),
arp_htype=Signal(intbv(0)[16:]),
arp_ptype=Signal(intbv(0)[16:]),
arp_hlen=Signal(intbv(6)[8:]),
arp_plen=Signal(intbv(4)[8:]),
arp_oper=Signal(intbv(0)[16:]),
arp_sha=Signal(intbv(0)[48:]),
arp_spa=Signal(intbv(0)[32:]),
arp_tha=Signal(intbv(0)[48:]),
arp_tpa=Signal(intbv(0)[32:]),
fifo=None,
pause=0,
name=None):
@ -217,18 +217,18 @@ def ARPFrameSource(clk, rst,
def ARPFrameSink(clk, rst,
frame_valid=None,
frame_ready=None,
eth_dest_mac=None,
eth_src_mac=None,
eth_type=None,
arp_htype=None,
arp_ptype=None,
arp_hlen=None,
arp_plen=None,
arp_oper=None,
arp_sha=None,
arp_spa=None,
arp_tha=None,
arp_tpa=None,
eth_dest_mac=Signal(intbv(0)[48:]),
eth_src_mac=Signal(intbv(0)[48:]),
eth_type=Signal(intbv(0)[16:]),
arp_htype=Signal(intbv(0)[16:]),
arp_ptype=Signal(intbv(0)[16:]),
arp_hlen=Signal(intbv(6)[8:]),
arp_plen=Signal(intbv(4)[8:]),
arp_oper=Signal(intbv(0)[16:]),
arp_sha=Signal(intbv(0)[48:]),
arp_spa=Signal(intbv(0)[32:]),
arp_tha=Signal(intbv(0)[48:]),
arp_tpa=Signal(intbv(0)[32:]),
fifo=None,
pause=0,
name=None):

12
tb/eth_ep.py
View File

@ -89,9 +89,9 @@ class EthFrame(object):
def EthFrameSource(clk, rst,
eth_hdr_valid=None,
eth_hdr_ready=None,
eth_dest_mac=None,
eth_src_mac=None,
eth_type=None,
eth_dest_mac=Signal(intbv(0)[48:]),
eth_src_mac=Signal(intbv(0)[48:]),
eth_type=Signal(intbv(0)[16:]),
eth_payload_tdata=None,
eth_payload_tkeep=Signal(bool(True)),
eth_payload_tvalid=Signal(bool(False)),
@ -157,9 +157,9 @@ def EthFrameSource(clk, rst,
def EthFrameSink(clk, rst,
eth_hdr_valid=None,
eth_hdr_ready=None,
eth_dest_mac=None,
eth_src_mac=None,
eth_type=None,
eth_dest_mac=Signal(intbv(0)[48:]),
eth_src_mac=Signal(intbv(0)[48:]),
eth_type=Signal(intbv(0)[16:]),
eth_payload_tdata=None,
eth_payload_tkeep=Signal(bool(True)),
eth_payload_tvalid=Signal(bool(True)),