From a7689b67725c8fe7b72d95b2a71d9b1f5ed8a8d0 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Thu, 3 Sep 2020 15:55:45 -0700 Subject: [PATCH] Pipeline RAM output in RAM switch --- rtl/axis_ram_switch.v | 30 +++++++++++++++++++-------- tb/test_axis_ram_switch_1x4_256_64.py | 1 + tb/test_axis_ram_switch_1x4_256_64.v | 4 +++- tb/test_axis_ram_switch_4x1_64_256.py | 1 + tb/test_axis_ram_switch_4x1_64_256.v | 4 +++- tb/test_axis_ram_switch_4x4_64_64.py | 1 + tb/test_axis_ram_switch_4x4_64_64.v | 4 +++- 7 files changed, 33 insertions(+), 12 deletions(-) diff --git a/rtl/axis_ram_switch.v b/rtl/axis_ram_switch.v index 7a2be8e1..e5bb03c1 100644 --- a/rtl/axis_ram_switch.v +++ b/rtl/axis_ram_switch.v @@ -93,7 +93,9 @@ module axis_ram_switch # // arbitration type: "PRIORITY" or "ROUND_ROBIN" parameter ARB_TYPE = "ROUND_ROBIN", // LSB priority: "LOW", "HIGH" - parameter LSB_PRIORITY = "HIGH" + parameter LSB_PRIORITY = "HIGH", + // RAM read data output pipeline stages + parameter RAM_PIPELINE = 2 ) ( input wire clk, @@ -217,8 +219,8 @@ end // Shared RAM reg [DATA_WIDTH-1:0] mem[(2**RAM_ADDR_WIDTH)-1:0]; -reg [DATA_WIDTH-1:0] mem_read_data_reg; -reg [M_COUNT-1:0] mem_read_data_valid_reg; +reg [DATA_WIDTH-1:0] mem_read_data_reg[RAM_PIPELINE-1:0]; +reg [M_COUNT-1:0] mem_read_data_valid_reg[RAM_PIPELINE-1:0]; wire [S_COUNT*DATA_WIDTH-1:0] port_ram_wr_data; wire [S_COUNT*RAM_ADDR_WIDTH-1:0] port_ram_wr_addr; @@ -231,8 +233,8 @@ wire [M_COUNT-1:0] port_ram_rd_ack; wire [M_COUNT*DATA_WIDTH-1:0] port_ram_rd_data; wire [M_COUNT-1:0] port_ram_rd_data_valid; -assign port_ram_rd_data = {M_COUNT{mem_read_data_reg}}; -assign port_ram_rd_data_valid = mem_read_data_valid_reg; +assign port_ram_rd_data = {M_COUNT{mem_read_data_reg[RAM_PIPELINE-1]}}; +assign port_ram_rd_data_valid = mem_read_data_valid_reg[RAM_PIPELINE-1]; wire [CL_S_COUNT-1:0] ram_wr_sel; wire ram_wr_en; @@ -306,16 +308,26 @@ end endgenerate +integer s; + always @(posedge clk) begin - mem_read_data_valid_reg <= 0; + mem_read_data_valid_reg[0] <= 0; + + for (s = RAM_PIPELINE-1; s > 0; s = s - 1) begin + mem_read_data_reg[s] <= mem_read_data_reg[s-1]; + mem_read_data_valid_reg[s] <= mem_read_data_valid_reg[s-1]; + end if (ram_rd_en) begin - mem_read_data_reg <= mem[port_ram_rd_addr[ram_rd_sel*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH]]; - mem_read_data_valid_reg <= 1 << ram_rd_sel; + mem_read_data_reg[0] <= mem[port_ram_rd_addr[ram_rd_sel*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH]]; + mem_read_data_valid_reg[0] <= 1 << ram_rd_sel; end if (rst) begin - mem_read_data_valid_reg <= 0; + mem_read_data_valid_reg[0] <= 0; + for (s = 0; s < RAM_PIPELINE; s = s + 1) begin + mem_read_data_valid_reg[s] <= 0; + end end end diff --git a/tb/test_axis_ram_switch_1x4_256_64.py b/tb/test_axis_ram_switch_1x4_256_64.py index 66ae46d2..fe70d77c 100755 --- a/tb/test_axis_ram_switch_1x4_256_64.py +++ b/tb/test_axis_ram_switch_1x4_256_64.py @@ -72,6 +72,7 @@ def bench(): M_CONNECT = [0b1111]*M_COUNT ARB_TYPE = "ROUND_ROBIN" LSB_PRIORITY = "HIGH" + RAM_PIPELINE = 2 # Inputs clk = Signal(bool(0)) diff --git a/tb/test_axis_ram_switch_1x4_256_64.v b/tb/test_axis_ram_switch_1x4_256_64.v index e5b20ff7..04961586 100644 --- a/tb/test_axis_ram_switch_1x4_256_64.v +++ b/tb/test_axis_ram_switch_1x4_256_64.v @@ -56,6 +56,7 @@ parameter M_TOP = {3'd3, 3'd2, 3'd1, 3'd0}; parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}}; parameter ARB_TYPE = "ROUND_ROBIN"; parameter LSB_PRIORITY = "HIGH"; +parameter RAM_PIPELINE = 2; // Inputs reg clk = 0; @@ -142,7 +143,8 @@ axis_ram_switch #( .M_TOP(M_TOP), .M_CONNECT(M_CONNECT), .ARB_TYPE(ARB_TYPE), - .LSB_PRIORITY(LSB_PRIORITY) + .LSB_PRIORITY(LSB_PRIORITY), + .RAM_PIPELINE(RAM_PIPELINE) ) UUT ( .clk(clk), diff --git a/tb/test_axis_ram_switch_4x1_64_256.py b/tb/test_axis_ram_switch_4x1_64_256.py index 45b933b0..72c013bf 100755 --- a/tb/test_axis_ram_switch_4x1_64_256.py +++ b/tb/test_axis_ram_switch_4x1_64_256.py @@ -72,6 +72,7 @@ def bench(): M_CONNECT = [0b1111]*M_COUNT ARB_TYPE = "ROUND_ROBIN" LSB_PRIORITY = "HIGH" + RAM_PIPELINE = 2 # Inputs clk = Signal(bool(0)) diff --git a/tb/test_axis_ram_switch_4x1_64_256.v b/tb/test_axis_ram_switch_4x1_64_256.v index 44a760b2..f32cc106 100644 --- a/tb/test_axis_ram_switch_4x1_64_256.v +++ b/tb/test_axis_ram_switch_4x1_64_256.v @@ -56,6 +56,7 @@ parameter M_TOP = {3'd3, 3'd2, 3'd1, 3'd0}; parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}}; parameter ARB_TYPE = "ROUND_ROBIN"; parameter LSB_PRIORITY = "HIGH"; +parameter RAM_PIPELINE = 2; // Inputs reg clk = 0; @@ -142,7 +143,8 @@ axis_ram_switch #( .M_TOP(M_TOP), .M_CONNECT(M_CONNECT), .ARB_TYPE(ARB_TYPE), - .LSB_PRIORITY(LSB_PRIORITY) + .LSB_PRIORITY(LSB_PRIORITY), + .RAM_PIPELINE(RAM_PIPELINE) ) UUT ( .clk(clk), diff --git a/tb/test_axis_ram_switch_4x4_64_64.py b/tb/test_axis_ram_switch_4x4_64_64.py index 5628f39a..3896930a 100755 --- a/tb/test_axis_ram_switch_4x4_64_64.py +++ b/tb/test_axis_ram_switch_4x4_64_64.py @@ -70,6 +70,7 @@ def bench(): M_CONNECT = [0b1111]*M_COUNT ARB_TYPE = "ROUND_ROBIN" LSB_PRIORITY = "HIGH" + RAM_PIPELINE = 2 # Inputs clk = Signal(bool(0)) diff --git a/tb/test_axis_ram_switch_4x4_64_64.v b/tb/test_axis_ram_switch_4x4_64_64.v index 1882ee25..576c68e1 100644 --- a/tb/test_axis_ram_switch_4x4_64_64.v +++ b/tb/test_axis_ram_switch_4x4_64_64.v @@ -56,6 +56,7 @@ parameter M_TOP = {3'd3, 3'd2, 3'd1, 3'd0}; parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}}; parameter ARB_TYPE = "ROUND_ROBIN"; parameter LSB_PRIORITY = "HIGH"; +parameter RAM_PIPELINE = 2; // Inputs reg clk = 0; @@ -142,7 +143,8 @@ axis_ram_switch #( .M_TOP(M_TOP), .M_CONNECT(M_CONNECT), .ARB_TYPE(ARB_TYPE), - .LSB_PRIORITY(LSB_PRIORITY) + .LSB_PRIORITY(LSB_PRIORITY), + .RAM_PIPELINE(RAM_PIPELINE) ) UUT ( .clk(clk),