FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-14 06:43:18 +08:00
Code Issues Projects Releases Wiki Activity

merged changes in axis

Browse Source
This commit is contained in:
Alex Forencich 2019-03-07 23:43:13 -08:00
commit 4d3036b9d0
46 changed files with 2204 additions and 152 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
lib/axis/README.md
View File

@ -40,6 +40,11 @@ Configurable word-based or frame-based asynchronous FIFO with parametrizable
data width, depth, type, and bad frame detection. Supports power of two
depths only.
### axis_broadcast module
AXI stream broadcaster. Duplicates one input stream across multiple output
streams.
### axis_cobs_decode
Consistent Overhead Byte Stuffing (COBS) decoder. Fixed 8 bit width.
@ -186,6 +191,7 @@ Parametrizable priority encoder.
axis_adapter.v : Parametrizable bus width adapter
axis_arb_mux.v : Parametrizable arbitrated multiplexer
axis_async_fifo.v : Parametrizable asynchronous FIFO
axis_broadcast.v : AXI stream broadcaster
axis_cobs_decode.v : COBS decoder
axis_cobs_encode.v : COBS encoder
axis_crosspoint.v : Parametrizable crosspoint switch

180
lib/axis/rtl/axis_broadcast.v Normal file
View File

@ -0,0 +1,180 @@
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream broadcaster
*/
module axis_broadcast #
(
parameter M_COUNT = 4,
parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter LAST_ENABLE = 1,
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [ID_WIDTH-1:0] s_axis_tid,
input wire [DEST_WIDTH-1:0] s_axis_tdest,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI outputs
*/
output wire [M_COUNT*DATA_WIDTH-1:0] m_axis_tdata,
output wire [M_COUNT*KEEP_WIDTH-1:0] m_axis_tkeep,
output wire [M_COUNT-1:0] m_axis_tvalid,
input wire [M_COUNT-1:0] m_axis_tready,
output wire [M_COUNT-1:0] m_axis_tlast,
output wire [M_COUNT*ID_WIDTH-1:0] m_axis_tid,
output wire [M_COUNT*DEST_WIDTH-1:0] m_axis_tdest,
output wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser
);
parameter CL_M_COUNT = $clog2(M_COUNT);
// datapath registers
reg s_axis_tready_reg = 1'b0, s_axis_tready_next;
reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg [M_COUNT-1:0] m_axis_tvalid_reg = {M_COUNT{1'b0}}, m_axis_tvalid_next;
reg m_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
reg temp_m_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] temp_m_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_m_axis_tuser_reg = {USER_WIDTH{1'b0}};
// // datapath control
reg store_axis_input_to_output;
reg store_axis_input_to_temp;
reg store_axis_temp_to_output;
assign s_axis_tready = s_axis_tready_reg;
assign m_axis_tdata = {M_COUNT{m_axis_tdata_reg}};
assign m_axis_tkeep = KEEP_ENABLE ? {M_COUNT{m_axis_tkeep_reg}} : {M_COUNT*KEEP_WIDTH{1'b1}};
assign m_axis_tvalid = m_axis_tvalid_reg;
assign m_axis_tlast = LAST_ENABLE ? {M_COUNT{m_axis_tlast_reg}} : {M_COUNT{1'b1}};
assign m_axis_tid = ID_ENABLE ? {M_COUNT{m_axis_tid_reg}} : {M_COUNT*ID_WIDTH{1'b0}};
assign m_axis_tdest = DEST_ENABLE ? {M_COUNT{m_axis_tdest_reg}} : {M_COUNT*DEST_WIDTH{1'b0}};
assign m_axis_tuser = USER_ENABLE ? {M_COUNT{m_axis_tuser_reg}} : {M_COUNT*USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
wire s_axis_tready_early = ((m_axis_tready & m_axis_tvalid) == m_axis_tvalid) || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid || !s_axis_tvalid));
always @* begin
// transfer sink ready state to source
m_axis_tvalid_next = m_axis_tvalid_reg & ~m_axis_tready;
temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
store_axis_input_to_output = 1'b0;
store_axis_input_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (s_axis_tready_reg) begin
// input is ready
if (((m_axis_tready & m_axis_tvalid) == m_axis_tvalid) || !m_axis_tvalid) begin
// output is ready or currently not valid, transfer data to output
m_axis_tvalid_next = {M_COUNT{s_axis_tvalid}};
store_axis_input_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_axis_tvalid_next = s_axis_tvalid;
store_axis_input_to_temp = 1'b1;
end
end else if ((m_axis_tready & m_axis_tvalid) == m_axis_tvalid) begin
// input is not ready, but output is ready
m_axis_tvalid_next = {M_COUNT{temp_m_axis_tvalid_reg}};
temp_m_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
s_axis_tready_reg <= 1'b0;
m_axis_tvalid_reg <= {M_COUNT{1'b0}};
temp_m_axis_tvalid_reg <= {M_COUNT{1'b0}};
end else begin
s_axis_tready_reg <= s_axis_tready_early;
m_axis_tvalid_reg <= m_axis_tvalid_next;
temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
end
// datapath
if (store_axis_input_to_output) begin
m_axis_tdata_reg <= s_axis_tdata;
m_axis_tkeep_reg <= s_axis_tkeep;
m_axis_tlast_reg <= s_axis_tlast;
m_axis_tid_reg <= s_axis_tid;
m_axis_tdest_reg <= s_axis_tdest;
m_axis_tuser_reg <= s_axis_tuser;
end else if (store_axis_temp_to_output) begin
m_axis_tdata_reg <= temp_m_axis_tdata_reg;
m_axis_tkeep_reg <= temp_m_axis_tkeep_reg;
m_axis_tlast_reg <= temp_m_axis_tlast_reg;
m_axis_tid_reg <= temp_m_axis_tid_reg;
m_axis_tdest_reg <= temp_m_axis_tdest_reg;
m_axis_tuser_reg <= temp_m_axis_tuser_reg;
end
if (store_axis_input_to_temp) begin
temp_m_axis_tdata_reg <= s_axis_tdata;
temp_m_axis_tkeep_reg <= s_axis_tkeep;
temp_m_axis_tlast_reg <= s_axis_tlast;
temp_m_axis_tid_reg <= s_axis_tid;
temp_m_axis_tdest_reg <= s_axis_tdest;
temp_m_axis_tuser_reg <= s_axis_tuser;
end
end
endmodule

2
lib/axis/rtl/axis_demux.v
View File

@ -99,8 +99,6 @@ wire m_axis_tready_int_early;
assign s_axis_tready = s_axis_tready_reg && enable;
integer i;
always @* begin
select_next = select_reg;
select_ctl = select_reg;

110
lib/axis/rtl/axis_frame_len.v Normal file
View File

@ -0,0 +1,110 @@
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream frame length measurement
*/
module axis_frame_len #
(
parameter DATA_WIDTH = 64,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter LEN_WIDTH = 16
)
(
input wire clk,
input wire rst,
/*
* AXI monitor
*/
input wire [KEEP_WIDTH-1:0] monitor_axis_tkeep,
input wire monitor_axis_tvalid,
input wire monitor_axis_tready,
input wire monitor_axis_tlast,
/*
* Status
*/
output wire [LEN_WIDTH-1:0] frame_len,
output wire frame_len_valid
);
reg [LEN_WIDTH-1:0] frame_len_reg = 0, frame_len_next;
reg frame_len_valid_reg = 1'b0, frame_len_valid_next;
reg frame_reg = 1'b0, frame_next;
assign frame_len = frame_len_reg;
assign frame_len_valid = frame_len_valid_reg;
integer offset, i, bit_cnt;
always @* begin
frame_len_next = frame_len_reg;
frame_len_valid_next = 1'b0;
frame_next = frame_reg;
if (monitor_axis_tready && monitor_axis_tvalid) begin
// valid transfer cycle
if (monitor_axis_tlast) begin
// end of frame
frame_len_valid_next = 1'b1;
frame_next = 1'b0;
end else if (!frame_reg) begin
// first word after end of frame
frame_len_next = 0;
frame_next = 1'b1;
end
// increment frame length by number of words transferred
if (KEEP_ENABLE) begin
bit_cnt = 0;
for (i = 0; i <= KEEP_WIDTH; i = i + 1) begin
if (monitor_axis_tkeep == ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-i)) bit_cnt = i;
end
frame_len_next = frame_len_next + bit_cnt;
end else begin
frame_len_next = frame_len_next + 1;
end
end
end
always @(posedge clk) begin
if (rst) begin
frame_len_reg <= 0;
frame_len_valid_reg <= 0;
frame_reg <= 1'b0;
end else begin
frame_len_reg <= frame_len_next;
frame_len_valid_reg <= frame_len_valid_next;
frame_reg <= frame_next;
end
end
endmodule

6
lib/axis/rtl/priority_encoder.v
View File

@ -47,7 +47,11 @@ parameter W1 = 2**$clog2(WIDTH);
parameter W2 = W1/2;
generate
if (WIDTH == 2) begin
if (WIDTH == 1) begin
// one input
assign output_valid = input_unencoded;
assign output_encoded = 0;
end else if (WIDTH == 2) begin
// two inputs - just an OR gate
assign output_valid = |input_unencoded;
if (LSB_PRIORITY == "LOW") begin

6
lib/axis/tb/test_axis_adapter_64_8.py
View File

@ -157,12 +157,14 @@ def bench():
def wait_pause_source():
while s_axis_tvalid or m_axis_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
source_pause.next = True
yield clk.posedge
source_pause.next = False
def wait_pause_sink():
while s_axis_tvalid or m_axis_tvalid:

6
lib/axis/tb/test_axis_adapter_8_64.py
View File

@ -157,12 +157,14 @@ def bench():
def wait_pause_source():
while s_axis_tvalid or m_axis_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
source_pause.next = True
yield clk.posedge
source_pause.next = False
def wait_pause_sink():
while s_axis_tvalid or m_axis_tvalid:

13
lib/axis/tb/test_axis_arb_mux_4.py
View File

@ -302,7 +302,7 @@ def bench():
yield delay(100)
yield clk.posedge
print("test 5: alterate pause source")
print("test 5: alternate pause source")
current_test.next = 5
test_frame1 = axis_ep.AXIStreamFrame(
@ -327,14 +327,17 @@ def bench():
yield clk.posedge
while s_axis_tvalid:
for k in range(S_COUNT):
source_pause_list[k].next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
for k in range(S_COUNT):
source_pause_list[k].next = False
yield clk.posedge
for k in range(S_COUNT):
source_pause_list[k].next = True
yield clk.posedge
for k in range(S_COUNT):
source_pause_list[k].next = False
yield sink.wait()
rx_frame = sink.recv()
@ -349,7 +352,7 @@ def bench():
yield delay(100)
yield clk.posedge
print("test 6: alterate pause sink")
print("test 6: alternate pause sink")
current_test.next = 6
test_frame1 = axis_ep.AXIStreamFrame(

13
lib/axis/tb/test_axis_arb_mux_4_64.py
View File

@ -302,7 +302,7 @@ def bench():
yield delay(100)
yield clk.posedge
print("test 5: alterate pause source")
print("test 5: alternate pause source")
current_test.next = 5
test_frame1 = axis_ep.AXIStreamFrame(
@ -327,14 +327,17 @@ def bench():
yield clk.posedge
while s_axis_tvalid:
for k in range(S_COUNT):
source_pause_list[k].next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
for k in range(S_COUNT):
source_pause_list[k].next = False
yield clk.posedge
for k in range(S_COUNT):
source_pause_list[k].next = True
yield clk.posedge
for k in range(S_COUNT):
source_pause_list[k].next = False
yield sink.wait()
rx_frame = sink.recv()
@ -349,7 +352,7 @@ def bench():
yield delay(100)
yield clk.posedge
print("test 6: alterate pause sink")
print("test 6: alternate pause sink")
current_test.next = 6
test_frame1 = axis_ep.AXIStreamFrame(

6
lib/axis/tb/test_axis_async_fifo.py
View File

@ -320,12 +320,14 @@ def bench():
yield s_clk.posedge
while s_axis_tvalid or m_axis_tvalid:
source_pause.next = True
yield s_clk.posedge
yield s_clk.posedge
yield s_clk.posedge
source_pause.next = False
yield s_clk.posedge
source_pause.next = True
yield s_clk.posedge
source_pause.next = False
yield sink.wait()
rx_frame = sink.recv()

6
lib/axis/tb/test_axis_async_fifo_64.py
View File

@ -320,12 +320,14 @@ def bench():
yield s_clk.posedge
while s_axis_tvalid or m_axis_tvalid:
source_pause.next = True
yield s_clk.posedge
yield s_clk.posedge
yield s_clk.posedge
source_pause.next = False
yield s_clk.posedge
source_pause.next = True
yield s_clk.posedge
source_pause.next = False
yield sink.wait()
rx_frame = sink.recv()

6
lib/axis/tb/test_axis_async_frame_fifo.py
View File

@ -418,12 +418,14 @@ def bench():
yield s_clk.posedge
while s_axis_tvalid or m_axis_tvalid:
source_pause.next = True
yield s_clk.posedge
yield s_clk.posedge
yield s_clk.posedge
source_pause.next = False
yield s_clk.posedge
source_pause.next = True
yield s_clk.posedge
source_pause.next = False
yield sink.wait()
rx_frame = sink.recv()

6
lib/axis/tb/test_axis_async_frame_fifo_64.py
View File

@ -418,12 +418,14 @@ def bench():
yield s_clk.posedge
while s_axis_tvalid or m_axis_tvalid:
source_pause.next = True
yield s_clk.posedge
yield s_clk.posedge
yield s_clk.posedge
source_pause.next = False
yield s_clk.posedge
source_pause.next = True
yield s_clk.posedge
source_pause.next = False
yield sink.wait()
rx_frame = sink.recv()

540
lib/axis/tb/test_axis_broadcast_4.py Executable file
View File

@ -0,0 +1,540 @@
#!/usr/bin/env python
"""
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
"""
from myhdl import *
import os
import axis_ep
import math
module = 'axis_broadcast'
testbench = 'test_%s_4' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
M_COUNT = 4
DATA_WIDTH = 8
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8)
LAST_ENABLE = 1
ID_ENABLE = 1
ID_WIDTH = 8
DEST_ENABLE = 1
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
s_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
s_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
s_axis_tvalid = Signal(bool(0))
s_axis_tlast = Signal(bool(0))
s_axis_tid = Signal(intbv(0)[ID_WIDTH:])
s_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
s_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
m_axis_tready_list = [Signal(bool(0)) for i in range(M_COUNT)]
m_axis_tready = ConcatSignal(*reversed(m_axis_tready_list))
# Outputs
s_axis_tready = Signal(bool(0))
m_axis_tdata = Signal(intbv(0)[M_COUNT*DATA_WIDTH:])
m_axis_tkeep = Signal(intbv(0xf)[M_COUNT*KEEP_WIDTH:])
m_axis_tvalid = Signal(intbv(0)[M_COUNT:])
m_axis_tlast = Signal(intbv(0)[M_COUNT:])
m_axis_tid = Signal(intbv(0)[M_COUNT*ID_WIDTH:])
m_axis_tdest = Signal(intbv(0)[M_COUNT*DEST_WIDTH:])
m_axis_tuser = Signal(intbv(0)[M_COUNT*USER_WIDTH:])
m_axis_tdata_list = [m_axis_tdata((i+1)*DATA_WIDTH, i*DATA_WIDTH) for i in range(M_COUNT)]
m_axis_tkeep_list = [m_axis_tkeep((i+1)*KEEP_WIDTH, i*KEEP_WIDTH) for i in range(M_COUNT)]
m_axis_tvalid_list = [m_axis_tvalid(i) for i in range(M_COUNT)]
m_axis_tlast_list = [m_axis_tlast(i) for i in range(M_COUNT)]
m_axis_tid_list = [m_axis_tid((i+1)*ID_WIDTH, i*ID_WIDTH) for i in range(M_COUNT)]
m_axis_tdest_list = [m_axis_tdest((i+1)*DEST_WIDTH, i*DEST_WIDTH) for i in range(M_COUNT)]
m_axis_tuser_list = [m_axis_tuser((i+1)*USER_WIDTH, i*USER_WIDTH) for i in range(M_COUNT)]
# sources and sinks
source_pause = Signal(bool(0))
sink_pause_list = []
sink_list = []
sink_logic_list = []
source = axis_ep.AXIStreamSource()
source_logic = source.create_logic(
clk,
rst,
tdata=s_axis_tdata,
tkeep=s_axis_tkeep,
tvalid=s_axis_tvalid,
tready=s_axis_tready,
tlast=s_axis_tlast,
tid=s_axis_tid,
tdest=s_axis_tdest,
tuser=s_axis_tuser,
pause=source_pause,
name='source'
)
for k in range(M_COUNT):
s = axis_ep.AXIStreamSink()
p = Signal(bool(0))
sink_list.append(s)
sink_pause_list.append(p)
sink_logic_list.append(s.create_logic(
clk,
rst,
tdata=m_axis_tdata_list[k],
tkeep=m_axis_tkeep_list[k],
tvalid=m_axis_tvalid_list[k],
tready=m_axis_tready_list[k],
tlast=m_axis_tlast_list[k],
tid=m_axis_tid_list[k],
tdest=m_axis_tdest_list[k],
tuser=m_axis_tuser_list[k],
pause=p,
name='sink_%d' % k
))
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
s_axis_tdata=s_axis_tdata,
s_axis_tkeep=s_axis_tkeep,
s_axis_tvalid=s_axis_tvalid,
s_axis_tready=s_axis_tready,
s_axis_tlast=s_axis_tlast,
s_axis_tid=s_axis_tid,
s_axis_tdest=s_axis_tdest,
s_axis_tuser=s_axis_tuser,
m_axis_tdata=m_axis_tdata,
m_axis_tkeep=m_axis_tkeep,
m_axis_tvalid=m_axis_tvalid,
m_axis_tready=m_axis_tready,
m_axis_tlast=m_axis_tlast,
m_axis_tid=m_axis_tid,
m_axis_tdest=m_axis_tdest,
m_axis_tuser=m_axis_tuser
)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
yield clk.posedge
print("test 1: test packet")
current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=1
)
source.send(test_frame)
for sink in sink_list:
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 2: longer packet")
current_test.next = 2
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)),
id=1
)
source.send(test_frame)
for sink in sink_list:
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 3: test packet with pauses")
current_test.next = 3
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=3,
dest=1
)
source.send(test_frame)
yield clk.posedge
yield delay(64)
yield clk.posedge
source_pause.next = True
yield delay(32)
yield clk.posedge
source_pause.next = False
yield delay(64)
yield clk.posedge
for k in range(M_COUNT):
sink_pause_list[k].next = True
yield delay(32)
yield clk.posedge
for k in range(M_COUNT):
sink_pause_list[k].next = False
for sink in sink_list:
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 4: back-to-back packets")
current_test.next = 4
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=4,
dest=1
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=4,
dest=2
)
source.send(test_frame1)
source.send(test_frame2)
for sink in sink_list:
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame1
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 5: alternate pause source")
current_test.next = 5
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=1
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=2
)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while s_axis_tvalid or m_axis_tvalid:
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
source_pause.next = True
yield clk.posedge
source_pause.next = False
for sink in sink_list:
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame1
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 6: alternate pause sink")
current_test.next = 6
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=6,
dest=1
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=6,
dest=2
)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while s_axis_tvalid or m_axis_tvalid:
for k in range(M_COUNT):
sink_pause_list[k].next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
for k in range(M_COUNT):
sink_pause_list[k].next = False
yield clk.posedge
for sink in sink_list:
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame1
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 7: alternate pause individual sinks")
current_test.next = 7
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=7,
dest=1
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=7,
dest=2
)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while s_axis_tvalid or m_axis_tvalid:
for pause in sink_pause_list:
pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
pause.next = False
yield clk.posedge
for sink in sink_list:
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame1
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 8: alternate un-pause individual sinks")
current_test.next = 8
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=8,
dest=1
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=8,
dest=2
)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
for pause in sink_pause_list:
pause.next = True
while s_axis_tvalid or m_axis_tvalid:
for pause in sink_pause_list:
yield clk.posedge
yield clk.posedge
yield clk.posedge
pause.next = False
yield clk.posedge
pause.next = True
for pause in sink_pause_list:
pause.next = False
for sink in sink_list:
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame1
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 9: tuser assert")
current_test.next = 9
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=9,
dest=1,
last_cycle_user=1
)
source.send(test_frame)
for sink in sink_list:
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame
assert rx_frame.last_cycle_user
yield delay(100)
raise StopSimulation
return instances()
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))
sim = Simulation(bench())
sim.run()
if __name__ == '__main__':
print("Running test...")
test_bench()

140
lib/axis/tb/test_axis_broadcast_4.v Normal file
View File

@ -0,0 +1,140 @@
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_broadcast
*/
module test_axis_broadcast_4;
// Parameters
parameter M_COUNT = 4;
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg [M_COUNT-1:0] m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [M_COUNT*DATA_WIDTH-1:0] m_axis_tdata;
wire [M_COUNT*KEEP_WIDTH-1:0] m_axis_tkeep;
wire [M_COUNT-1:0] m_axis_tvalid;
wire [M_COUNT-1:0] m_axis_tlast;
wire [M_COUNT*ID_WIDTH-1:0] m_axis_tid;
wire [M_COUNT*DEST_WIDTH-1:0] m_axis_tdest;
wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_axis_tdata,
s_axis_tkeep,
s_axis_tvalid,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tready
);
$to_myhdl(
s_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tvalid,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser
);
// dump file
$dumpfile("test_axis_broadcast_4.lxt");
$dumpvars(0, test_axis_broadcast_4);
end
axis_broadcast #(
.M_COUNT(M_COUNT),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI outputs
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser)
);
endmodule

7
lib/axis/tb/test_axis_cobs_decode.py
View File

@ -77,7 +77,6 @@ def cobs_decode(block):
block = bytearray(block)
dec = bytearray()
it = iter(bytearray(block))
code = 0
i = 0
@ -202,12 +201,14 @@ def bench():
i = max(0, i-1)
if s_axis_tvalid or m_axis_tvalid or not source.empty():
i = 2
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
source_pause.next = True
yield clk.posedge
source_pause.next = False
def wait_pause_sink():
i = 2

7
lib/axis/tb/test_axis_cobs_encode.py
View File

@ -78,7 +78,6 @@ def cobs_decode(block):
block = bytearray(block)
dec = bytearray()
it = iter(bytearray(block))
code = 0
i = 0
@ -203,12 +202,14 @@ def bench():
i = max(0, i-1)
if s_axis_tvalid or m_axis_tvalid or not source.empty():
i = 2
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
source_pause.next = True
yield clk.posedge
source_pause.next = False
def wait_pause_sink():
i = 2

7
lib/axis/tb/test_axis_cobs_encode_zero_frame.py
View File

@ -78,7 +78,6 @@ def cobs_decode(block):
block = bytearray(block)
dec = bytearray()
it = iter(bytearray(block))
code = 0
i = 0
@ -204,12 +203,14 @@ def bench():
i = max(0, i-1)
if s_axis_tvalid or m_axis_tvalid or not source.empty():
i = 2
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
source_pause.next = True
yield clk.posedge
source_pause.next = False
def wait_pause_sink():
i = 2

24
lib/axis/tb/test_axis_demux_4.py
View File

@ -322,7 +322,7 @@ def bench():
yield delay(100)
yield clk.posedge
print("test 5: alterate pause source")
print("test 5: alternate pause source")
current_test.next = 5
select.next = 1
@ -349,13 +349,15 @@ def bench():
yield clk.posedge
while s_axis_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
select.next = 2
yield clk.posedge
source_pause.next = False
yield clk.posedge
select.next = 2
source_pause.next = True
yield clk.posedge
source_pause.next = False
yield sink_list[1].wait()
rx_frame = sink_list[1].recv()
@ -370,7 +372,7 @@ def bench():
yield delay(100)
yield clk.posedge
print("test 6: alterate pause sink")
print("test 6: alternate pause sink")
current_test.next = 6
select.next = 1
@ -397,17 +399,13 @@ def bench():
yield clk.posedge
while s_axis_tvalid:
sink_pause_list[0].next = True
sink_pause_list[1].next = True
sink_pause_list[2].next = True
sink_pause_list[3].next = True
for k in range(M_COUNT):
sink_pause_list[k].next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause_list[0].next = False
sink_pause_list[1].next = False
sink_pause_list[2].next = False
sink_pause_list[3].next = False
for k in range(M_COUNT):
sink_pause_list[k].next = False
yield clk.posedge
select.next = 2

24
lib/axis/tb/test_axis_demux_4_64.py
View File

@ -322,7 +322,7 @@ def bench():
yield delay(100)
yield clk.posedge
print("test 5: alterate pause source")
print("test 5: alternate pause source")
current_test.next = 5
select.next = 1
@ -349,13 +349,15 @@ def bench():
yield clk.posedge
while s_axis_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
select.next = 2
yield clk.posedge
source_pause.next = False
yield clk.posedge
select.next = 2
source_pause.next = True
yield clk.posedge
source_pause.next = False
yield sink_list[1].wait()
rx_frame = sink_list[1].recv()
@ -370,7 +372,7 @@ def bench():
yield delay(100)
yield clk.posedge
print("test 6: alterate pause sink")
print("test 6: alternate pause sink")
current_test.next = 6
select.next = 1
@ -397,17 +399,13 @@ def bench():
yield clk.posedge
while s_axis_tvalid:
sink_pause_list[0].next = True
sink_pause_list[1].next = True
sink_pause_list[2].next = True
sink_pause_list[3].next = True
for k in range(M_COUNT):
sink_pause_list[k].next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause_list[0].next = False
sink_pause_list[1].next = False
sink_pause_list[2].next = False
sink_pause_list[3].next = False
for k in range(M_COUNT):
sink_pause_list[k].next = False
yield clk.posedge
select.next = 2

6
lib/axis/tb/test_axis_fifo.py
View File

@ -309,12 +309,14 @@ def bench():
yield clk.posedge
while s_axis_tvalid or m_axis_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
source_pause.next = True
yield clk.posedge
source_pause.next = False
yield sink.wait()
rx_frame = sink.recv()

6
lib/axis/tb/test_axis_fifo_64.py
View File

@ -309,12 +309,14 @@ def bench():
yield clk.posedge
while s_axis_tvalid or m_axis_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
source_pause.next = True
yield clk.posedge
source_pause.next = False
yield sink.wait()
rx_frame = sink.recv()

6
lib/axis/tb/test_axis_frame_fifo.py
View File

@ -365,12 +365,14 @@ def bench():
yield clk.posedge
while s_axis_tvalid or m_axis_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
source_pause.next = True
yield clk.posedge
source_pause.next = False
yield sink.wait()
rx_frame = sink.recv()

6
lib/axis/tb/test_axis_frame_fifo_64.py
View File

@ -365,12 +365,14 @@ def bench():
yield clk.posedge
while s_axis_tvalid or m_axis_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
source_pause.next = True
yield clk.posedge
source_pause.next = False
yield sink.wait()
rx_frame = sink.recv()

15
lib/axis/tb/test_axis_frame_join_4.py
View File

@ -292,19 +292,18 @@ def bench():
yield clk.posedge
while s_axis_tvalid or m_axis_tvalid:
source_pause_list[0].next = True
source_pause_list[1].next = True
source_pause_list[2].next = True
source_pause_list[3].next = True
yield clk.posedge
yield clk.posedge
for k in range(S_COUNT):
source_pause_list[k].next = False
yield clk.posedge
source_pause_list[0].next = False
source_pause_list[1].next = False
source_pause_list[2].next = False
source_pause_list[3].next = False
for k in range(S_COUNT):
source_pause_list[k].next = True
yield clk.posedge
for k in range(S_COUNT):
source_pause_list[k].next = False
yield sink.wait()
rx_frame = sink.recv()

418
lib/axis/tb/test_axis_frame_len_64.py Executable file
View File

@ -0,0 +1,418 @@
#!/usr/bin/env python
"""
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
"""
from myhdl import *
import os
import axis_ep
module = 'axis_frame_len'
testbench = 'test_%s_64' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
DATA_WIDTH = 64
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8)
LEN_WIDTH = 16
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
monitor_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
monitor_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
monitor_axis_tvalid = Signal(bool(0))
monitor_axis_tready = Signal(bool(0))
monitor_axis_tlast = Signal(bool(0))
# Outputs
frame_len = Signal(intbv(0)[LEN_WIDTH:])
frame_len_valid = Signal(bool(0))
# sources and sinks
source_pause = Signal(bool(0))
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource()
source_logic = source.create_logic(
clk,
rst,
tdata=monitor_axis_tdata,
tkeep=monitor_axis_tkeep,
tvalid=monitor_axis_tvalid,
tready=monitor_axis_tready,
tlast=monitor_axis_tlast,
pause=source_pause,
name='source'
)
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
clk,
rst,
tdata=monitor_axis_tdata,
tkeep=monitor_axis_tkeep,
tvalid=monitor_axis_tvalid,
tready=monitor_axis_tready,
tlast=monitor_axis_tlast,
pause=sink_pause,
name='sink'
)
frame_len_sink = axis_ep.AXIStreamSink()
frame_len_sink_logic = frame_len_sink.create_logic(
clk,
rst,
tdata=frame_len,
tvalid=frame_len_valid,
name='frame_len_sink'
)
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
monitor_axis_tkeep=monitor_axis_tkeep,
monitor_axis_tvalid=monitor_axis_tvalid,
monitor_axis_tready=monitor_axis_tready,
monitor_axis_tlast=monitor_axis_tlast,
frame_len=frame_len,
frame_len_valid=frame_len_valid
)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
print("test 1: test packet")
current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
source.send(test_frame)
yield clk.posedge
while monitor_axis_tvalid:
yield clk.posedge
yield sink.wait()
f = sink.recv()
yield frame_len_sink.wait()
l = frame_len_sink.recv()
assert len(f.data) == l.data[0]
yield delay(100)
yield clk.posedge
print("test 4: longer packet")
current_test.next = 4
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256))
)
source.send(test_frame)
yield clk.posedge
while monitor_axis_tvalid:
yield clk.posedge
yield sink.wait()
f = sink.recv()
yield frame_len_sink.wait()
l = frame_len_sink.recv()
assert len(f.data) == l.data[0]
yield delay(100)
yield clk.posedge
print("test 5: test packet with pauses")
current_test.next = 5
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256))
)
source.send(test_frame)
yield clk.posedge
yield delay(64)
yield clk.posedge
source_pause.next = True
yield delay(32)
yield clk.posedge
source_pause.next = False
yield delay(64)
yield clk.posedge
sink_pause.next = True
yield delay(32)
yield clk.posedge
sink_pause.next = False
while monitor_axis_tvalid:
yield clk.posedge
yield sink.wait()
f = sink.recv()
yield frame_len_sink.wait()
l = frame_len_sink.recv()
assert len(f.data) == l.data[0]
yield delay(100)
yield clk.posedge
print("test 6: back-to-back packets")
current_test.next = 6
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while monitor_axis_tvalid:
yield clk.posedge
yield sink.wait()
f = sink.recv()
yield frame_len_sink.wait()
l = frame_len_sink.recv()
assert len(f.data) == l.data[0]
yield sink.wait()
f = sink.recv()
yield frame_len_sink.wait()
l = frame_len_sink.recv()
assert len(f.data) == l.data[0]
yield delay(100)
yield clk.posedge
print("test 7: alternate pause source")
current_test.next = 7
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while monitor_axis_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
yield sink.wait()
f = sink.recv()
yield frame_len_sink.wait()
l = frame_len_sink.recv()
assert len(f.data) == l.data[0]
yield sink.wait()
f = sink.recv()
yield frame_len_sink.wait()
l = frame_len_sink.recv()
assert len(f.data) == l.data[0]
yield delay(100)
yield clk.posedge
print("test 8: alternate pause sink")
current_test.next = 8
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while monitor_axis_tvalid:
sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = False
yield clk.posedge
yield sink.wait()
f = sink.recv()
yield frame_len_sink.wait()
l = frame_len_sink.recv()
assert len(f.data) == l.data[0]
yield sink.wait()
f = sink.recv()
yield frame_len_sink.wait()
l = frame_len_sink.recv()
assert len(f.data) == l.data[0]
yield delay(100)
yield clk.posedge
print("test 9: various length packets")
current_test.next = 9
lens = [32, 48, 96, 128, 256]
test_frame = []
for i in lens:
test_frame.append(axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(i)))
)
for f in test_frame:
source.send(f)
yield clk.posedge
while monitor_axis_tvalid:
yield clk.posedge
for i in lens:
yield sink.wait()
f = sink.recv()
yield frame_len_sink.wait()
l = frame_len_sink.recv()
assert len(f.data) == l.data[0]
yield delay(100)
raise StopSimulation
return instances()
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))
sim = Simulation(bench())
sim.run()
if __name__ == '__main__':
print("Running test...")
test_bench()

94
lib/axis/tb/test_axis_frame_len_64.v Normal file
View File

@ -0,0 +1,94 @@
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_frame_len
*/
module test_axis_frame_len_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter LEN_WIDTH = 16;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [KEEP_WIDTH-1:0] monitor_axis_tkeep = 0;
reg monitor_axis_tvalid = 0;
reg monitor_axis_tready = 0;
reg monitor_axis_tlast = 0;
// Outputs
wire [LEN_WIDTH-1:0] frame_len;
wire frame_len_valid;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
monitor_axis_tkeep,
monitor_axis_tvalid,
monitor_axis_tready,
monitor_axis_tlast
);
$to_myhdl(
frame_len,
frame_len_valid
);
// dump file
$dumpfile("test_axis_frame_len_64.lxt");
$dumpvars(0, test_axis_frame_len_64);
end
axis_frame_len #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LEN_WIDTH(LEN_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
// AXI monitor
.monitor_axis_tkeep(monitor_axis_tkeep),
.monitor_axis_tvalid(monitor_axis_tvalid),
.monitor_axis_tready(monitor_axis_tready),
.monitor_axis_tlast(monitor_axis_tlast),
// Status
.frame_len(frame_len),
.frame_len_valid(frame_len_valid)
);
endmodule

420
lib/axis/tb/test_axis_frame_len_8.py Executable file
View File

@ -0,0 +1,420 @@
#!/usr/bin/env python
"""
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
"""
from myhdl import *
import os
import axis_ep
module = 'axis_frame_len'
testbench = 'test_%s_8' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
DATA_WIDTH = 8
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8)
LEN_WIDTH = 16
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
monitor_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
monitor_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
monitor_axis_tvalid = Signal(bool(0))
monitor_axis_tready = Signal(bool(0))
monitor_axis_tlast = Signal(bool(0))
# Outputs
frame_len = Signal(intbv(0)[LEN_WIDTH:])
frame_len_valid = Signal(bool(0))
# sources and sinks
source_pause = Signal(bool(0))
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource()
source_logic = source.create_logic(
clk,
rst,
tdata=monitor_axis_tdata,
tkeep=monitor_axis_tkeep,
tvalid=monitor_axis_tvalid,
tready=monitor_axis_tready,
tlast=monitor_axis_tlast,
pause=source_pause,
name='source'
)
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
clk,
rst,
tdata=monitor_axis_tdata,
tkeep=monitor_axis_tkeep,
tvalid=monitor_axis_tvalid,
tready=monitor_axis_tready,
tlast=monitor_axis_tlast,
pause=sink_pause,
name='sink'
)
frame_len_sink = axis_ep.AXIStreamSink()
frame_len_sink_logic = frame_len_sink.create_logic(
clk,
rst,
tdata=frame_len,
tvalid=frame_len_valid,
name='frame_len_sink'
)
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
monitor_axis_tkeep=monitor_axis_tkeep,
monitor_axis_tvalid=monitor_axis_tvalid,
monitor_axis_tready=monitor_axis_tready,
monitor_axis_tlast=monitor_axis_tlast,
frame_len=frame_len,
frame_len_valid=frame_len_valid
)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
print("test 1: test packet")
current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
source.send(test_frame)
yield clk.posedge
while monitor_axis_tvalid:
yield clk.posedge
yield sink.wait()
f = sink.recv()
yield frame_len_sink.wait()
l = frame_len_sink.recv()
assert len(f.data) == l.data[0]
yield delay(100)
yield clk.posedge
print("test 4: longer packet")
current_test.next = 4
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256))
)
source.send(test_frame)
yield clk.posedge
while monitor_axis_tvalid:
yield clk.posedge
yield sink.wait()
f = sink.recv()
yield frame_len_sink.wait()
l = frame_len_sink.recv()
assert len(f.data) == l.data[0]
yield delay(100)
yield clk.posedge
print("test 5: test packet with pauses")
current_test.next = 5
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256))
)
source.send(test_frame)
yield clk.posedge
yield delay(64)
yield clk.posedge
source_pause.next = True
yield delay(32)
yield clk.posedge
source_pause.next = False
yield delay(64)
yield clk.posedge
sink_pause.next = True
yield delay(32)
yield clk.posedge
sink_pause.next = False
while monitor_axis_tvalid:
yield clk.posedge
yield sink.wait()
f = sink.recv()
yield frame_len_sink.wait()
l = frame_len_sink.recv()
assert len(f.data) == l.data[0]
yield delay(100)
yield clk.posedge
print("test 6: back-to-back packets")
current_test.next = 6
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while monitor_axis_tvalid:
yield clk.posedge
yield sink.wait()
f = sink.recv()
yield frame_len_sink.wait()
l = frame_len_sink.recv()
assert len(f.data) == l.data[0]
yield sink.wait()
f = sink.recv()
yield frame_len_sink.wait()
l = frame_len_sink.recv()
assert len(f.data) == l.data[0]
yield delay(100)
yield clk.posedge
print("test 7: alternate pause source")
current_test.next = 7
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while monitor_axis_tvalid:
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
source_pause.next = True
yield clk.posedge
source_pause.next = False
yield sink.wait()
f = sink.recv()
yield frame_len_sink.wait()
l = frame_len_sink.recv()
assert len(f.data) == l.data[0]
yield sink.wait()
f = sink.recv()
yield frame_len_sink.wait()
l = frame_len_sink.recv()
assert len(f.data) == l.data[0]
yield delay(100)
yield clk.posedge
print("test 8: alternate pause sink")
current_test.next = 8
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while monitor_axis_tvalid:
sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = False
yield clk.posedge
yield sink.wait()
f = sink.recv()
yield frame_len_sink.wait()
l = frame_len_sink.recv()
assert len(f.data) == l.data[0]
yield sink.wait()
f = sink.recv()
yield frame_len_sink.wait()
l = frame_len_sink.recv()
assert len(f.data) == l.data[0]
yield delay(100)
yield clk.posedge
print("test 9: various length packets")
current_test.next = 9
lens = [32, 48, 96, 128, 256]
test_frame = []
for i in lens:
test_frame.append(axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(i)))
)
for f in test_frame:
source.send(f)
yield clk.posedge
while monitor_axis_tvalid:
yield clk.posedge
for i in lens:
yield sink.wait()
f = sink.recv()
yield frame_len_sink.wait()
l = frame_len_sink.recv()
assert len(f.data) == l.data[0]
yield delay(100)
raise StopSimulation
return instances()
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))
sim = Simulation(bench())
sim.run()
if __name__ == '__main__':
print("Running test...")
test_bench()

94
lib/axis/tb/test_axis_frame_len_8.v Normal file
View File

@ -0,0 +1,94 @@
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_frame_len
*/
module test_axis_frame_len_8;
// Parameters
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter LEN_WIDTH = 16;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [KEEP_WIDTH-1:0] monitor_axis_tkeep = 0;
reg monitor_axis_tvalid = 0;
reg monitor_axis_tready = 0;
reg monitor_axis_tlast = 0;
// Outputs
wire [LEN_WIDTH-1:0] frame_len;
wire frame_len_valid;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
monitor_axis_tkeep,
monitor_axis_tvalid,
monitor_axis_tready,
monitor_axis_tlast
);
$to_myhdl(
frame_len,
frame_len_valid
);
// dump file
$dumpfile("test_axis_frame_len_8.lxt");
$dumpvars(0, test_axis_frame_len_8);
end
axis_frame_len #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LEN_WIDTH(LEN_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
// AXI monitor
.monitor_axis_tkeep(monitor_axis_tkeep),
.monitor_axis_tvalid(monitor_axis_tvalid),
.monitor_axis_tready(monitor_axis_tready),
.monitor_axis_tlast(monitor_axis_tlast),
// Status
.frame_len(frame_len),
.frame_len_valid(frame_len_valid)
);
endmodule

6
lib/axis/tb/test_axis_frame_length_adjust_64.py
View File

@ -185,12 +185,14 @@ def bench():
def wait_pause_source():
while s_axis_tvalid or m_axis_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
source_pause.next = True
yield clk.posedge
source_pause.next = False
def wait_pause_sink():
while s_axis_tvalid or m_axis_tvalid:

6
lib/axis/tb/test_axis_frame_length_adjust_8.py
View File

@ -185,12 +185,14 @@ def bench():
def wait_pause_source():
while s_axis_tvalid or m_axis_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
source_pause.next = True
yield clk.posedge
source_pause.next = False
def wait_pause_sink():
while s_axis_tvalid or m_axis_tvalid:

19
lib/axis/tb/test_axis_mux_4.py
View File

@ -318,7 +318,7 @@ def bench():
yield delay(100)
yield clk.posedge
print("test 5: alterate pause source")
print("test 5: alternate pause source")
current_test.next = 5
select.next = 1
@ -345,20 +345,19 @@ def bench():
yield clk.posedge
while s_axis_tvalid:
source_pause_list[0].next = True
source_pause_list[1].next = True
source_pause_list[2].next = True
source_pause_list[3].next = True
yield clk.posedge
yield clk.posedge
for k in range(S_COUNT):
source_pause_list[k].next = False
yield clk.posedge
source_pause_list[0].next = False
source_pause_list[1].next = False
source_pause_list[2].next = False
source_pause_list[3].next = False
for k in range(S_COUNT):
source_pause_list[k].next = True
yield clk.posedge
select.next = 2
for k in range(S_COUNT):
source_pause_list[k].next = False
yield sink.wait()
rx_frame = sink.recv()
@ -372,7 +371,7 @@ def bench():
yield delay(100)
yield clk.posedge
print("test 6: alterate pause sink")
print("test 6: alternate pause sink")
current_test.next = 6
select.next = 1

19
lib/axis/tb/test_axis_mux_4_64.py
View File

@ -318,7 +318,7 @@ def bench():
yield delay(100)
yield clk.posedge
print("test 5: alterate pause source")
print("test 5: alternate pause source")
current_test.next = 5
select.next = 1
@ -345,20 +345,19 @@ def bench():
yield clk.posedge
while s_axis_tvalid:
source_pause_list[0].next = True
source_pause_list[1].next = True
source_pause_list[2].next = True
source_pause_list[3].next = True
yield clk.posedge
yield clk.posedge
for k in range(S_COUNT):
source_pause_list[k].next = False
yield clk.posedge
source_pause_list[0].next = False
source_pause_list[1].next = False
source_pause_list[2].next = False
source_pause_list[3].next = False
for k in range(S_COUNT):
source_pause_list[k].next = True
yield clk.posedge
select.next = 2
for k in range(S_COUNT):
source_pause_list[k].next = False
yield sink.wait()
rx_frame = sink.recv()
@ -372,7 +371,7 @@ def bench():
yield delay(100)
yield clk.posedge
print("test 6: alterate pause sink")
print("test 6: alternate pause sink")
current_test.next = 6
select.next = 1

6
lib/axis/tb/test_axis_rate_limit.py
View File

@ -349,12 +349,14 @@ def bench():
yield clk.posedge
while s_axis_tvalid or m_axis_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
source_pause.next = True
yield clk.posedge
source_pause.next = False
yield sink.wait()
rx_frame = sink.recv()

6
lib/axis/tb/test_axis_rate_limit_64.py
View File

@ -349,12 +349,14 @@ def bench():
yield clk.posedge
while s_axis_tvalid or m_axis_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
source_pause.next = True
yield clk.posedge
source_pause.next = False
yield sink.wait()
rx_frame = sink.recv()

6
lib/axis/tb/test_axis_register.py
View File

@ -304,12 +304,14 @@ def bench():
yield clk.posedge
while s_axis_tvalid or m_axis_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
source_pause.next = True
yield clk.posedge
source_pause.next = False
yield sink.wait()
rx_frame = sink.recv()

6
lib/axis/tb/test_axis_register_64.py
View File

@ -304,12 +304,14 @@ def bench():
yield clk.posedge
while s_axis_tvalid or m_axis_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
source_pause.next = True
yield clk.posedge
source_pause.next = False
yield sink.wait()
rx_frame = sink.recv()

6
lib/axis/tb/test_axis_srl_fifo.py
View File

@ -306,12 +306,14 @@ def bench():
yield clk.posedge
while s_axis_tvalid or m_axis_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
source_pause.next = True
yield clk.posedge
source_pause.next = False
yield sink.wait()
rx_frame = sink.recv()

6
lib/axis/tb/test_axis_srl_fifo_64.py
View File

@ -306,12 +306,14 @@ def bench():
yield clk.posedge
while s_axis_tvalid or m_axis_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
source_pause.next = True
yield clk.posedge
source_pause.next = False
yield sink.wait()
rx_frame = sink.recv()

6
lib/axis/tb/test_axis_srl_register.py
View File

@ -303,12 +303,14 @@ def bench():
yield clk.posedge
while s_axis_tvalid or m_axis_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
source_pause.next = True
yield clk.posedge
source_pause.next = False
yield sink.wait()
rx_frame = sink.recv()

6
lib/axis/tb/test_axis_srl_register_64.py
View File

@ -303,12 +303,14 @@ def bench():
yield clk.posedge
while s_axis_tvalid or m_axis_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
source_pause.next = True
yield clk.posedge
source_pause.next = False
yield sink.wait()
rx_frame = sink.recv()

12
lib/axis/tb/test_axis_stat_counter.py
View File

@ -528,6 +528,13 @@ def bench():
while monitor_axis_tvalid:
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
source_pause.next = True
yield clk.posedge
source_pause.next = False
while m_axis_tvalid:
yield clk.posedge
@ -589,6 +596,11 @@ def bench():
yield clk.posedge
while monitor_axis_tvalid:
monitor_sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
monitor_sink_pause.next = False
yield clk.posedge
while m_axis_tvalid:

27
lib/axis/tb/test_axis_switch_4x4.py
View File

@ -202,32 +202,27 @@ def bench():
def wait_pause_source():
while s_axis_tvalid:
source_pause_list[0].next = True
source_pause_list[1].next = True
source_pause_list[2].next = True
source_pause_list[3].next = True
yield clk.posedge
yield clk.posedge
for k in range(S_COUNT):
source_pause_list[k].next = False
yield clk.posedge
source_pause_list[0].next = False
source_pause_list[1].next = False
source_pause_list[2].next = False
source_pause_list[3].next = False
for k in range(S_COUNT):
source_pause_list[k].next = True
yield clk.posedge
for k in range(S_COUNT):
source_pause_list[k].next = False
def wait_pause_sink():
while s_axis_tvalid:
sink_pause_list[0].next = True
sink_pause_list[1].next = True
sink_pause_list[2].next = True
sink_pause_list[3].next = True
for k in range(M_COUNT):
sink_pause_list[k].next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause_list[0].next = False
sink_pause_list[1].next = False
sink_pause_list[2].next = False
sink_pause_list[3].next = False
for k in range(M_COUNT):
sink_pause_list[k].next = False
yield clk.posedge
@instance

27
lib/axis/tb/test_axis_switch_4x4_64.py
View File

@ -202,32 +202,27 @@ def bench():
def wait_pause_source():
while s_axis_tvalid:
source_pause_list[0].next = True
source_pause_list[1].next = True
source_pause_list[2].next = True
source_pause_list[3].next = True
yield clk.posedge
yield clk.posedge
for k in range(S_COUNT):
source_pause_list[k].next = False
yield clk.posedge
source_pause_list[0].next = False
source_pause_list[1].next = False
source_pause_list[2].next = False
source_pause_list[3].next = False
for k in range(S_COUNT):
source_pause_list[k].next = True
yield clk.posedge
for k in range(S_COUNT):
source_pause_list[k].next = False
def wait_pause_sink():
while s_axis_tvalid:
sink_pause_list[0].next = True
sink_pause_list[1].next = True
sink_pause_list[2].next = True
sink_pause_list[3].next = True
for k in range(M_COUNT):
sink_pause_list[k].next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause_list[0].next = False
sink_pause_list[1].next = False
sink_pause_list[2].next = False
sink_pause_list[3].next = False
for k in range(M_COUNT):
sink_pause_list[k].next = False
yield clk.posedge
@instance

6
lib/axis/tb/test_axis_tap.py
View File

@ -329,12 +329,14 @@ def bench():
yield clk.posedge
while tap_axis_tvalid or m_axis_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
source_pause.next = True
yield clk.posedge
source_pause.next = False
yield sink.wait()
rx_frame = sink.recv()

6
lib/axis/tb/test_axis_tap_64.py
View File

@ -329,12 +329,14 @@ def bench():
yield clk.posedge
while tap_axis_tvalid or m_axis_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
source_pause.next = True
yield clk.posedge
source_pause.next = False
yield sink.wait()
rx_frame = sink.recv()