FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-28 07:03:08 +08:00
Code Issues Projects Releases Wiki Activity

Whitespace fixes

Browse Source
This commit is contained in:
Alex Forencich 2017-11-21 00:18:09 -08:00
parent b00eaf4d3c
commit 4ec4c901e8
3 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
rtl/arbiter.v
View File

@ -42,7 +42,7 @@ module arbiter #
( (
input wire clk, input wire clk,
input wire rst, input wire rst,
input wire [PORTS-1:0] request, input wire [PORTS-1:0] request,
input wire [PORTS-1:0] acknowledge, input wire [PORTS-1:0] acknowledge,

4
rtl/axis_ll_bridge.v
View File

@ -36,7 +36,7 @@ module axis_ll_bridge #
( (
input wire clk, input wire clk,
input wire rst, input wire rst,
/* /*
* AXI input * AXI input
*/ */
@ -44,7 +44,7 @@ module axis_ll_bridge #
input wire axis_tvalid, input wire axis_tvalid,
output wire axis_tready, output wire axis_tready,
input wire axis_tlast, input wire axis_tlast,
/* /*
* LocalLink output * LocalLink output
*/ */

4
rtl/ll_axis_bridge.v
View File

@ -36,7 +36,7 @@ module ll_axis_bridge #
( (
input wire clk, input wire clk,
input wire rst, input wire rst,
/* /*
* LocalLink input * LocalLink input
*/ */
@ -45,7 +45,7 @@ module ll_axis_bridge #
input wire ll_eof_in_n, input wire ll_eof_in_n,
input wire ll_src_rdy_in_n, input wire ll_src_rdy_in_n,
output wire ll_dst_rdy_out_n, output wire ll_dst_rdy_out_n,
/* /*
* AXI output * AXI output
*/ */