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https://github.com/alexforencich/verilog-ethernet.git
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream SRL register
This commit is contained in:
Alex Forencich
parent
b0d7820f5b
commit
4ef4ef2622
@ -31,7 +31,16 @@ THE SOFTWARE.
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*/
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module axis_srl_register #
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(
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parameter DATA_WIDTH = 8
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parameter DATA_WIDTH = 8,
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parameter KEEP_ENABLE = (DATA_WIDTH>8),
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parameter KEEP_WIDTH = (DATA_WIDTH/8),
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parameter LAST_ENABLE = 1,
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parameter ID_ENABLE = 0,
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parameter ID_WIDTH = 8,
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parameter DEST_ENABLE = 0,
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parameter DEST_WIDTH = 8,
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parameter USER_ENABLE = 1,
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parameter USER_WIDTH = 1
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)
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(
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input wire clk,
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@ -41,30 +50,63 @@ module axis_srl_register #
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* AXI input
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*/
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input wire [DATA_WIDTH-1:0] input_axis_tdata,
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input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
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input wire input_axis_tvalid,
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output wire input_axis_tready,
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input wire input_axis_tlast,
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input wire input_axis_tuser,
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input wire [ID_WIDTH-1:0] input_axis_tid,
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input wire [DEST_WIDTH-1:0] input_axis_tdest,
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input wire [USER_WIDTH-1:0] input_axis_tuser,
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/*
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* AXI output
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*/
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output wire [DATA_WIDTH-1:0] output_axis_tdata,
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output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
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output wire output_axis_tvalid,
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input wire output_axis_tready,
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output wire output_axis_tlast,
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output wire output_axis_tuser
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output wire [ID_WIDTH-1:0] output_axis_tid,
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output wire [DEST_WIDTH-1:0] output_axis_tdest,
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output wire [USER_WIDTH-1:0] output_axis_tuser
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);
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reg [DATA_WIDTH+2-1:0] data_reg[1:0];
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localparam KEEP_OFFSET = DATA_WIDTH;
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localparam LAST_OFFSET = KEEP_OFFSET + (KEEP_ENABLE ? KEEP_WIDTH : 0);
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localparam ID_OFFSET = LAST_OFFSET + (LAST_ENABLE ? 1 : 0);
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localparam DEST_OFFSET = ID_OFFSET + (ID_ENABLE ? ID_WIDTH : 0);
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localparam USER_OFFSET = DEST_OFFSET + (DEST_ENABLE ? DEST_WIDTH : 0);
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localparam WIDTH = USER_OFFSET + (USER_ENABLE ? USER_WIDTH : 0);
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reg [WIDTH-1:0] data_reg[1:0];
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reg valid_reg[1:0];
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reg ptr_reg = 0;
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reg full_reg = 0;
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assign {output_axis_tlast, output_axis_tuser, output_axis_tdata} = data_reg[ptr_reg];
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wire [WIDTH-1:0] input_axis;
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wire [WIDTH-1:0] output_axis = data_reg[ptr_reg];
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assign input_axis_tready = ~full_reg;
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generate
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assign input_axis[DATA_WIDTH-1:0] = input_axis_tdata;
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if (KEEP_ENABLE) assign input_axis[KEEP_OFFSET +: KEEP_WIDTH] = input_axis_tkeep;
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if (LAST_ENABLE) assign input_axis[LAST_OFFSET] = input_axis_tlast;
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if (ID_ENABLE) assign input_axis[ID_OFFSET +: ID_WIDTH] = input_axis_tid;
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if (DEST_ENABLE) assign input_axis[DEST_OFFSET +: DEST_WIDTH] = input_axis_tdest;
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if (USER_ENABLE) assign input_axis[USER_OFFSET +: USER_WIDTH] = input_axis_tuser;
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endgenerate
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assign output_axis_tvalid = valid_reg[ptr_reg];
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assign output_axis_tdata = output_axis[DATA_WIDTH-1:0];
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assign output_axis_tkeep = KEEP_ENABLE ? output_axis[KEEP_OFFSET +: KEEP_WIDTH] : {KEEP_WIDTH{1'b1}};
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assign output_axis_tlast = LAST_ENABLE ? output_axis[LAST_OFFSET] : 1'b1;
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assign output_axis_tid = ID_ENABLE ? output_axis[ID_OFFSET +: ID_WIDTH] : {ID_WIDTH{1'b0}};
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assign output_axis_tdest = DEST_ENABLE ? output_axis[DEST_OFFSET +: DEST_WIDTH] : {DEST_WIDTH{1'b0}};
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assign output_axis_tuser = USER_ENABLE ? output_axis[USER_OFFSET +: USER_WIDTH] : {USER_WIDTH{1'b0}};
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integer i;
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initial begin
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@ -84,7 +126,7 @@ always @(posedge clk) begin
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// transfer in if not full
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if (input_axis_tready) begin
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data_reg[0] <= {input_axis_tlast, input_axis_tuser, input_axis_tdata};
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data_reg[0] <= input_axis;
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valid_reg[0] <= input_axis_tvalid;
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for (i = 0; i < 1; i = i + 1) begin
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data_reg[i+1] <= data_reg[i];
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@ -1,105 +0,0 @@
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/*
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Copyright (c) 2014-2017 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4-Stream SRL-based FIFO register (64 bit datapath)
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*/
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module axis_srl_register_64 #
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(
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parameter DATA_WIDTH = 64,
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parameter KEEP_WIDTH = (DATA_WIDTH/8)
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI input
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*/
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input wire [DATA_WIDTH-1:0] input_axis_tdata,
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input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
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input wire input_axis_tvalid,
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output wire input_axis_tready,
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input wire input_axis_tlast,
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input wire input_axis_tuser,
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/*
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* AXI output
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*/
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output wire [DATA_WIDTH-1:0] output_axis_tdata,
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output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
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output wire output_axis_tvalid,
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input wire output_axis_tready,
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output wire output_axis_tlast,
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output wire output_axis_tuser
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);
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reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] data_reg[1:0];
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reg valid_reg[1:0];
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reg ptr_reg = 0;
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reg full_reg = 0;
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assign {output_axis_tlast, output_axis_tuser, output_axis_tkeep, output_axis_tdata} = data_reg[ptr_reg];
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assign input_axis_tready = ~full_reg;
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assign output_axis_tvalid = valid_reg[ptr_reg];
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integer i;
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initial begin
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for (i = 0; i < 2; i = i + 1) begin
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data_reg[i] <= 0;
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valid_reg[i] <= 0;
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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ptr_reg <= 0;
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full_reg <= 0;
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end else begin
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// transfer empty to full
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full_reg <= ~output_axis_tready & output_axis_tvalid;
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// transfer in if not full
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if (input_axis_tready) begin
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data_reg[0] <= {input_axis_tlast, input_axis_tuser, input_axis_tkeep, input_axis_tdata};
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valid_reg[0] <= input_axis_tvalid;
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for (i = 0; i < 1; i = i + 1) begin
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data_reg[i+1] <= data_reg[i];
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valid_reg[i+1] <= valid_reg[i];
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end
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ptr_reg <= valid_reg[0];
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end
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if (output_axis_tready) begin
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ptr_reg <= 0;
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end
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end
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end
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endmodule
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@ -44,24 +44,39 @@ def bench():
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# Parameters
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DATA_WIDTH = 8
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KEEP_ENABLE = (DATA_WIDTH>8)
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KEEP_WIDTH = (DATA_WIDTH/8)
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LAST_ENABLE = 1
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ID_ENABLE = 1
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ID_WIDTH = 8
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DEST_ENABLE = 1
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DEST_WIDTH = 8
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USER_ENABLE = 1
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USER_WIDTH = 1
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# Inputs
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clk = Signal(bool(0))
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rst = Signal(bool(0))
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current_test = Signal(intbv(0)[8:])
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input_axis_tdata = Signal(intbv(0)[8:])
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input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
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input_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
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input_axis_tvalid = Signal(bool(0))
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input_axis_tlast = Signal(bool(0))
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input_axis_tuser = Signal(bool(0))
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input_axis_tid = Signal(intbv(0)[ID_WIDTH:])
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input_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
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input_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
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output_axis_tready = Signal(bool(0))
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# Outputs
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input_axis_tready = Signal(bool(0))
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output_axis_tdata = Signal(intbv(0)[8:])
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output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
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output_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
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output_axis_tvalid = Signal(bool(0))
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output_axis_tlast = Signal(bool(0))
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output_axis_tuser = Signal(bool(0))
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output_axis_tid = Signal(intbv(0)[ID_WIDTH:])
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output_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
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output_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
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# sources and sinks
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source_pause = Signal(bool(0))
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@ -73,9 +88,12 @@ def bench():
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clk,
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rst,
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tdata=input_axis_tdata,
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tkeep=input_axis_tkeep,
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tvalid=input_axis_tvalid,
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tready=input_axis_tready,
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tlast=input_axis_tlast,
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tid=input_axis_tid,
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tdest=input_axis_tdest,
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tuser=input_axis_tuser,
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pause=source_pause,
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name='source'
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@ -87,9 +105,12 @@ def bench():
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clk,
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rst,
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tdata=output_axis_tdata,
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tkeep=output_axis_tkeep,
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tvalid=output_axis_tvalid,
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tready=output_axis_tready,
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tlast=output_axis_tlast,
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tid=output_axis_tid,
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tdest=output_axis_tdest,
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tuser=output_axis_tuser,
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pause=sink_pause,
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name='sink'
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@ -106,15 +127,21 @@ def bench():
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current_test=current_test,
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input_axis_tdata=input_axis_tdata,
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input_axis_tkeep=input_axis_tkeep,
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input_axis_tvalid=input_axis_tvalid,
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input_axis_tready=input_axis_tready,
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input_axis_tlast=input_axis_tlast,
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input_axis_tid=input_axis_tid,
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input_axis_tdest=input_axis_tdest,
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input_axis_tuser=input_axis_tuser,
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output_axis_tdata=output_axis_tdata,
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output_axis_tkeep=output_axis_tkeep,
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output_axis_tvalid=output_axis_tvalid,
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output_axis_tready=output_axis_tready,
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output_axis_tlast=output_axis_tlast,
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output_axis_tid=output_axis_tid,
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output_axis_tdest=output_axis_tdest,
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output_axis_tuser=output_axis_tuser
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)
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@ -139,10 +166,15 @@ def bench():
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print("test 1: test packet")
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current_test.next = 1
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test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
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b'\x5A\x51\x52\x53\x54\x55' +
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b'\x80\x00' +
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b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
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test_frame = axis_ep.AXIStreamFrame(
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b'\xDA\xD1\xD2\xD3\xD4\xD5' +
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b'\x5A\x51\x52\x53\x54\x55' +
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b'\x80\x00' +
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b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
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id=1,
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dest=1
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)
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source.send(test_frame)
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yield clk.posedge
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@ -160,10 +192,15 @@ def bench():
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print("test 2: longer packet")
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current_test.next = 2
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test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
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b'\x5A\x51\x52\x53\x54\x55' +
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b'\x80\x00' +
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bytearray(range(256)))
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test_frame = axis_ep.AXIStreamFrame(
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b'\xDA\xD1\xD2\xD3\xD4\xD5' +
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b'\x5A\x51\x52\x53\x54\x55' +
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b'\x80\x00' +
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bytearray(range(256)),
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id=2,
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dest=1
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)
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source.send(test_frame)
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yield clk.posedge
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@ -179,10 +216,15 @@ def bench():
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print("test 3: test packet with pauses")
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current_test.next = 3
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test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
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b'\x5A\x51\x52\x53\x54\x55' +
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b'\x80\x00' +
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b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
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test_frame = axis_ep.AXIStreamFrame(
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b'\xDA\xD1\xD2\xD3\xD4\xD5' +
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b'\x5A\x51\x52\x53\x54\x55' +
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b'\x80\x00' +
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b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
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id=3,
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dest=1
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)
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source.send(test_frame)
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yield clk.posedge
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@ -214,14 +256,23 @@ def bench():
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print("test 4: back-to-back packets")
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current_test.next = 4
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test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
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b'\x5A\x51\x52\x53\x54\x55' +
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b'\x80\x00' +
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b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
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test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
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b'\x5A\x51\x52\x53\x54\x55' +
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b'\x80\x00' +
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b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
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test_frame1 = axis_ep.AXIStreamFrame(
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b'\xDA\xD1\xD2\xD3\xD4\xD5' +
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b'\x5A\x51\x52\x53\x54\x55' +
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b'\x80\x00' +
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b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
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id=4,
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dest=1
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)
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test_frame2 = axis_ep.AXIStreamFrame(
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b'\xDA\xD1\xD2\xD3\xD4\xD5' +
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b'\x5A\x51\x52\x53\x54\x55' +
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b'\x80\x00' +
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b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
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id=4,
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dest=2
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)
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source.send(test_frame1)
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source.send(test_frame2)
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yield clk.posedge
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@ -246,14 +297,23 @@ def bench():
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print("test 5: alternate pause source")
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current_test.next = 5
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test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
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b'\x5A\x51\x52\x53\x54\x55' +
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b'\x80\x00' +
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b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
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test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
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b'\x5A\x51\x52\x53\x54\x55' +
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b'\x80\x00' +
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b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
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test_frame1 = axis_ep.AXIStreamFrame(
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b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
|
||||
id=5,
|
||||
dest=1
|
||||
)
|
||||
test_frame2 = axis_ep.AXIStreamFrame(
|
||||
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
|
||||
id=5,
|
||||
dest=2
|
||||
)
|
||||
|
||||
source.send(test_frame1)
|
||||
source.send(test_frame2)
|
||||
yield clk.posedge
|
||||
@ -283,14 +343,23 @@ def bench():
|
||||
print("test 6: alternate pause sink")
|
||||
current_test.next = 6
|
||||
|
||||
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame1 = axis_ep.AXIStreamFrame(
|
||||
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
|
||||
id=6,
|
||||
dest=1
|
||||
)
|
||||
test_frame2 = axis_ep.AXIStreamFrame(
|
||||
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
|
||||
id=6,
|
||||
dest=2
|
||||
)
|
||||
|
||||
source.send(test_frame1)
|
||||
source.send(test_frame2)
|
||||
yield clk.posedge
|
||||
@ -320,11 +389,16 @@ def bench():
|
||||
print("test 7: tuser assert")
|
||||
current_test.next = 7
|
||||
|
||||
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame.user = 1
|
||||
test_frame = axis_ep.AXIStreamFrame(
|
||||
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
|
||||
id=7,
|
||||
dest=1,
|
||||
last_cycle_user=1
|
||||
)
|
||||
|
||||
source.send(test_frame)
|
||||
yield clk.posedge
|
||||
|
||||
@ -335,7 +409,7 @@ def bench():
|
||||
rx_frame = sink.recv()
|
||||
|
||||
assert rx_frame == test_frame
|
||||
assert rx_frame.user[-1]
|
||||
assert rx_frame.last_cycle_user
|
||||
|
||||
yield delay(100)
|
||||
|
||||
|
||||
@ -33,6 +33,15 @@ module test_axis_srl_register;
|
||||
|
||||
// Parameters
|
||||
parameter DATA_WIDTH = 8;
|
||||
parameter KEEP_ENABLE = (DATA_WIDTH>8);
|
||||
parameter KEEP_WIDTH = (DATA_WIDTH/8);
|
||||
parameter LAST_ENABLE = 1;
|
||||
parameter ID_ENABLE = 1;
|
||||
parameter ID_WIDTH = 8;
|
||||
parameter DEST_ENABLE = 1;
|
||||
parameter DEST_WIDTH = 8;
|
||||
parameter USER_ENABLE = 1;
|
||||
parameter USER_WIDTH = 1;
|
||||
|
||||
// Inputs
|
||||
reg clk = 0;
|
||||
@ -40,17 +49,23 @@ reg rst = 0;
|
||||
reg [7:0] current_test = 0;
|
||||
|
||||
reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
|
||||
reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0;
|
||||
reg input_axis_tvalid = 0;
|
||||
reg input_axis_tlast = 0;
|
||||
reg input_axis_tuser = 0;
|
||||
reg [ID_WIDTH-1:0] input_axis_tid = 0;
|
||||
reg [DEST_WIDTH-1:0] input_axis_tdest = 0;
|
||||
reg [USER_WIDTH-1:0] input_axis_tuser = 0;
|
||||
reg output_axis_tready = 0;
|
||||
|
||||
// Outputs
|
||||
wire input_axis_tready;
|
||||
wire [DATA_WIDTH-1:0] output_axis_tdata;
|
||||
wire [KEEP_WIDTH-1:0] output_axis_tkeep;
|
||||
wire output_axis_tvalid;
|
||||
wire output_axis_tlast;
|
||||
wire output_axis_tuser;
|
||||
wire [ID_WIDTH-1:0] output_axis_tid;
|
||||
wire [DEST_WIDTH-1:0] output_axis_tdest;
|
||||
wire [USER_WIDTH-1:0] output_axis_tuser;
|
||||
|
||||
initial begin
|
||||
// myhdl integration
|
||||
@ -59,16 +74,22 @@ initial begin
|
||||
rst,
|
||||
current_test,
|
||||
input_axis_tdata,
|
||||
input_axis_tkeep,
|
||||
input_axis_tvalid,
|
||||
input_axis_tlast,
|
||||
input_axis_tid,
|
||||
input_axis_tdest,
|
||||
input_axis_tuser,
|
||||
output_axis_tready
|
||||
);
|
||||
$to_myhdl(
|
||||
input_axis_tready,
|
||||
output_axis_tdata,
|
||||
output_axis_tkeep,
|
||||
output_axis_tvalid,
|
||||
output_axis_tlast,
|
||||
output_axis_tid,
|
||||
output_axis_tdest,
|
||||
output_axis_tuser
|
||||
);
|
||||
|
||||
@ -78,22 +99,37 @@ initial begin
|
||||
end
|
||||
|
||||
axis_srl_register #(
|
||||
.DATA_WIDTH(DATA_WIDTH)
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.KEEP_ENABLE(KEEP_ENABLE),
|
||||
.KEEP_WIDTH(KEEP_WIDTH),
|
||||
.LAST_ENABLE(LAST_ENABLE),
|
||||
.ID_ENABLE(ID_ENABLE),
|
||||
.ID_WIDTH(ID_WIDTH),
|
||||
.DEST_ENABLE(DEST_ENABLE),
|
||||
.DEST_WIDTH(DEST_WIDTH),
|
||||
.USER_ENABLE(USER_ENABLE),
|
||||
.USER_WIDTH(USER_WIDTH)
|
||||
)
|
||||
UUT (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
// axi input
|
||||
// AXI input
|
||||
.input_axis_tdata(input_axis_tdata),
|
||||
.input_axis_tkeep(input_axis_tkeep),
|
||||
.input_axis_tvalid(input_axis_tvalid),
|
||||
.input_axis_tready(input_axis_tready),
|
||||
.input_axis_tlast(input_axis_tlast),
|
||||
.input_axis_tid(input_axis_tid),
|
||||
.input_axis_tdest(input_axis_tdest),
|
||||
.input_axis_tuser(input_axis_tuser),
|
||||
// axi output
|
||||
// AXI output
|
||||
.output_axis_tdata(output_axis_tdata),
|
||||
.output_axis_tkeep(output_axis_tkeep),
|
||||
.output_axis_tvalid(output_axis_tvalid),
|
||||
.output_axis_tready(output_axis_tready),
|
||||
.output_axis_tlast(output_axis_tlast),
|
||||
.output_axis_tid(output_axis_tid),
|
||||
.output_axis_tdest(output_axis_tdest),
|
||||
.output_axis_tuser(output_axis_tuser)
|
||||
);
|
||||
|
||||
|
||||
@ -28,8 +28,8 @@ import os
|
||||
|
||||
import axis_ep
|
||||
|
||||
module = 'axis_srl_register_64'
|
||||
testbench = 'test_%s' % module
|
||||
module = 'axis_srl_register'
|
||||
testbench = 'test_%s_64' % module
|
||||
|
||||
srcs = []
|
||||
|
||||
@ -44,27 +44,39 @@ def bench():
|
||||
|
||||
# Parameters
|
||||
DATA_WIDTH = 64
|
||||
KEEP_ENABLE = (DATA_WIDTH>8)
|
||||
KEEP_WIDTH = (DATA_WIDTH/8)
|
||||
LAST_ENABLE = 1
|
||||
ID_ENABLE = 1
|
||||
ID_WIDTH = 8
|
||||
DEST_ENABLE = 1
|
||||
DEST_WIDTH = 8
|
||||
USER_ENABLE = 1
|
||||
USER_WIDTH = 1
|
||||
|
||||
# Inputs
|
||||
clk = Signal(bool(0))
|
||||
rst = Signal(bool(0))
|
||||
current_test = Signal(intbv(0)[8:])
|
||||
|
||||
input_axis_tdata = Signal(intbv(0)[64:])
|
||||
input_axis_tkeep = Signal(intbv(0)[8:])
|
||||
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
|
||||
input_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
|
||||
input_axis_tvalid = Signal(bool(0))
|
||||
input_axis_tlast = Signal(bool(0))
|
||||
input_axis_tuser = Signal(bool(0))
|
||||
input_axis_tid = Signal(intbv(0)[ID_WIDTH:])
|
||||
input_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
|
||||
input_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
|
||||
output_axis_tready = Signal(bool(0))
|
||||
|
||||
# Outputs
|
||||
input_axis_tready = Signal(bool(0))
|
||||
output_axis_tdata = Signal(intbv(0)[64:])
|
||||
output_axis_tkeep = Signal(intbv(0)[8:])
|
||||
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
|
||||
output_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
|
||||
output_axis_tvalid = Signal(bool(0))
|
||||
output_axis_tlast = Signal(bool(0))
|
||||
output_axis_tuser = Signal(bool(0))
|
||||
output_axis_tid = Signal(intbv(0)[ID_WIDTH:])
|
||||
output_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
|
||||
output_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
|
||||
|
||||
# sources and sinks
|
||||
source_pause = Signal(bool(0))
|
||||
@ -80,6 +92,8 @@ def bench():
|
||||
tvalid=input_axis_tvalid,
|
||||
tready=input_axis_tready,
|
||||
tlast=input_axis_tlast,
|
||||
tid=input_axis_tid,
|
||||
tdest=input_axis_tdest,
|
||||
tuser=input_axis_tuser,
|
||||
pause=source_pause,
|
||||
name='source'
|
||||
@ -95,6 +109,8 @@ def bench():
|
||||
tvalid=output_axis_tvalid,
|
||||
tready=output_axis_tready,
|
||||
tlast=output_axis_tlast,
|
||||
tid=output_axis_tid,
|
||||
tdest=output_axis_tdest,
|
||||
tuser=output_axis_tuser,
|
||||
pause=sink_pause,
|
||||
name='sink'
|
||||
@ -115,6 +131,8 @@ def bench():
|
||||
input_axis_tvalid=input_axis_tvalid,
|
||||
input_axis_tready=input_axis_tready,
|
||||
input_axis_tlast=input_axis_tlast,
|
||||
input_axis_tid=input_axis_tid,
|
||||
input_axis_tdest=input_axis_tdest,
|
||||
input_axis_tuser=input_axis_tuser,
|
||||
|
||||
output_axis_tdata=output_axis_tdata,
|
||||
@ -122,6 +140,8 @@ def bench():
|
||||
output_axis_tvalid=output_axis_tvalid,
|
||||
output_axis_tready=output_axis_tready,
|
||||
output_axis_tlast=output_axis_tlast,
|
||||
output_axis_tid=output_axis_tid,
|
||||
output_axis_tdest=output_axis_tdest,
|
||||
output_axis_tuser=output_axis_tuser
|
||||
)
|
||||
|
||||
@ -146,10 +166,15 @@ def bench():
|
||||
print("test 1: test packet")
|
||||
current_test.next = 1
|
||||
|
||||
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame = axis_ep.AXIStreamFrame(
|
||||
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
|
||||
id=1,
|
||||
dest=1
|
||||
)
|
||||
|
||||
source.send(test_frame)
|
||||
yield clk.posedge
|
||||
|
||||
@ -167,10 +192,15 @@ def bench():
|
||||
print("test 2: longer packet")
|
||||
current_test.next = 2
|
||||
|
||||
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
bytearray(range(256)))
|
||||
test_frame = axis_ep.AXIStreamFrame(
|
||||
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
bytearray(range(256)),
|
||||
id=2,
|
||||
dest=1
|
||||
)
|
||||
|
||||
source.send(test_frame)
|
||||
yield clk.posedge
|
||||
|
||||
@ -186,10 +216,15 @@ def bench():
|
||||
print("test 3: test packet with pauses")
|
||||
current_test.next = 3
|
||||
|
||||
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
bytearray(range(256)))
|
||||
test_frame = axis_ep.AXIStreamFrame(
|
||||
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
bytearray(range(256)),
|
||||
id=3,
|
||||
dest=1
|
||||
)
|
||||
|
||||
source.send(test_frame)
|
||||
yield clk.posedge
|
||||
|
||||
@ -221,14 +256,23 @@ def bench():
|
||||
print("test 4: back-to-back packets")
|
||||
current_test.next = 4
|
||||
|
||||
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame1 = axis_ep.AXIStreamFrame(
|
||||
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
|
||||
id=4,
|
||||
dest=1
|
||||
)
|
||||
test_frame2 = axis_ep.AXIStreamFrame(
|
||||
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
|
||||
id=4,
|
||||
dest=2
|
||||
)
|
||||
|
||||
source.send(test_frame1)
|
||||
source.send(test_frame2)
|
||||
yield clk.posedge
|
||||
@ -253,14 +297,23 @@ def bench():
|
||||
print("test 5: alternate pause source")
|
||||
current_test.next = 5
|
||||
|
||||
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame1 = axis_ep.AXIStreamFrame(
|
||||
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
|
||||
id=5,
|
||||
dest=1
|
||||
)
|
||||
test_frame2 = axis_ep.AXIStreamFrame(
|
||||
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
|
||||
id=5,
|
||||
dest=2
|
||||
)
|
||||
|
||||
source.send(test_frame1)
|
||||
source.send(test_frame2)
|
||||
yield clk.posedge
|
||||
@ -290,14 +343,23 @@ def bench():
|
||||
print("test 6: alternate pause sink")
|
||||
current_test.next = 6
|
||||
|
||||
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame1 = axis_ep.AXIStreamFrame(
|
||||
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
|
||||
id=6,
|
||||
dest=1
|
||||
)
|
||||
test_frame2 = axis_ep.AXIStreamFrame(
|
||||
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
|
||||
id=6,
|
||||
dest=2
|
||||
)
|
||||
|
||||
source.send(test_frame1)
|
||||
source.send(test_frame2)
|
||||
yield clk.posedge
|
||||
@ -327,11 +389,16 @@ def bench():
|
||||
print("test 7: tuser assert")
|
||||
current_test.next = 7
|
||||
|
||||
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame.user = 1
|
||||
test_frame = axis_ep.AXIStreamFrame(
|
||||
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
|
||||
id=7,
|
||||
dest=1,
|
||||
last_cycle_user=1
|
||||
)
|
||||
|
||||
source.send(test_frame)
|
||||
yield clk.posedge
|
||||
|
||||
@ -342,7 +409,7 @@ def bench():
|
||||
rx_frame = sink.recv()
|
||||
|
||||
assert rx_frame == test_frame
|
||||
assert rx_frame.user[-1]
|
||||
assert rx_frame.last_cycle_user
|
||||
|
||||
yield delay(100)
|
||||
|
||||
|
||||
@ -27,13 +27,21 @@ THE SOFTWARE.
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* Testbench for axis_srl_register_64
|
||||
* Testbench for axis_srl_register
|
||||
*/
|
||||
module test_axis_srl_register_64;
|
||||
|
||||
// Parameters
|
||||
parameter DATA_WIDTH = 64;
|
||||
parameter KEEP_ENABLE = (DATA_WIDTH>8);
|
||||
parameter KEEP_WIDTH = (DATA_WIDTH/8);
|
||||
parameter LAST_ENABLE = 1;
|
||||
parameter ID_ENABLE = 1;
|
||||
parameter ID_WIDTH = 8;
|
||||
parameter DEST_ENABLE = 1;
|
||||
parameter DEST_WIDTH = 8;
|
||||
parameter USER_ENABLE = 1;
|
||||
parameter USER_WIDTH = 1;
|
||||
|
||||
// Inputs
|
||||
reg clk = 0;
|
||||
@ -44,7 +52,9 @@ reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
|
||||
reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0;
|
||||
reg input_axis_tvalid = 0;
|
||||
reg input_axis_tlast = 0;
|
||||
reg input_axis_tuser = 0;
|
||||
reg [ID_WIDTH-1:0] input_axis_tid = 0;
|
||||
reg [DEST_WIDTH-1:0] input_axis_tdest = 0;
|
||||
reg [USER_WIDTH-1:0] input_axis_tuser = 0;
|
||||
reg output_axis_tready = 0;
|
||||
|
||||
// Outputs
|
||||
@ -53,7 +63,9 @@ wire [DATA_WIDTH-1:0] output_axis_tdata;
|
||||
wire [KEEP_WIDTH-1:0] output_axis_tkeep;
|
||||
wire output_axis_tvalid;
|
||||
wire output_axis_tlast;
|
||||
wire output_axis_tuser;
|
||||
wire [ID_WIDTH-1:0] output_axis_tid;
|
||||
wire [DEST_WIDTH-1:0] output_axis_tdest;
|
||||
wire [USER_WIDTH-1:0] output_axis_tuser;
|
||||
|
||||
initial begin
|
||||
// myhdl integration
|
||||
@ -65,6 +77,8 @@ initial begin
|
||||
input_axis_tkeep,
|
||||
input_axis_tvalid,
|
||||
input_axis_tlast,
|
||||
input_axis_tid,
|
||||
input_axis_tdest,
|
||||
input_axis_tuser,
|
||||
output_axis_tready
|
||||
);
|
||||
@ -74,6 +88,8 @@ initial begin
|
||||
output_axis_tkeep,
|
||||
output_axis_tvalid,
|
||||
output_axis_tlast,
|
||||
output_axis_tid,
|
||||
output_axis_tdest,
|
||||
output_axis_tuser
|
||||
);
|
||||
|
||||
@ -82,26 +98,38 @@ initial begin
|
||||
$dumpvars(0, test_axis_srl_register_64);
|
||||
end
|
||||
|
||||
axis_srl_register_64 #(
|
||||
axis_srl_register #(
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.KEEP_WIDTH(KEEP_WIDTH)
|
||||
.KEEP_ENABLE(KEEP_ENABLE),
|
||||
.KEEP_WIDTH(KEEP_WIDTH),
|
||||
.LAST_ENABLE(LAST_ENABLE),
|
||||
.ID_ENABLE(ID_ENABLE),
|
||||
.ID_WIDTH(ID_WIDTH),
|
||||
.DEST_ENABLE(DEST_ENABLE),
|
||||
.DEST_WIDTH(DEST_WIDTH),
|
||||
.USER_ENABLE(USER_ENABLE),
|
||||
.USER_WIDTH(USER_WIDTH)
|
||||
)
|
||||
UUT (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
// axi input
|
||||
// AXI input
|
||||
.input_axis_tdata(input_axis_tdata),
|
||||
.input_axis_tkeep(input_axis_tkeep),
|
||||
.input_axis_tvalid(input_axis_tvalid),
|
||||
.input_axis_tready(input_axis_tready),
|
||||
.input_axis_tlast(input_axis_tlast),
|
||||
.input_axis_tid(input_axis_tid),
|
||||
.input_axis_tdest(input_axis_tdest),
|
||||
.input_axis_tuser(input_axis_tuser),
|
||||
// axi output
|
||||
// AXI output
|
||||
.output_axis_tdata(output_axis_tdata),
|
||||
.output_axis_tkeep(output_axis_tkeep),
|
||||
.output_axis_tvalid(output_axis_tvalid),
|
||||
.output_axis_tready(output_axis_tready),
|
||||
.output_axis_tlast(output_axis_tlast),
|
||||
.output_axis_tid(output_axis_tid),
|
||||
.output_axis_tdest(output_axis_tdest),
|
||||
.output_axis_tuser(output_axis_tuser)
|
||||
);
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user