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Adjust constant naming

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Alex Forencich 2016-06-27 11:27:04 -07:00
parent f89620008d
commit 4f66059d21
1 changed files with 7 additions and 7 deletions
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14
rtl/axis_adapter.v
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@ -61,9 +61,9 @@ module axis_adapter #
output wire output_axis_tuser output wire output_axis_tuser
); );
// bus word widths (must be identical) // bus word sizes (must be identical)
localparam INPUT_DATA_WORD_WIDTH = INPUT_DATA_WIDTH / INPUT_KEEP_WIDTH; localparam INPUT_DATA_WORD_SIZE = INPUT_DATA_WIDTH / INPUT_KEEP_WIDTH;
localparam OUTPUT_DATA_WORD_WIDTH = OUTPUT_DATA_WIDTH / OUTPUT_KEEP_WIDTH; localparam OUTPUT_DATA_WORD_SIZE = OUTPUT_DATA_WIDTH / OUTPUT_KEEP_WIDTH;
// output bus is wider // output bus is wider
localparam EXPAND_BUS = OUTPUT_KEEP_WIDTH > INPUT_KEEP_WIDTH; localparam EXPAND_BUS = OUTPUT_KEEP_WIDTH > INPUT_KEEP_WIDTH;
// total data and keep widths // total data and keep widths
@ -77,18 +77,18 @@ localparam CYCLE_KEEP_WIDTH = KEEP_WIDTH / CYCLE_COUNT;
// bus width assertions // bus width assertions
initial begin initial begin
if (INPUT_DATA_WORD_WIDTH * INPUT_KEEP_WIDTH != INPUT_DATA_WIDTH) begin if (INPUT_DATA_WORD_SIZE * INPUT_KEEP_WIDTH != INPUT_DATA_WIDTH) begin
$error("Error: input data width not evenly divisble"); $error("Error: input data width not evenly divisble");
$finish; $finish;
end end
if (OUTPUT_DATA_WORD_WIDTH * OUTPUT_KEEP_WIDTH != OUTPUT_DATA_WIDTH) begin if (OUTPUT_DATA_WORD_SIZE * OUTPUT_KEEP_WIDTH != OUTPUT_DATA_WIDTH) begin
$error("Error: output data width not evenly divisble"); $error("Error: output data width not evenly divisble");
$finish; $finish;
end end
if (INPUT_DATA_WORD_WIDTH != OUTPUT_DATA_WORD_WIDTH) begin if (INPUT_DATA_WORD_SIZE != OUTPUT_DATA_WORD_SIZE) begin
$error("Error: word width mismatch"); $error("Error: word size mismatch");
$finish; $finish;
end end
end end