FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-28 07:03:08 +08:00
Code Issues Projects Releases Wiki Activity

merged changes in axis

Browse Source
This commit is contained in:
Alex Forencich 2014-11-21 10:43:52 -08:00
commit 51a3f77283
1 changed files with 3 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
lib/axis/rtl/axis_stat_counter.v
View File

@ -220,8 +220,9 @@ always @* begin
// increment byte count by number of words transferred
bit_cnt = 0;
for (i = 0; i < KEEP_WIDTH; i = i + 1) begin
bit_cnt = bit_cnt + monitor_axis_tkeep[i];
for (i = 0; i <= KEEP_WIDTH; i = i + 1) begin
//bit_cnt = bit_cnt + monitor_axis_tkeep[i];
if (monitor_axis_tkeep == ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-i)) bit_cnt = i;
end
byte_count_next = byte_count_next + bit_cnt;