diff --git a/example/VCU118/fpga_10g/fpga.xdc b/example/VCU118/fpga_10g/fpga.xdc index 5f67fd2b..5dd36a0b 100644 --- a/example/VCU118/fpga_10g/fpga.xdc +++ b/example/VCU118/fpga_10g/fpga.xdc @@ -4,6 +4,7 @@ # General configuration set_property CFGBVS GND [current_design] set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] # System clocks # 300 MHz @@ -84,23 +85,23 @@ set_clock_groups -asynchronous -group [get_clocks phy_sgmii_clk -include_generat # QSFP28 Interfaces set_property -dict {LOC V7 } [get_ports qsfp1_tx1_p] ;# MGTYTXN0_231 GTYE3_CHANNEL_X1Y48 / GTYE3_COMMON_X1Y12 -set_property -dict {LOC V6 } [get_ports qsfp1_tx1_n] ;# MGTYTXP0_231 GTYE3_CHANNEL_X1Y48 / GTYE3_COMMON_X1Y12 +#set_property -dict {LOC V6 } [get_ports qsfp1_tx1_n] ;# MGTYTXP0_231 GTYE3_CHANNEL_X1Y48 / GTYE3_COMMON_X1Y12 set_property -dict {LOC Y2 } [get_ports qsfp1_rx1_p] ;# MGTYTXN1_231 GTYE3_CHANNEL_X1Y48 / GTYE3_COMMON_X1Y12 -set_property -dict {LOC Y1 } [get_ports qsfp1_rx1_n] ;# MGTYTXP1_231 GTYE3_CHANNEL_X1Y48 / GTYE3_COMMON_X1Y12 +#set_property -dict {LOC Y1 } [get_ports qsfp1_rx1_n] ;# MGTYTXP1_231 GTYE3_CHANNEL_X1Y48 / GTYE3_COMMON_X1Y12 set_property -dict {LOC T7 } [get_ports qsfp1_tx2_p] ;# MGTYTXN2_231 GTYE3_CHANNEL_X1Y49 / GTYE3_COMMON_X1Y12 -set_property -dict {LOC T6 } [get_ports qsfp1_tx2_n] ;# MGTYTXP2_231 GTYE3_CHANNEL_X1Y49 / GTYE3_COMMON_X1Y12 +#set_property -dict {LOC T6 } [get_ports qsfp1_tx2_n] ;# MGTYTXP2_231 GTYE3_CHANNEL_X1Y49 / GTYE3_COMMON_X1Y12 set_property -dict {LOC W4 } [get_ports qsfp1_rx2_p] ;# MGTYTXN3_231 GTYE3_CHANNEL_X1Y49 / GTYE3_COMMON_X1Y12 -set_property -dict {LOC W3 } [get_ports qsfp1_rx2_n] ;# MGTYTXP3_231 GTYE3_CHANNEL_X1Y49 / GTYE3_COMMON_X1Y12 +#set_property -dict {LOC W3 } [get_ports qsfp1_rx2_n] ;# MGTYTXP3_231 GTYE3_CHANNEL_X1Y49 / GTYE3_COMMON_X1Y12 set_property -dict {LOC P7 } [get_ports qsfp1_tx3_p] ;# MGTYTXN0_231 GTYE3_CHANNEL_X1Y50 / GTYE3_COMMON_X1Y12 -set_property -dict {LOC P6 } [get_ports qsfp1_tx3_n] ;# MGTYTXP0_231 GTYE3_CHANNEL_X1Y50 / GTYE3_COMMON_X1Y12 +#set_property -dict {LOC P6 } [get_ports qsfp1_tx3_n] ;# MGTYTXP0_231 GTYE3_CHANNEL_X1Y50 / GTYE3_COMMON_X1Y12 set_property -dict {LOC V2 } [get_ports qsfp1_rx3_p] ;# MGTYTXN1_231 GTYE3_CHANNEL_X1Y50 / GTYE3_COMMON_X1Y12 -set_property -dict {LOC V1 } [get_ports qsfp1_rx3_n] ;# MGTYTXP1_231 GTYE3_CHANNEL_X1Y50 / GTYE3_COMMON_X1Y12 +#set_property -dict {LOC V1 } [get_ports qsfp1_rx3_n] ;# MGTYTXP1_231 GTYE3_CHANNEL_X1Y50 / GTYE3_COMMON_X1Y12 set_property -dict {LOC M7 } [get_ports qsfp1_tx4_p] ;# MGTYTXN2_231 GTYE3_CHANNEL_X1Y51 / GTYE3_COMMON_X1Y12 -set_property -dict {LOC M6 } [get_ports qsfp1_tx4_n] ;# MGTYTXP2_231 GTYE3_CHANNEL_X1Y51 / GTYE3_COMMON_X1Y12 +#set_property -dict {LOC M6 } [get_ports qsfp1_tx4_n] ;# MGTYTXP2_231 GTYE3_CHANNEL_X1Y51 / GTYE3_COMMON_X1Y12 set_property -dict {LOC U4 } [get_ports qsfp1_rx4_p] ;# MGTYTXN3_231 GTYE3_CHANNEL_X1Y51 / GTYE3_COMMON_X1Y12 -set_property -dict {LOC U3 } [get_ports qsfp1_rx4_n] ;# MGTYTXP3_231 GTYE3_CHANNEL_X1Y51 / GTYE3_COMMON_X1Y12 +#set_property -dict {LOC U3 } [get_ports qsfp1_rx4_n] ;# MGTYTXP3_231 GTYE3_CHANNEL_X1Y51 / GTYE3_COMMON_X1Y12 set_property -dict {LOC W9 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_231 from U38.4 -set_property -dict {LOC W8 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_231 from U38.5 +#set_property -dict {LOC W8 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_231 from U38.5 #set_property -dict {LOC U9 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_231 from U57.28 #set_property -dict {LOC U8 } [get_ports qsfp1_mgt_refclk_1_n] ;# MGTREFCLK1N_231 from U57.29 #set_property -dict {LOC AM23 IOSTANDARD LVDS} [get_ports qsfp1_recclk_p] ;# to U57.16 @@ -116,23 +117,23 @@ create_clock -period 6.400 -name qsfp1_mgt_refclk_0 [get_ports qsfp1_mgt_refclk_ set_clock_groups -asynchronous -group [get_clocks qsfp1_mgt_refclk_0 -include_generated_clocks] set_property -dict {LOC L5 } [get_ports qsfp2_tx1_p] ;# MGTYTXN0_232 GTYE3_CHANNEL_X1Y52 / GTYE3_COMMON_X1Y13 -set_property -dict {LOC L4 } [get_ports qsfp2_tx1_n] ;# MGTYTXP0_232 GTYE3_CHANNEL_X1Y52 / GTYE3_COMMON_X1Y13 +#set_property -dict {LOC L4 } [get_ports qsfp2_tx1_n] ;# MGTYTXP0_232 GTYE3_CHANNEL_X1Y52 / GTYE3_COMMON_X1Y13 set_property -dict {LOC T2 } [get_ports qsfp2_rx1_p] ;# MGTYTXN1_232 GTYE3_CHANNEL_X1Y52 / GTYE3_COMMON_X1Y13 -set_property -dict {LOC T1 } [get_ports qsfp2_rx1_n] ;# MGTYTXP1_232 GTYE3_CHANNEL_X1Y52 / GTYE3_COMMON_X1Y13 +#set_property -dict {LOC T1 } [get_ports qsfp2_rx1_n] ;# MGTYTXP1_232 GTYE3_CHANNEL_X1Y52 / GTYE3_COMMON_X1Y13 set_property -dict {LOC K7 } [get_ports qsfp2_tx2_p] ;# MGTYTXN2_232 GTYE3_CHANNEL_X1Y53 / GTYE3_COMMON_X1Y13 -set_property -dict {LOC K6 } [get_ports qsfp2_tx2_n] ;# MGTYTXP2_232 GTYE3_CHANNEL_X1Y53 / GTYE3_COMMON_X1Y13 +#set_property -dict {LOC K6 } [get_ports qsfp2_tx2_n] ;# MGTYTXP2_232 GTYE3_CHANNEL_X1Y53 / GTYE3_COMMON_X1Y13 set_property -dict {LOC R4 } [get_ports qsfp2_rx2_p] ;# MGTYTXN3_232 GTYE3_CHANNEL_X1Y53 / GTYE3_COMMON_X1Y13 -set_property -dict {LOC R3 } [get_ports qsfp2_rx2_n] ;# MGTYTXP3_232 GTYE3_CHANNEL_X1Y53 / GTYE3_COMMON_X1Y13 +#set_property -dict {LOC R3 } [get_ports qsfp2_rx2_n] ;# MGTYTXP3_232 GTYE3_CHANNEL_X1Y53 / GTYE3_COMMON_X1Y13 set_property -dict {LOC J5 } [get_ports qsfp2_tx3_p] ;# MGTYTXN0_232 GTYE3_CHANNEL_X1Y54 / GTYE3_COMMON_X1Y13 -set_property -dict {LOC J4 } [get_ports qsfp2_tx3_n] ;# MGTYTXP0_232 GTYE3_CHANNEL_X1Y54 / GTYE3_COMMON_X1Y13 +#set_property -dict {LOC J4 } [get_ports qsfp2_tx3_n] ;# MGTYTXP0_232 GTYE3_CHANNEL_X1Y54 / GTYE3_COMMON_X1Y13 set_property -dict {LOC P2 } [get_ports qsfp2_rx3_p] ;# MGTYTXN1_232 GTYE3_CHANNEL_X1Y54 / GTYE3_COMMON_X1Y13 -set_property -dict {LOC P1 } [get_ports qsfp2_rx3_n] ;# MGTYTXP1_232 GTYE3_CHANNEL_X1Y54 / GTYE3_COMMON_X1Y13 +#set_property -dict {LOC P1 } [get_ports qsfp2_rx3_n] ;# MGTYTXP1_232 GTYE3_CHANNEL_X1Y54 / GTYE3_COMMON_X1Y13 set_property -dict {LOC H7 } [get_ports qsfp2_tx4_p] ;# MGTYTXN2_232 GTYE3_CHANNEL_X1Y55 / GTYE3_COMMON_X1Y13 -set_property -dict {LOC H6 } [get_ports qsfp2_tx4_n] ;# MGTYTXP2_232 GTYE3_CHANNEL_X1Y55 / GTYE3_COMMON_X1Y13 +#set_property -dict {LOC H6 } [get_ports qsfp2_tx4_n] ;# MGTYTXP2_232 GTYE3_CHANNEL_X1Y55 / GTYE3_COMMON_X1Y13 set_property -dict {LOC M2 } [get_ports qsfp2_rx4_p] ;# MGTYTXN3_232 GTYE3_CHANNEL_X1Y55 / GTYE3_COMMON_X1Y13 -set_property -dict {LOC M1 } [get_ports qsfp2_rx4_n] ;# MGTYTXP3_232 GTYE3_CHANNEL_X1Y55 / GTYE3_COMMON_X1Y13 -set_property -dict {LOC R9 } [get_ports qsfp2_mgt_refclk_0_p] ;# MGTREFCLK0P_232 from U104.13 -set_property -dict {LOC R8 } [get_ports qsfp2_mgt_refclk_0_n] ;# MGTREFCLK0N_232 from U104.14 +#set_property -dict {LOC M1 } [get_ports qsfp2_rx4_n] ;# MGTYTXP3_232 GTYE3_CHANNEL_X1Y55 / GTYE3_COMMON_X1Y13 +#set_property -dict {LOC R9 } [get_ports qsfp2_mgt_refclk_0_p] ;# MGTREFCLK0P_232 from U104.13 +#set_property -dict {LOC R8 } [get_ports qsfp2_mgt_refclk_0_n] ;# MGTREFCLK0N_232 from U104.14 #set_property -dict {LOC N9 } [get_ports qsfp2_mgt_refclk_1_p] ;# MGTREFCLK1P_232 from U57.35 #set_property -dict {LOC N8 } [get_ports qsfp2_mgt_refclk_1_n] ;# MGTREFCLK1N_232 from U57.34 #set_property -dict {LOC AP23 IOSTANDARD LVDS} [get_ports qsfp2_recclk_p] ;# to U57.12 @@ -144,8 +145,8 @@ set_property -dict {LOC AT21 IOSTANDARD LVCMOS18} [get_ports qsfp2_intl] set_property -dict {LOC AT24 IOSTANDARD LVCMOS18} [get_ports qsfp2_lpmode] # 156.25 MHz MGT reference clock -create_clock -period 6.400 -name qsfp2_mgt_refclk_0 [get_ports qsfp2_mgt_refclk_0_p] -set_clock_groups -asynchronous -group [get_clocks qsfp2_mgt_refclk_0 -include_generated_clocks] +#create_clock -period 6.400 -name qsfp2_mgt_refclk_0 [get_ports qsfp2_mgt_refclk_0_p] +#set_clock_groups -asynchronous -group [get_clocks qsfp2_mgt_refclk_0 -include_generated_clocks] # I2C interface set_property -dict {LOC AM24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_scl] diff --git a/example/VCU118/fpga_10g/fpga/Makefile b/example/VCU118/fpga_10g/fpga/Makefile index 82fc9d2b..37f715b9 100644 --- a/example/VCU118/fpga_10g/fpga/Makefile +++ b/example/VCU118/fpga_10g/fpga/Makefile @@ -19,6 +19,13 @@ SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v SYN_FILES += lib/eth/rtl/eth_mac_10g.v SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v +SYN_FILES += lib/eth/rtl/eth_phy_10g.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v +SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v +SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v SYN_FILES += lib/eth/rtl/eth_axis_rx_64.v SYN_FILES += lib/eth/rtl/eth_axis_tx_64.v @@ -51,7 +58,7 @@ XDC_FILES += clock.xdc # IP XCI_FILES = ip/gig_ethernet_pcs_pma_0.xci -XCI_FILES += ip/ten_gig_eth_pcs_pma_0.xci +XCI_FILES += ip/gtwizard_ultrascale_0.xci include ../common/vivado.mk diff --git a/example/VCU118/fpga_10g/ip/gig_ethernet_pcs_pma_0.xci b/example/VCU118/fpga_10g/ip/gig_ethernet_pcs_pma_0.xci index c2325349..129b30cc 100644 --- a/example/VCU118/fpga_10g/ip/gig_ethernet_pcs_pma_0.xci +++ b/example/VCU118/fpga_10g/ip/gig_ethernet_pcs_pma_0.xci @@ -9,6 +9,207 @@ gig_ethernet_pcs_pma_0 + 1 + 1 + 1 + 1 + + + + 0 + + + + 0 + + + 0 + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + false + false + false + false + 0 + + + + 0 + + + + 0 + false + 100000000 + + + + 0 + + + + 0 + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + false + false + false + false + 0 + 0 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + false + false + false + + + + 100000000 + 0 + 0.000 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + ACTIVE_LOW + ACTIVE_LOW + ACTIVE_LOW + ACTIVE_LOW + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0.000 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 true 0 0 @@ -20,7 +221,7 @@ DIFF_PAIR_2 DIFF_PAIR_1 virtexuplus - Sync + 0 gig_ethernet_pcs_pma_0 50.0 false @@ -38,6 +239,7 @@ GTH false true + false false false false @@ -59,6 +261,7 @@ xcvu9p false 1 + false true Sync gig_ethernet_pcs_pma_0 @@ -98,7 +301,8 @@ 0 false virtexuplus - + + xcvu9p flga2104 VERILOG @@ -109,17 +313,35 @@ TRUE TRUE IP_Flow - 0 + 5 TRUE . . - 2017.2.1 + 2018.3 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + diff --git a/example/VCU118/fpga_10g/ip/gtwizard_ultrascale_0.xci b/example/VCU118/fpga_10g/ip/gtwizard_ultrascale_0.xci new file mode 100644 index 00000000..a596a88d --- /dev/null +++ b/example/VCU118/fpga_10g/ip/gtwizard_ultrascale_0.xci @@ -0,0 +1,1408 @@ + + + xilinx.com + xci + unknown + 1.0 + + + gtwizard_ultrascale_0 + + + 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false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + true + true + true + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + true + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + true + false + false + false + false + false + true + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + true + false + false + false + false + false + false + false + false + false + true + true + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + true + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + true + false + false + false + false + false + false + false + false + false + false + true + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + true + false + false + false + false + false + false + false + true + false + false + false + false + false + false + false + false + false + false + true + false + false + false + false + false + false + false + false + true + true + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + virtexuplus + + + xcvu9p + flga2104 + VERILOG + + MIXED + -2L + E + TRUE + TRUE + IP_Flow + 5 + TRUE + . + + . + 2018.3 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/example/VCU118/fpga_10g/ip/ten_gig_eth_pcs_pma_0.xci b/example/VCU118/fpga_10g/ip/ten_gig_eth_pcs_pma_0.xci deleted file mode 100644 index 2d73f4a1..00000000 --- a/example/VCU118/fpga_10g/ip/ten_gig_eth_pcs_pma_0.xci +++ /dev/null @@ -1,131 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - ten_gig_eth_pcs_pma_0 - - - 0 - 75 - 64 - 7 - BASE-R - Asynchronous - Ethernet PCS/PMA 64-bit - MII - 0 - 0 - 0 - 0 - 0 - virtexuplus - 0 - 125 - Quad X0Y0 - 1 - 156.25 - GTY - None - 0 - 0 - 0 - 1 - 0 - X1Y48 - X1Y49 - X1Y50 - X1Y51 - 10 - 4 - 0 - 2 - 0 - 0 - 4 - 1 - 0 - 0 - 100 - BASE-R - Asynchronous - Ethernet PCS/PMA 64-bit - ten_gig_eth_pcs_pma_0 - MII - Custom - 0 - 0 - 0 - 0 - 0 - Custom - 0 - 125 - Quad_X1Y12 - 1 - 156.25 - GTY - None - 0 - 0 - 0 - 1 - 0 - X1Y48 - X1Y49 - X1Y50 - X1Y51 - 10 - 4 - 0 - 2 - 0 - 0 - false - 1 - virtexuplus - - xcvu9p - flga2104 - VERILOG - - MIXED - -2L - E - TRUE - TRUE - IP_Flow - 0 - TRUE - . - - . - 2017.2.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/example/VCU118/fpga_10g/rtl/fpga.v b/example/VCU118/fpga_10g/rtl/fpga.v index 3d704efb..7ffe4ac3 100644 --- a/example/VCU118/fpga_10g/rtl/fpga.v +++ b/example/VCU118/fpga_10g/rtl/fpga.v @@ -102,8 +102,8 @@ module fpga ( output wire qsfp2_tx4_n, input wire qsfp2_rx4_p, input wire qsfp2_rx4_n, - input wire qsfp2_mgt_refclk_0_p, - input wire qsfp2_mgt_refclk_0_n, + // input wire qsfp2_mgt_refclk_0_p, + // input wire qsfp2_mgt_refclk_0_n, // input wire qsfp2_mgt_refclk_1_p, // input wire qsfp2_mgt_refclk_1_n, // output wire qsfp2_recclk_p, @@ -282,11 +282,11 @@ sync_signal_inst ( // SI570 I2C wire i2c_scl_i; -wire i2c_scl_o = 1; -wire i2c_scl_t = 1; +wire i2c_scl_o = 1'b1; +wire i2c_scl_t = 1'b1; wire i2c_sda_i; -wire i2c_sda_o = 1; -wire i2c_sda_t = 1; +wire i2c_sda_o = 1'b1; +wire i2c_sda_t = 1'b1; assign i2c_scl_i = i2c_scl; assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o; @@ -302,7 +302,7 @@ wire qsfp1_tx_clk_1_int; wire qsfp1_tx_rst_1_int; wire [63:0] qsfp1_txd_1_int; wire [7:0] qsfp1_txc_1_int; -wire qsfp1_rx_clk_1_int = qsfp1_tx_clk_1_int; +wire qsfp1_rx_clk_1_int; wire qsfp1_rx_rst_1_int; wire [63:0] qsfp1_rxd_1_int; wire [7:0] qsfp1_rxc_1_int; @@ -310,7 +310,7 @@ wire qsfp1_tx_clk_2_int; wire qsfp1_tx_rst_2_int; wire [63:0] qsfp1_txd_2_int; wire [7:0] qsfp1_txc_2_int; -wire qsfp1_rx_clk_2_int = qsfp1_tx_clk_2_int; +wire qsfp1_rx_clk_2_int; wire qsfp1_rx_rst_2_int; wire [63:0] qsfp1_rxd_2_int; wire [7:0] qsfp1_rxc_2_int; @@ -318,7 +318,7 @@ wire qsfp1_tx_clk_3_int; wire qsfp1_tx_rst_3_int; wire [63:0] qsfp1_txd_3_int; wire [7:0] qsfp1_txc_3_int; -wire qsfp1_rx_clk_3_int = qsfp1_tx_clk_3_int; +wire qsfp1_rx_clk_3_int; wire qsfp1_rx_rst_3_int; wire [63:0] qsfp1_rxd_3_int; wire [7:0] qsfp1_rxc_3_int; @@ -326,7 +326,7 @@ wire qsfp1_tx_clk_4_int; wire qsfp1_tx_rst_4_int; wire [63:0] qsfp1_txd_4_int; wire [7:0] qsfp1_txc_4_int; -wire qsfp1_rx_clk_4_int = qsfp1_tx_clk_4_int; +wire qsfp1_rx_clk_4_int; wire qsfp1_rx_rst_4_int; wire [63:0] qsfp1_rxd_4_int; wire [7:0] qsfp1_rxc_4_int; @@ -339,7 +339,7 @@ wire qsfp2_tx_clk_1_int; wire qsfp2_tx_rst_1_int; wire [63:0] qsfp2_txd_1_int; wire [7:0] qsfp2_txc_1_int; -wire qsfp2_rx_clk_1_int = qsfp2_tx_clk_1_int; +wire qsfp2_rx_clk_1_int; wire qsfp2_rx_rst_1_int; wire [63:0] qsfp2_rxd_1_int; wire [7:0] qsfp2_rxc_1_int; @@ -347,7 +347,7 @@ wire qsfp2_tx_clk_2_int; wire qsfp2_tx_rst_2_int; wire [63:0] qsfp2_txd_2_int; wire [7:0] qsfp2_txc_2_int; -wire qsfp2_rx_clk_2_int = qsfp2_tx_clk_2_int; +wire qsfp2_rx_clk_2_int; wire qsfp2_rx_rst_2_int; wire [63:0] qsfp2_rxd_2_int; wire [7:0] qsfp2_rxc_2_int; @@ -355,7 +355,7 @@ wire qsfp2_tx_clk_3_int; wire qsfp2_tx_rst_3_int; wire [63:0] qsfp2_txd_3_int; wire [7:0] qsfp2_txc_3_int; -wire qsfp2_rx_clk_3_int = qsfp2_tx_clk_3_int; +wire qsfp2_rx_clk_3_int; wire qsfp2_rx_rst_3_int; wire [63:0] qsfp2_rxd_3_int; wire [7:0] qsfp2_rxc_3_int; @@ -363,7 +363,7 @@ wire qsfp2_tx_clk_4_int; wire qsfp2_tx_rst_4_int; wire [63:0] qsfp2_txd_4_int; wire [7:0] qsfp2_txc_4_int; -wire qsfp2_rx_clk_4_int = qsfp2_tx_clk_4_int; +wire qsfp2_rx_clk_4_int; wire qsfp2_rx_rst_4_int; wire [63:0] qsfp2_rxd_4_int; wire [7:0] qsfp2_rxc_4_int; @@ -378,555 +378,493 @@ wire qsfp2_rx_block_lock_2; wire qsfp2_rx_block_lock_3; wire qsfp2_rx_block_lock_4; -assign clk_156mhz_int = qsfp1_tx_clk_1_int; -assign rst_156mhz_int = qsfp1_tx_rst_1_int; +wire qsfp1_mgt_refclk_0; -ten_gig_eth_pcs_pma_0 -ten_gig_eth_pcs_pma_inst_qsfp1 ( - //// Channel 0 - .gt_rxp_in_0(qsfp1_rx1_p), - .gt_rxn_in_0(qsfp1_rx1_n), - .gt_txp_out_0(qsfp1_tx1_p), - .gt_txn_out_0(qsfp1_tx1_n), +wire [7:0] gt_txclkout; +wire gt_txusrclk; - .tx_mii_clk_0(qsfp1_tx_clk_1_int), - .rx_core_clk_0(qsfp1_rx_clk_1_int), - .rx_clk_out_0(), - .gt_loopback_in_0(3'd0), +wire [7:0] gt_rxclkout; +wire [7:0] gt_rxusrclk; - //// RX_0 Signals - .rx_reset_0(1'b0), - .user_rx_reset_0(qsfp1_rx_rst_1_int), - .rxrecclkout_0(), +wire gt_reset_tx_done; +wire gt_reset_rx_done; - //// RX_0 User Interface Signals - .rx_mii_d_0(qsfp1_rxd_1_int), - .rx_mii_c_0(qsfp1_rxc_1_int), +wire [7:0] gt_txprgdivresetdone; +wire [7:0] gt_txpmaresetdone; +wire [7:0] gt_rxprgdivresetdone; +wire [7:0] gt_rxpmaresetdone; - //// RX_0 Control Signals - .ctl_rx_test_pattern_0(1'b0), - .ctl_rx_test_pattern_enable_0(1'b0), - .ctl_rx_data_pattern_select_0(1'b0), - .ctl_rx_prbs31_test_pattern_enable_0(1'b0), +wire gt_tx_reset = ~((>_txprgdivresetdone) & (>_txpmaresetdone)); +wire gt_rx_reset = ~>_rxpmaresetdone; - //// RX_0 Stats Signals - .stat_rx_block_lock_0(qsfp1_rx_block_lock_1), - .stat_rx_framing_err_valid_0(), - .stat_rx_framing_err_0(), - .stat_rx_hi_ber_0(), - .stat_rx_valid_ctrl_code_0(), - .stat_rx_bad_code_0(), - .stat_rx_bad_code_valid_0(), - .stat_rx_error_valid_0(), - .stat_rx_error_0(), - .stat_rx_fifo_error_0(), - .stat_rx_local_fault_0(), - .stat_rx_status_0(), +reg gt_userclk_tx_active = 1'b0; +reg [7:0] gt_userclk_rx_active = 1'b0; - //// TX_0 Signals - .tx_reset_0(1'b0), - .user_tx_reset_0(qsfp1_tx_rst_1_int), - - //// TX_0 User Interface Signals - .tx_mii_d_0(qsfp1_txd_1_int), - .tx_mii_c_0(qsfp1_txc_1_int), - - //// TX_0 Control Signals - .ctl_tx_test_pattern_0(1'b0), - .ctl_tx_test_pattern_enable_0(1'b0), - .ctl_tx_test_pattern_select_0(1'b0), - .ctl_tx_data_pattern_select_0(1'b0), - .ctl_tx_test_pattern_seed_a_0(58'd0), - .ctl_tx_test_pattern_seed_b_0(58'd0), - .ctl_tx_prbs31_test_pattern_enable_0(1'b0), - - //// TX_0 Stats Signals - .stat_tx_local_fault_0(), - - .gtwiz_reset_tx_datapath_0(1'b0), - .gtwiz_reset_rx_datapath_0(1'b0), - - .gtpowergood_out_0(), - - - //// Channel 1 - .gt_rxp_in_1(qsfp1_rx2_p), - .gt_rxn_in_1(qsfp1_rx2_n), - .gt_txp_out_1(qsfp1_tx2_p), - .gt_txn_out_1(qsfp1_tx2_n), - - .tx_mii_clk_1(qsfp1_tx_clk_2_int), - .rx_core_clk_1(qsfp1_rx_clk_2_int), - .rx_clk_out_1(), - .gt_loopback_in_1(3'd0), - - //// RX_1 Signals - .rx_reset_1(1'b0), - .user_rx_reset_1(qsfp1_rx_rst_2_int), - .rxrecclkout_1(), - - //// RX_1 User Interface Signals - .rx_mii_d_1(qsfp1_rxd_2_int), - .rx_mii_c_1(qsfp1_rxc_2_int), - - //// RX_1 Control Signals - .ctl_rx_test_pattern_1(1'b0), - .ctl_rx_test_pattern_enable_1(1'b0), - .ctl_rx_data_pattern_select_1(1'b0), - .ctl_rx_prbs31_test_pattern_enable_1(1'b0), - - //// RX_1 Stats Signals - .stat_rx_block_lock_1(qsfp1_rx_block_lock_2), - .stat_rx_framing_err_valid_1(), - .stat_rx_framing_err_1(), - .stat_rx_hi_ber_1(), - .stat_rx_valid_ctrl_code_1(), - .stat_rx_bad_code_1(), - .stat_rx_bad_code_valid_1(), - .stat_rx_error_valid_1(), - .stat_rx_error_1(), - .stat_rx_fifo_error_1(), - .stat_rx_local_fault_1(), - .stat_rx_status_1(), - - //// TX_1 Signals - .tx_reset_1(1'b0), - .user_tx_reset_1(qsfp1_tx_rst_2_int), - - //// TX_1 User Interface Signals - .tx_mii_d_1(qsfp1_txd_2_int), - .tx_mii_c_1(qsfp1_txc_2_int), - - //// TX_1 Control Signals - .ctl_tx_test_pattern_1(1'b0), - .ctl_tx_test_pattern_enable_1(1'b0), - .ctl_tx_test_pattern_select_1(1'b0), - .ctl_tx_data_pattern_select_1(1'b0), - .ctl_tx_test_pattern_seed_a_1(58'd0), - .ctl_tx_test_pattern_seed_b_1(58'd0), - .ctl_tx_prbs31_test_pattern_enable_1(1'b0), - - //// TX_1 Stats Signals - .stat_tx_local_fault_1(), - - .gtwiz_reset_tx_datapath_1(1'b0), - .gtwiz_reset_rx_datapath_1(1'b0), - - .gtpowergood_out_1(), - - - //// Channel 2 - .gt_rxp_in_2(qsfp1_rx3_p), - .gt_rxn_in_2(qsfp1_rx3_n), - .gt_txp_out_2(qsfp1_tx3_p), - .gt_txn_out_2(qsfp1_tx3_n), - - .tx_mii_clk_2(qsfp1_tx_clk_3_int), - .rx_core_clk_2(qsfp1_rx_clk_3_int), - .rx_clk_out_2(), - .gt_loopback_in_2(3'd0), - - //// RX_2 Signals - .rx_reset_2(1'b0), - .user_rx_reset_2(qsfp1_rx_rst_3_int), - .rxrecclkout_2(), - - //// RX_2 User Interface Signals - .rx_mii_d_2(qsfp1_rxd_3_int), - .rx_mii_c_2(qsfp1_rxc_3_int), - - //// RX_2 Control Signals - .ctl_rx_test_pattern_2(1'b0), - .ctl_rx_test_pattern_enable_2(1'b0), - .ctl_rx_data_pattern_select_2(1'b0), - .ctl_rx_prbs31_test_pattern_enable_2(1'b0), - - //// RX_2 Stats Signals - .stat_rx_block_lock_2(qsfp1_rx_block_lock_3), - .stat_rx_framing_err_valid_2(), - .stat_rx_framing_err_2(), - .stat_rx_hi_ber_2(), - .stat_rx_valid_ctrl_code_2(), - .stat_rx_bad_code_2(), - .stat_rx_bad_code_valid_2(), - .stat_rx_error_valid_2(), - .stat_rx_error_2(), - .stat_rx_fifo_error_2(), - .stat_rx_local_fault_2(), - .stat_rx_status_2(), - - //// TX_2 Signals - .tx_reset_2(1'b0), - .user_tx_reset_2(qsfp1_tx_rst_3_int), - - //// TX_2 User Interface Signals - .tx_mii_d_2(qsfp1_txd_3_int), - .tx_mii_c_2(qsfp1_txc_3_int), - - //// TX_2 Control Signals - .ctl_tx_test_pattern_2(1'b0), - .ctl_tx_test_pattern_enable_2(1'b0), - .ctl_tx_test_pattern_select_2(1'b0), - .ctl_tx_data_pattern_select_2(1'b0), - .ctl_tx_test_pattern_seed_a_2(58'd0), - .ctl_tx_test_pattern_seed_b_2(58'd0), - .ctl_tx_prbs31_test_pattern_enable_2(1'b0), - - //// TX_2 Stats Signals - .stat_tx_local_fault_2(), - - .gtwiz_reset_tx_datapath_2(1'b0), - .gtwiz_reset_rx_datapath_2(1'b0), - - .gtpowergood_out_2(), - - - //// Channel 3 - .gt_rxp_in_3(qsfp1_rx4_p), - .gt_rxn_in_3(qsfp1_rx4_n), - .gt_txp_out_3(qsfp1_tx4_p), - .gt_txn_out_3(qsfp1_tx4_n), - - .tx_mii_clk_3(qsfp1_tx_clk_4_int), - .rx_core_clk_3(qsfp1_rx_clk_4_int), - .rx_clk_out_3(), - .gt_loopback_in_3(3'd0), - - //// RX_3 Signals - .rx_reset_3(1'b0), - .user_rx_reset_3(qsfp1_rx_rst_4_int), - .rxrecclkout_3(), - - //// RX_3 User Interface Signals - .rx_mii_d_3(qsfp1_rxd_4_int), - .rx_mii_c_3(qsfp1_rxc_4_int), - - //// RX_3 Control Signals - .ctl_rx_test_pattern_3(1'b0), - .ctl_rx_test_pattern_enable_3(1'b0), - .ctl_rx_data_pattern_select_3(1'b0), - .ctl_rx_prbs31_test_pattern_enable_3(1'b0), - - //// RX_3 Stats Signals - .stat_rx_block_lock_3(qsfp1_rx_block_lock_4), - .stat_rx_framing_err_valid_3(), - .stat_rx_framing_err_3(), - .stat_rx_hi_ber_3(), - .stat_rx_valid_ctrl_code_3(), - .stat_rx_bad_code_3(), - .stat_rx_bad_code_valid_3(), - .stat_rx_error_valid_3(), - .stat_rx_error_3(), - .stat_rx_fifo_error_3(), - .stat_rx_local_fault_3(), - .stat_rx_status_3(), - - //// TX_3 Signals - .tx_reset_3(1'b0), - .user_tx_reset_3(qsfp1_tx_rst_4_int), - - //// TX_3 User Interface Signals - .tx_mii_d_3(qsfp1_txd_4_int), - .tx_mii_c_3(qsfp1_txc_4_int), - - //// TX_3 Control Signals - .ctl_tx_test_pattern_3(1'b0), - .ctl_tx_test_pattern_enable_3(1'b0), - .ctl_tx_test_pattern_select_3(1'b0), - .ctl_tx_data_pattern_select_3(1'b0), - .ctl_tx_test_pattern_seed_a_3(58'd0), - .ctl_tx_test_pattern_seed_b_3(58'd0), - .ctl_tx_prbs31_test_pattern_enable_3(1'b0), - - //// TX_3 Stats Signals - .stat_tx_local_fault_3(), - - .gtwiz_reset_tx_datapath_3(1'b0), - .gtwiz_reset_rx_datapath_3(1'b0), - - .gtpowergood_out_3(), - - .gt_refclk_p(qsfp1_mgt_refclk_0_p), - .gt_refclk_n(qsfp1_mgt_refclk_0_n), - - .gt_refclk_out(), - - .sys_reset(rst_125mhz_int), - .dclk(clk_125mhz_int) +IBUFDS_GTE4 ibufds_gte4_qsfp1_mgt_refclk_0_inst ( + .I (qsfp1_mgt_refclk_0_p), + .IB (qsfp1_mgt_refclk_0_n), + .CEB (1'b0), + .O (qsfp1_mgt_refclk_0), + .ODIV2 () ); -ten_gig_eth_pcs_pma_0 -ten_gig_eth_pcs_pma_inst_qsfp2 ( - //// Channel 0 - .gt_rxp_in_0(qsfp2_rx1_p), - .gt_rxn_in_0(qsfp2_rx1_n), - .gt_txp_out_0(qsfp2_tx1_p), - .gt_txn_out_0(qsfp2_tx1_n), - .tx_mii_clk_0(qsfp2_tx_clk_1_int), - .rx_core_clk_0(qsfp2_rx_clk_1_int), - .rx_clk_out_0(), - .gt_loopback_in_0(3'd0), +BUFG_GT bufg_gt_tx_usrclk_inst ( + .CE (1'b1), + .CEMASK (1'b0), + .CLR (gt_tx_reset), + .CLRMASK (1'b0), + .DIV (3'd0), + .I (gt_txclkout[0]), + .O (gt_txusrclk) +); - //// RX_0 Signals - .rx_reset_0(1'b0), - .user_rx_reset_0(qsfp2_rx_rst_1_int), - .rxrecclkout_0(), +assign clk_156mhz_int = gt_txusrclk; - //// RX_0 User Interface Signals - .rx_mii_d_0(qsfp2_rxd_1_int), - .rx_mii_c_0(qsfp2_rxc_1_int), +always @(posedge gt_txusrclk, posedge gt_tx_reset) begin + if (gt_tx_reset) begin + gt_userclk_tx_active <= 1'b0; + end else begin + gt_userclk_tx_active <= 1'b1; + end +end - //// RX_0 Control Signals - .ctl_rx_test_pattern_0(1'b0), - .ctl_rx_test_pattern_enable_0(1'b0), - .ctl_rx_data_pattern_select_0(1'b0), - .ctl_rx_prbs31_test_pattern_enable_0(1'b0), +genvar n; - //// RX_0 Stats Signals - .stat_rx_block_lock_0(qsfp2_rx_block_lock_1), - .stat_rx_framing_err_valid_0(), - .stat_rx_framing_err_0(), - .stat_rx_hi_ber_0(), - .stat_rx_valid_ctrl_code_0(), - .stat_rx_bad_code_0(), - .stat_rx_bad_code_valid_0(), - .stat_rx_error_valid_0(), - .stat_rx_error_0(), - .stat_rx_fifo_error_0(), - .stat_rx_local_fault_0(), - .stat_rx_status_0(), +generate - //// TX_0 Signals - .tx_reset_0(1'b0), - .user_tx_reset_0(qsfp2_tx_rst_1_int), +for (n = 0; n < 8; n = n + 1) begin - //// TX_0 User Interface Signals - .tx_mii_d_0(qsfp2_txd_1_int), - .tx_mii_c_0(qsfp2_txc_1_int), + BUFG_GT bufg_gt_rx_usrclk_inst ( + .CE (1'b1), + .CEMASK (1'b0), + .CLR (gt_rx_reset), + .CLRMASK (1'b0), + .DIV (3'd0), + .I (gt_rxclkout[n]), + .O (gt_rxusrclk[n]) + ); - //// TX_0 Control Signals - .ctl_tx_test_pattern_0(1'b0), - .ctl_tx_test_pattern_enable_0(1'b0), - .ctl_tx_test_pattern_select_0(1'b0), - .ctl_tx_data_pattern_select_0(1'b0), - .ctl_tx_test_pattern_seed_a_0(58'd0), - .ctl_tx_test_pattern_seed_b_0(58'd0), - .ctl_tx_prbs31_test_pattern_enable_0(1'b0), + always @(posedge gt_rxusrclk[n], posedge gt_rx_reset) begin + if (gt_rx_reset) begin + gt_userclk_rx_active[n] <= 1'b0; + end else begin + gt_userclk_rx_active[n] <= 1'b1; + end + end - //// TX_0 Stats Signals - .stat_tx_local_fault_0(), +end - .gtwiz_reset_tx_datapath_0(1'b0), - .gtwiz_reset_rx_datapath_0(1'b0), +endgenerate - .gtpowergood_out_0(), +sync_reset #( + .N(4) +) +sync_reset_156mhz_inst ( + .clk(clk_156mhz_int), + .rst(~gt_reset_tx_done), + .sync_reset_out(rst_156mhz_int) +); +wire [5:0] qsfp1_gt_txheader_1; +wire [127:0] qsfp1_gt_txdata_1; +wire qsfp1_gt_rxgearboxslip_1; +wire [5:0] qsfp1_gt_rxheader_1; +wire [1:0] qsfp1_gt_rxheadervalid_1; +wire [127:0] qsfp1_gt_rxdata_1; +wire [1:0] qsfp1_gt_rxdatavalid_1; - //// Channel 1 - .gt_rxp_in_1(qsfp2_rx2_p), - .gt_rxn_in_1(qsfp2_rx2_n), - .gt_txp_out_1(qsfp2_tx2_p), - .gt_txn_out_1(qsfp2_tx2_n), +wire [5:0] qsfp1_gt_txheader_2; +wire [127:0] qsfp1_gt_txdata_2; +wire qsfp1_gt_rxgearboxslip_2; +wire [5:0] qsfp1_gt_rxheader_2; +wire [1:0] qsfp1_gt_rxheadervalid_2; +wire [127:0] qsfp1_gt_rxdata_2; +wire [1:0] qsfp1_gt_rxdatavalid_2; - .tx_mii_clk_1(qsfp2_tx_clk_2_int), - .rx_core_clk_1(qsfp2_rx_clk_2_int), - .rx_clk_out_1(), - .gt_loopback_in_1(3'd0), +wire [5:0] qsfp1_gt_txheader_3; +wire [127:0] qsfp1_gt_txdata_3; +wire qsfp1_gt_rxgearboxslip_3; +wire [5:0] qsfp1_gt_rxheader_3; +wire [1:0] qsfp1_gt_rxheadervalid_3; +wire [127:0] qsfp1_gt_rxdata_3; +wire [1:0] qsfp1_gt_rxdatavalid_3; - //// RX_1 Signals - .rx_reset_1(1'b0), - .user_rx_reset_1(qsfp2_rx_rst_2_int), - .rxrecclkout_1(), +wire [5:0] qsfp1_gt_txheader_4; +wire [127:0] qsfp1_gt_txdata_4; +wire qsfp1_gt_rxgearboxslip_4; +wire [5:0] qsfp1_gt_rxheader_4; +wire [1:0] qsfp1_gt_rxheadervalid_4; +wire [127:0] qsfp1_gt_rxdata_4; +wire [1:0] qsfp1_gt_rxdatavalid_4; - //// RX_1 User Interface Signals - .rx_mii_d_1(qsfp2_rxd_2_int), - .rx_mii_c_1(qsfp2_rxc_2_int), +wire [5:0] qsfp2_gt_txheader_1; +wire [127:0] qsfp2_gt_txdata_1; +wire qsfp2_gt_rxgearboxslip_1; +wire [5:0] qsfp2_gt_rxheader_1; +wire [1:0] qsfp2_gt_rxheadervalid_1; +wire [127:0] qsfp2_gt_rxdata_1; +wire [1:0] qsfp2_gt_rxdatavalid_1; - //// RX_1 Control Signals - .ctl_rx_test_pattern_1(1'b0), - .ctl_rx_test_pattern_enable_1(1'b0), - .ctl_rx_data_pattern_select_1(1'b0), - .ctl_rx_prbs31_test_pattern_enable_1(1'b0), +wire [5:0] qsfp2_gt_txheader_2; +wire [127:0] qsfp2_gt_txdata_2; +wire qsfp2_gt_rxgearboxslip_2; +wire [5:0] qsfp2_gt_rxheader_2; +wire [1:0] qsfp2_gt_rxheadervalid_2; +wire [127:0] qsfp2_gt_rxdata_2; +wire [1:0] qsfp2_gt_rxdatavalid_2; - //// RX_1 Stats Signals - .stat_rx_block_lock_1(qsfp2_rx_block_lock_2), - .stat_rx_framing_err_valid_1(), - .stat_rx_framing_err_1(), - .stat_rx_hi_ber_1(), - .stat_rx_valid_ctrl_code_1(), - .stat_rx_bad_code_1(), - .stat_rx_bad_code_valid_1(), - .stat_rx_error_valid_1(), - .stat_rx_error_1(), - .stat_rx_fifo_error_1(), - .stat_rx_local_fault_1(), - .stat_rx_status_1(), +wire [5:0] qsfp2_gt_txheader_3; +wire [127:0] qsfp2_gt_txdata_3; +wire qsfp2_gt_rxgearboxslip_3; +wire [5:0] qsfp2_gt_rxheader_3; +wire [1:0] qsfp2_gt_rxheadervalid_3; +wire [127:0] qsfp2_gt_rxdata_3; +wire [1:0] qsfp2_gt_rxdatavalid_3; - //// TX_1 Signals - .tx_reset_1(1'b0), - .user_tx_reset_1(qsfp2_tx_rst_2_int), +wire [5:0] qsfp2_gt_txheader_4; +wire [127:0] qsfp2_gt_txdata_4; +wire qsfp2_gt_rxgearboxslip_4; +wire [5:0] qsfp2_gt_rxheader_4; +wire [1:0] qsfp2_gt_rxheadervalid_4; +wire [127:0] qsfp2_gt_rxdata_4; +wire [1:0] qsfp2_gt_rxdatavalid_4; - //// TX_1 User Interface Signals - .tx_mii_d_1(qsfp2_txd_2_int), - .tx_mii_c_1(qsfp2_txc_2_int), +gtwizard_ultrascale_0 +qsfp_gty_inst ( + .gtwiz_userclk_tx_active_in(>_userclk_tx_active), + .gtwiz_userclk_rx_active_in(>_userclk_rx_active), - //// TX_1 Control Signals - .ctl_tx_test_pattern_1(1'b0), - .ctl_tx_test_pattern_enable_1(1'b0), - .ctl_tx_test_pattern_select_1(1'b0), - .ctl_tx_data_pattern_select_1(1'b0), - .ctl_tx_test_pattern_seed_a_1(58'd0), - .ctl_tx_test_pattern_seed_b_1(58'd0), - .ctl_tx_prbs31_test_pattern_enable_1(1'b0), + .gtwiz_reset_clk_freerun_in(clk_125mhz_int), + .gtwiz_reset_all_in(rst_125mhz_int), - //// TX_1 Stats Signals - .stat_tx_local_fault_1(), + .gtwiz_reset_tx_pll_and_datapath_in(1'b0), + .gtwiz_reset_tx_datapath_in(1'b0), - .gtwiz_reset_tx_datapath_1(1'b0), - .gtwiz_reset_rx_datapath_1(1'b0), + .gtwiz_reset_rx_pll_and_datapath_in(1'b0), + .gtwiz_reset_rx_datapath_in(1'b0), - .gtpowergood_out_1(), + .gtwiz_reset_rx_cdr_stable_out(), + .gtwiz_reset_tx_done_out(gt_reset_tx_done), + .gtwiz_reset_rx_done_out(gt_reset_rx_done), - //// Channel 2 - .gt_rxp_in_2(qsfp2_rx3_p), - .gt_rxn_in_2(qsfp2_rx3_n), - .gt_txp_out_2(qsfp2_tx3_p), - .gt_txn_out_2(qsfp2_tx3_n), + .gtrefclk00_in({2{qsfp1_mgt_refclk_0}}), - .tx_mii_clk_2(qsfp2_tx_clk_3_int), - .rx_core_clk_2(qsfp2_rx_clk_3_int), - .rx_clk_out_2(), - .gt_loopback_in_2(3'd0), + .qpll0outclk_out(), + .qpll0outrefclk_out(), - //// RX_2 Signals - .rx_reset_2(1'b0), - .user_rx_reset_2(qsfp2_rx_rst_3_int), - .rxrecclkout_2(), + .gtyrxn_in({qsfp2_rx4_n, qsfp2_rx3_n, qsfp2_rx2_n, qsfp2_rx1_n, qsfp1_rx4_n, qsfp1_rx3_n, qsfp1_rx2_n, qsfp1_rx1_n}), + .gtyrxp_in({qsfp2_rx4_p, qsfp2_rx3_p, qsfp2_rx2_p, qsfp2_rx1_p, qsfp1_rx4_p, qsfp1_rx3_p, qsfp1_rx2_p, qsfp1_rx1_p}), - //// RX_2 User Interface Signals - .rx_mii_d_2(qsfp2_rxd_3_int), - .rx_mii_c_2(qsfp2_rxc_3_int), + .rxusrclk_in(gt_rxusrclk), + .rxusrclk2_in(gt_rxusrclk), - //// RX_2 Control Signals - .ctl_rx_test_pattern_2(1'b0), - .ctl_rx_test_pattern_enable_2(1'b0), - .ctl_rx_data_pattern_select_2(1'b0), - .ctl_rx_prbs31_test_pattern_enable_2(1'b0), + .txdata_in({qsfp2_gt_txdata_4, qsfp2_gt_txdata_3, qsfp2_gt_txdata_2, qsfp2_gt_txdata_1, qsfp1_gt_txdata_4, qsfp1_gt_txdata_3, qsfp1_gt_txdata_2, qsfp1_gt_txdata_1}), + .txheader_in({qsfp2_gt_txheader_4, qsfp2_gt_txheader_3, qsfp2_gt_txheader_2, qsfp2_gt_txheader_1, qsfp1_gt_txheader_4, qsfp1_gt_txheader_3, qsfp1_gt_txheader_2, qsfp1_gt_txheader_1}), + .txsequence_in({8{1'b0}}), - //// RX_2 Stats Signals - .stat_rx_block_lock_2(qsfp2_rx_block_lock_3), - .stat_rx_framing_err_valid_2(), - .stat_rx_framing_err_2(), - .stat_rx_hi_ber_2(), - .stat_rx_valid_ctrl_code_2(), - .stat_rx_bad_code_2(), - .stat_rx_bad_code_valid_2(), - .stat_rx_error_valid_2(), - .stat_rx_error_2(), - .stat_rx_fifo_error_2(), - .stat_rx_local_fault_2(), - .stat_rx_status_2(), + .txusrclk_in({8{gt_txusrclk}}), + .txusrclk2_in({8{gt_txusrclk}}), - //// TX_2 Signals - .tx_reset_2(1'b0), - .user_tx_reset_2(qsfp2_tx_rst_3_int), + .gtpowergood_out(), - //// TX_2 User Interface Signals - .tx_mii_d_2(qsfp2_txd_3_int), - .tx_mii_c_2(qsfp2_txc_3_int), + .gtytxn_out({qsfp2_tx4_n, qsfp2_tx3_n, qsfp2_tx2_n, qsfp2_tx1_n, qsfp1_tx4_n, qsfp1_tx3_n, qsfp1_tx2_n, qsfp1_tx1_n}), + .gtytxp_out({qsfp2_tx4_p, qsfp2_tx3_p, qsfp2_tx2_p, qsfp2_tx1_p, qsfp1_tx4_p, qsfp1_tx3_p, qsfp1_tx2_p, qsfp1_tx1_p}), - //// TX_2 Control Signals - .ctl_tx_test_pattern_2(1'b0), - .ctl_tx_test_pattern_enable_2(1'b0), - .ctl_tx_test_pattern_select_2(1'b0), - .ctl_tx_data_pattern_select_2(1'b0), - .ctl_tx_test_pattern_seed_a_2(58'd0), - .ctl_tx_test_pattern_seed_b_2(58'd0), - .ctl_tx_prbs31_test_pattern_enable_2(1'b0), + .rxgearboxslip_in({qsfp2_gt_rxgearboxslip_4, qsfp2_gt_rxgearboxslip_3, qsfp2_gt_rxgearboxslip_2, qsfp2_gt_rxgearboxslip_1, qsfp1_gt_rxgearboxslip_4, qsfp1_gt_rxgearboxslip_3, qsfp1_gt_rxgearboxslip_2, qsfp1_gt_rxgearboxslip_1}), + .rxdata_out({qsfp2_gt_rxdata_4, qsfp2_gt_rxdata_3, qsfp2_gt_rxdata_2, qsfp2_gt_rxdata_1, qsfp1_gt_rxdata_4, qsfp1_gt_rxdata_3, qsfp1_gt_rxdata_2, qsfp1_gt_rxdata_1}), + .rxdatavalid_out({qsfp2_gt_rxdatavalid_4, qsfp2_gt_rxdatavalid_3, qsfp2_gt_rxdatavalid_2, qsfp2_gt_rxdatavalid_1, qsfp1_gt_rxdatavalid_4, qsfp1_gt_rxdatavalid_3, qsfp1_gt_rxdatavalid_2, qsfp1_gt_rxdatavalid_1}), + .rxheader_out({qsfp2_gt_rxheader_4, qsfp2_gt_rxheader_3, qsfp2_gt_rxheader_2, qsfp2_gt_rxheader_1, qsfp1_gt_rxheader_4, qsfp1_gt_rxheader_3, qsfp1_gt_rxheader_2, qsfp1_gt_rxheader_1}), + .rxheadervalid_out({qsfp2_gt_rxheadervalid_4, qsfp2_gt_rxheadervalid_3, qsfp2_gt_rxheadervalid_2, qsfp2_gt_rxheadervalid_1, qsfp1_gt_rxheadervalid_4, qsfp1_gt_rxheadervalid_3, qsfp1_gt_rxheadervalid_2, qsfp1_gt_rxheadervalid_1}), + .rxoutclk_out(gt_rxclkout), + .rxpmaresetdone_out(gt_rxpmaresetdone), + .rxprgdivresetdone_out(gt_rxprgdivresetdone), + .rxstartofseq_out(), - //// TX_2 Stats Signals - .stat_tx_local_fault_2(), + .txoutclk_out(gt_txclkout), + .txpmaresetdone_out(gt_txpmaresetdone), + .txprgdivresetdone_out(gt_txprgdivresetdone) +); - .gtwiz_reset_tx_datapath_2(1'b0), - .gtwiz_reset_rx_datapath_2(1'b0), +assign qsfp1_tx_clk_1_int = clk_156mhz_int; +assign qsfp1_tx_rst_1_int = rst_156mhz_int; - .gtpowergood_out_2(), +assign qsfp1_rx_clk_1_int = gt_rxusrclk[0]; +sync_reset #( + .N(4) +) +qsfp1_rx_rst_1_reset_sync_inst ( + .clk(qsfp1_rx_clk_1_int), + .rst(~gt_reset_rx_done), + .sync_reset_out(qsfp1_rx_rst_1_int) +); - //// Channel 3 - .gt_rxp_in_3(qsfp2_rx4_p), - .gt_rxn_in_3(qsfp2_rx4_n), - .gt_txp_out_3(qsfp2_tx4_p), - .gt_txn_out_3(qsfp2_tx4_n), +eth_phy_10g #( + .BIT_REVERSE(1) +) +qsfp1_phy_1_inst ( + .tx_clk(qsfp1_tx_clk_1_int), + .tx_rst(qsfp1_tx_rst_1_int), + .rx_clk(qsfp1_rx_clk_1_int), + .rx_rst(qsfp1_rx_rst_1_int), + .xgmii_txd(qsfp1_txd_1_int), + .xgmii_txc(qsfp1_txc_1_int), + .xgmii_rxd(qsfp1_rxd_1_int), + .xgmii_rxc(qsfp1_rxc_1_int), + .serdes_tx_data(qsfp1_gt_txdata_1), + .serdes_tx_hdr(qsfp1_gt_txheader_1), + .serdes_rx_data(qsfp1_gt_rxdata_1), + .serdes_rx_hdr(qsfp1_gt_rxheader_1), + .serdes_rx_bitslip(qsfp1_gt_rxgearboxslip_1), + .rx_block_lock(qsfp1_rx_block_lock_1), + .rx_high_ber() +); - .tx_mii_clk_3(qsfp2_tx_clk_4_int), - .rx_core_clk_3(qsfp2_rx_clk_4_int), - .rx_clk_out_3(), - .gt_loopback_in_3(3'd0), +assign qsfp1_tx_clk_2_int = clk_156mhz_int; +assign qsfp1_tx_rst_2_int = rst_156mhz_int; - //// RX_3 Signals - .rx_reset_3(1'b0), - .user_rx_reset_3(qsfp2_rx_rst_4_int), - .rxrecclkout_3(), +assign qsfp1_rx_clk_2_int = gt_rxusrclk[1]; - //// RX_3 User Interface Signals - .rx_mii_d_3(qsfp2_rxd_4_int), - .rx_mii_c_3(qsfp2_rxc_4_int), +sync_reset #( + .N(4) +) +qsfp1_rx_rst_2_reset_sync_inst ( + .clk(qsfp1_rx_clk_2_int), + .rst(~gt_reset_rx_done), + .sync_reset_out(qsfp1_rx_rst_2_int) +); - //// RX_3 Control Signals - .ctl_rx_test_pattern_3(1'b0), - .ctl_rx_test_pattern_enable_3(1'b0), - .ctl_rx_data_pattern_select_3(1'b0), - .ctl_rx_prbs31_test_pattern_enable_3(1'b0), +eth_phy_10g #( + .BIT_REVERSE(1) +) +qsfp1_phy_2_inst ( + .tx_clk(qsfp1_tx_clk_2_int), + .tx_rst(qsfp1_tx_rst_2_int), + .rx_clk(qsfp1_rx_clk_2_int), + .rx_rst(qsfp1_rx_rst_2_int), + .xgmii_txd(qsfp1_txd_2_int), + .xgmii_txc(qsfp1_txc_2_int), + .xgmii_rxd(qsfp1_rxd_2_int), + .xgmii_rxc(qsfp1_rxc_2_int), + .serdes_tx_data(qsfp1_gt_txdata_2), + .serdes_tx_hdr(qsfp1_gt_txheader_2), + .serdes_rx_data(qsfp1_gt_rxdata_2), + .serdes_rx_hdr(qsfp1_gt_rxheader_2), + .serdes_rx_bitslip(qsfp1_gt_rxgearboxslip_2), + .rx_block_lock(qsfp1_rx_block_lock_2), + .rx_high_ber() +); - //// RX_3 Stats Signals - .stat_rx_block_lock_3(qsfp2_rx_block_lock_4), - .stat_rx_framing_err_valid_3(), - .stat_rx_framing_err_3(), - .stat_rx_hi_ber_3(), - .stat_rx_valid_ctrl_code_3(), - .stat_rx_bad_code_3(), - .stat_rx_bad_code_valid_3(), - .stat_rx_error_valid_3(), - .stat_rx_error_3(), - .stat_rx_fifo_error_3(), - .stat_rx_local_fault_3(), - .stat_rx_status_3(), +assign qsfp1_tx_clk_3_int = clk_156mhz_int; +assign qsfp1_tx_rst_3_int = rst_156mhz_int; - //// TX_3 Signals - .tx_reset_3(1'b0), - .user_tx_reset_3(qsfp2_tx_rst_4_int), +assign qsfp1_rx_clk_3_int = gt_rxusrclk[2]; - //// TX_3 User Interface Signals - .tx_mii_d_3(qsfp2_txd_4_int), - .tx_mii_c_3(qsfp2_txc_4_int), +sync_reset #( + .N(4) +) +qsfp1_rx_rst_3_reset_sync_inst ( + .clk(qsfp1_rx_clk_3_int), + .rst(~gt_reset_rx_done), + .sync_reset_out(qsfp1_rx_rst_3_int) +); - //// TX_3 Control Signals - .ctl_tx_test_pattern_3(1'b0), - .ctl_tx_test_pattern_enable_3(1'b0), - .ctl_tx_test_pattern_select_3(1'b0), - .ctl_tx_data_pattern_select_3(1'b0), - .ctl_tx_test_pattern_seed_a_3(58'd0), - .ctl_tx_test_pattern_seed_b_3(58'd0), - .ctl_tx_prbs31_test_pattern_enable_3(1'b0), +eth_phy_10g #( + .BIT_REVERSE(1) +) +qsfp1_phy_3_inst ( + .tx_clk(qsfp1_tx_clk_3_int), + .tx_rst(qsfp1_tx_rst_3_int), + .rx_clk(qsfp1_rx_clk_3_int), + .rx_rst(qsfp1_rx_rst_3_int), + .xgmii_txd(qsfp1_txd_3_int), + .xgmii_txc(qsfp1_txc_3_int), + .xgmii_rxd(qsfp1_rxd_3_int), + .xgmii_rxc(qsfp1_rxc_3_int), + .serdes_tx_data(qsfp1_gt_txdata_3), + .serdes_tx_hdr(qsfp1_gt_txheader_3), + .serdes_rx_data(qsfp1_gt_rxdata_3), + .serdes_rx_hdr(qsfp1_gt_rxheader_3), + .serdes_rx_bitslip(qsfp1_gt_rxgearboxslip_3), + .rx_block_lock(qsfp1_rx_block_lock_3), + .rx_high_ber() +); - //// TX_3 Stats Signals - .stat_tx_local_fault_3(), +assign qsfp1_tx_clk_4_int = clk_156mhz_int; +assign qsfp1_tx_rst_4_int = rst_156mhz_int; - .gtwiz_reset_tx_datapath_3(1'b0), - .gtwiz_reset_rx_datapath_3(1'b0), +assign qsfp1_rx_clk_4_int = gt_rxusrclk[3]; - .gtpowergood_out_3(), +sync_reset #( + .N(4) +) +qsfp1_rx_rst_4_reset_sync_inst ( + .clk(qsfp1_rx_clk_4_int), + .rst(~gt_reset_rx_done), + .sync_reset_out(qsfp1_rx_rst_4_int) +); - .gt_refclk_p(qsfp2_mgt_refclk_0_p), - .gt_refclk_n(qsfp2_mgt_refclk_0_n), +eth_phy_10g #( + .BIT_REVERSE(1) +) +qsfp1_phy_4_inst ( + .tx_clk(qsfp1_tx_clk_4_int), + .tx_rst(qsfp1_tx_rst_4_int), + .rx_clk(qsfp1_rx_clk_4_int), + .rx_rst(qsfp1_rx_rst_4_int), + .xgmii_txd(qsfp1_txd_4_int), + .xgmii_txc(qsfp1_txc_4_int), + .xgmii_rxd(qsfp1_rxd_4_int), + .xgmii_rxc(qsfp1_rxc_4_int), + .serdes_tx_data(qsfp1_gt_txdata_4), + .serdes_tx_hdr(qsfp1_gt_txheader_4), + .serdes_rx_data(qsfp1_gt_rxdata_4), + .serdes_rx_hdr(qsfp1_gt_rxheader_4), + .serdes_rx_bitslip(qsfp1_gt_rxgearboxslip_4), + .rx_block_lock(qsfp1_rx_block_lock_4), + .rx_high_ber() +); - .gt_refclk_out(), +assign qsfp2_tx_clk_1_int = clk_156mhz_int; +assign qsfp2_tx_rst_1_int = rst_156mhz_int; - .sys_reset(rst_125mhz_int), - .dclk(clk_125mhz_int) +assign qsfp2_rx_clk_1_int = gt_rxusrclk[4]; + +sync_reset #( + .N(4) +) +qsfp2_rx_rst_1_reset_sync_inst ( + .clk(qsfp2_rx_clk_1_int), + .rst(~gt_reset_rx_done), + .sync_reset_out(qsfp2_rx_rst_1_int) +); + +eth_phy_10g #( + .BIT_REVERSE(1) +) +qsfp2_phy_1_inst ( + .tx_clk(qsfp2_tx_clk_1_int), + .tx_rst(qsfp2_tx_rst_1_int), + .rx_clk(qsfp2_rx_clk_1_int), + .rx_rst(qsfp2_rx_rst_1_int), + .xgmii_txd(qsfp2_txd_1_int), + .xgmii_txc(qsfp2_txc_1_int), + .xgmii_rxd(qsfp2_rxd_1_int), + .xgmii_rxc(qsfp2_rxc_1_int), + .serdes_tx_data(qsfp2_gt_txdata_1), + .serdes_tx_hdr(qsfp2_gt_txheader_1), + .serdes_rx_data(qsfp2_gt_rxdata_1), + .serdes_rx_hdr(qsfp2_gt_rxheader_1), + .serdes_rx_bitslip(qsfp2_gt_rxgearboxslip_1), + .rx_block_lock(qsfp2_rx_block_lock_1), + .rx_high_ber() +); + +assign qsfp2_tx_clk_2_int = clk_156mhz_int; +assign qsfp2_tx_rst_2_int = rst_156mhz_int; + +assign qsfp2_rx_clk_2_int = gt_rxusrclk[5]; + +sync_reset #( + .N(4) +) +qsfp2_rx_rst_2_reset_sync_inst ( + .clk(qsfp2_rx_clk_2_int), + .rst(~gt_reset_rx_done), + .sync_reset_out(qsfp2_rx_rst_2_int) +); + +eth_phy_10g #( + .BIT_REVERSE(1) +) +qsfp2_phy_2_inst ( + .tx_clk(qsfp2_tx_clk_2_int), + .tx_rst(qsfp2_tx_rst_2_int), + .rx_clk(qsfp2_rx_clk_2_int), + .rx_rst(qsfp2_rx_rst_2_int), + .xgmii_txd(qsfp2_txd_2_int), + .xgmii_txc(qsfp2_txc_2_int), + .xgmii_rxd(qsfp2_rxd_2_int), + .xgmii_rxc(qsfp2_rxc_2_int), + .serdes_tx_data(qsfp2_gt_txdata_2), + .serdes_tx_hdr(qsfp2_gt_txheader_2), + .serdes_rx_data(qsfp2_gt_rxdata_2), + .serdes_rx_hdr(qsfp2_gt_rxheader_2), + .serdes_rx_bitslip(qsfp2_gt_rxgearboxslip_2), + .rx_block_lock(qsfp2_rx_block_lock_2), + .rx_high_ber() +); + +assign qsfp2_tx_clk_3_int = clk_156mhz_int; +assign qsfp2_tx_rst_3_int = rst_156mhz_int; + +assign qsfp2_rx_clk_3_int = gt_rxusrclk[6]; + +sync_reset #( + .N(4) +) +qsfp2_rx_rst_3_reset_sync_inst ( + .clk(qsfp2_rx_clk_3_int), + .rst(~gt_reset_rx_done), + .sync_reset_out(qsfp2_rx_rst_3_int) +); + +eth_phy_10g #( + .BIT_REVERSE(1) +) +qsfp2_phy_3_inst ( + .tx_clk(qsfp2_tx_clk_3_int), + .tx_rst(qsfp2_tx_rst_3_int), + .rx_clk(qsfp2_rx_clk_3_int), + .rx_rst(qsfp2_rx_rst_3_int), + .xgmii_txd(qsfp2_txd_3_int), + .xgmii_txc(qsfp2_txc_3_int), + .xgmii_rxd(qsfp2_rxd_3_int), + .xgmii_rxc(qsfp2_rxc_3_int), + .serdes_tx_data(qsfp2_gt_txdata_3), + .serdes_tx_hdr(qsfp2_gt_txheader_3), + .serdes_rx_data(qsfp2_gt_rxdata_3), + .serdes_rx_hdr(qsfp2_gt_rxheader_3), + .serdes_rx_bitslip(qsfp2_gt_rxgearboxslip_3), + .rx_block_lock(qsfp2_rx_block_lock_3), + .rx_high_ber() +); + +assign qsfp2_tx_clk_4_int = clk_156mhz_int; +assign qsfp2_tx_rst_4_int = rst_156mhz_int; + +assign qsfp2_rx_clk_4_int = gt_rxusrclk[7]; + +sync_reset #( + .N(4) +) +qsfp2_rx_rst_4_reset_sync_inst ( + .clk(qsfp2_rx_clk_4_int), + .rst(~gt_reset_rx_done), + .sync_reset_out(qsfp2_rx_rst_4_int) +); + +eth_phy_10g #( + .BIT_REVERSE(1) +) +qsfp2_phy_4_inst ( + .tx_clk(qsfp2_tx_clk_4_int), + .tx_rst(qsfp2_tx_rst_4_int), + .rx_clk(qsfp2_rx_clk_4_int), + .rx_rst(qsfp2_rx_rst_4_int), + .xgmii_txd(qsfp2_txd_4_int), + .xgmii_txc(qsfp2_txc_4_int), + .xgmii_rxd(qsfp2_rxd_4_int), + .xgmii_rxc(qsfp2_rxc_4_int), + .serdes_tx_data(qsfp2_gt_txdata_4), + .serdes_tx_hdr(qsfp2_gt_txheader_4), + .serdes_rx_data(qsfp2_gt_rxdata_4), + .serdes_rx_hdr(qsfp2_gt_rxheader_4), + .serdes_rx_bitslip(qsfp2_gt_rxgearboxslip_4), + .rx_block_lock(qsfp2_rx_block_lock_4), + .rx_high_ber() ); // SGMII interface to PHY