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https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-14 06:43:18 +08:00
Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream demux
This commit is contained in:
Alex Forencich
parent
9e4aa38750
commit
57e700f802
@ -71,30 +71,44 @@ THE SOFTWARE.
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*/
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module {{name}} #
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(
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parameter DATA_WIDTH = 8
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parameter DATA_WIDTH = 8,
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parameter KEEP_ENABLE = (DATA_WIDTH>8),
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parameter KEEP_WIDTH = (DATA_WIDTH/8),
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parameter ID_ENABLE = 0,
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parameter ID_WIDTH = 8,
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parameter DEST_ENABLE = 0,
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parameter DEST_WIDTH = 8,
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parameter USER_ENABLE = 1,
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parameter USER_WIDTH = 1
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI input
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*/
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input wire [DATA_WIDTH-1:0] input_axis_tdata,
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input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
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input wire input_axis_tvalid,
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output wire input_axis_tready,
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input wire input_axis_tlast,
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input wire input_axis_tuser,
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input wire [ID_WIDTH-1:0] input_axis_tid,
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input wire [DEST_WIDTH-1:0] input_axis_tdest,
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input wire [USER_WIDTH-1:0] input_axis_tuser,
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/*
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* AXI outputs
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*/
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{%- for p in ports %}
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output wire [DATA_WIDTH-1:0] output_{{p}}_axis_tdata,
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output wire [KEEP_WIDTH-1:0] output_{{p}}_axis_tkeep,
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output wire output_{{p}}_axis_tvalid,
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input wire output_{{p}}_axis_tready,
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output wire output_{{p}}_axis_tlast,
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output wire output_{{p}}_axis_tuser,
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output wire [ID_WIDTH-1:0] output_{{p}}_axis_tid,
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output wire [DEST_WIDTH-1:0] output_{{p}}_axis_tdest,
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output wire [USER_WIDTH-1:0] output_{{p}}_axis_tuser,
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{% endfor %}
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/*
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* Control
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@ -109,12 +123,15 @@ reg frame_reg = 1'b0, frame_next;
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reg input_axis_tready_reg = 1'b0, input_axis_tready_next;
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// internal datapath
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reg [DATA_WIDTH-1:0] output_axis_tdata_int;
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reg output_axis_tvalid_int;
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reg output_axis_tready_int_reg = 1'b0;
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reg output_axis_tlast_int;
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reg output_axis_tuser_int;
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wire output_axis_tready_int_early;
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reg [DATA_WIDTH-1:0] output_axis_tdata_int;
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reg [KEEP_WIDTH-1:0] output_axis_tkeep_int;
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reg output_axis_tvalid_int;
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reg output_axis_tready_int_reg = 1'b0;
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reg output_axis_tlast_int;
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reg [ID_WIDTH-1:0] output_axis_tid_int;
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reg [DEST_WIDTH-1:0] output_axis_tdest_int;
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reg [USER_WIDTH-1:0] output_axis_tuser_int;
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wire output_axis_tready_int_early;
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assign input_axis_tready = input_axis_tready_reg;
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@ -157,10 +174,13 @@ always @* begin
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input_axis_tready_next = output_axis_tready_int_early & frame_next;
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output_axis_tdata_int = input_axis_tdata;
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output_axis_tdata_int = input_axis_tdata;
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output_axis_tkeep_int = input_axis_tkeep;
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output_axis_tvalid_int = input_axis_tvalid & input_axis_tready;
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output_axis_tlast_int = input_axis_tlast;
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output_axis_tuser_int = input_axis_tuser;
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output_axis_tlast_int = input_axis_tlast;
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output_axis_tid_int = input_axis_tid;
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output_axis_tdest_int = input_axis_tdest;
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output_axis_tuser_int = input_axis_tuser;
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end
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always @(posedge clk) begin
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@ -176,27 +196,36 @@ always @(posedge clk) begin
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end
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// output datapath logic
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reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}};
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reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}};
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reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
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{%- for p in ports %}
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reg output_{{p}}_axis_tvalid_reg = 1'b0, output_{{p}}_axis_tvalid_next;
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{%- endfor %}
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reg output_axis_tlast_reg = 1'b0;
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reg output_axis_tuser_reg = 1'b0;
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reg output_axis_tlast_reg = 1'b0;
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reg [ID_WIDTH-1:0] output_axis_tid_reg = {ID_WIDTH{1'b0}};
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reg [DEST_WIDTH-1:0] output_axis_tdest_reg = {DEST_WIDTH{1'b0}};
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reg [USER_WIDTH-1:0] output_axis_tuser_reg = {USER_WIDTH{1'b0}};
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reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = {DATA_WIDTH{1'b0}};
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reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = {DATA_WIDTH{1'b0}};
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reg [KEEP_WIDTH-1:0] temp_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
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reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next;
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reg temp_axis_tlast_reg = 1'b0;
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reg temp_axis_tuser_reg = 1'b0;
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reg temp_axis_tlast_reg = 1'b0;
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reg [ID_WIDTH-1:0] temp_axis_tid_reg = {ID_WIDTH{1'b0}};
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reg [DEST_WIDTH-1:0] temp_axis_tdest_reg = {DEST_WIDTH{1'b0}};
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reg [USER_WIDTH-1:0] temp_axis_tuser_reg = {USER_WIDTH{1'b0}};
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// datapath control
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reg store_axis_int_to_output;
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reg store_axis_int_to_temp;
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reg store_axis_temp_to_output;
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{% for p in ports %}
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assign output_{{p}}_axis_tdata = output_axis_tdata_reg;
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assign output_{{p}}_axis_tdata = output_axis_tdata_reg;
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assign output_{{p}}_axis_tkeep = KEEP_ENABLE ? output_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
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assign output_{{p}}_axis_tvalid = output_{{p}}_axis_tvalid_reg;
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assign output_{{p}}_axis_tlast = output_axis_tlast_reg;
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assign output_{{p}}_axis_tuser = output_axis_tuser_reg;
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assign output_{{p}}_axis_tlast = output_axis_tlast_reg;
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assign output_{{p}}_axis_tid = ID_ENABLE ? output_axis_tid_reg : {ID_WIDTH{1'b0}};
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assign output_{{p}}_axis_tdest = DEST_ENABLE ? output_axis_tdest_reg : {DEST_WIDTH{1'b0}};
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assign output_{{p}}_axis_tuser = USER_ENABLE ? output_axis_tuser_int : {USER_WIDTH{1'b0}};
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{% endfor %}
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// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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assign output_axis_tready_int_early = current_output_tready | (~temp_axis_tvalid_reg & (~current_output_tvalid | ~output_axis_tvalid_int));
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@ -211,7 +240,7 @@ always @* begin
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store_axis_int_to_output = 1'b0;
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store_axis_int_to_temp = 1'b0;
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store_axis_temp_to_output = 1'b0;
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if (output_axis_tready_int_reg) begin
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// input is ready
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if (current_output_tready | ~current_output_tvalid) begin
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@ -253,17 +282,26 @@ always @(posedge clk) begin
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// datapath
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if (store_axis_int_to_output) begin
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output_axis_tdata_reg <= output_axis_tdata_int;
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output_axis_tkeep_reg <= output_axis_tkeep_int;
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output_axis_tlast_reg <= output_axis_tlast_int;
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output_axis_tid_reg <= output_axis_tid_int;
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output_axis_tdest_reg <= output_axis_tdest_int;
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output_axis_tuser_reg <= output_axis_tuser_int;
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end else if (store_axis_temp_to_output) begin
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output_axis_tdata_reg <= temp_axis_tdata_reg;
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output_axis_tkeep_reg <= temp_axis_tkeep_reg;
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output_axis_tlast_reg <= temp_axis_tlast_reg;
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output_axis_tid_reg <= temp_axis_tid_reg;
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output_axis_tdest_reg <= temp_axis_tdest_reg;
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output_axis_tuser_reg <= temp_axis_tuser_reg;
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end
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if (store_axis_int_to_temp) begin
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temp_axis_tdata_reg <= output_axis_tdata_int;
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temp_axis_tkeep_reg <= output_axis_tkeep_int;
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temp_axis_tlast_reg <= output_axis_tlast_int;
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temp_axis_tid_reg <= output_axis_tid_int;
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temp_axis_tdest_reg <= output_axis_tdest_int;
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temp_axis_tuser_reg <= output_axis_tuser_int;
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end
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end
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@ -271,14 +309,14 @@ end
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endmodule
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""")
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output_file.write(t.render(
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n=ports,
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w=select_width,
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name=name,
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ports=range(ports)
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))
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print("Done")
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if __name__ == "__main__":
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@ -31,47 +31,70 @@ THE SOFTWARE.
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*/
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module axis_demux_4 #
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(
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parameter DATA_WIDTH = 8
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parameter DATA_WIDTH = 8,
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parameter KEEP_ENABLE = (DATA_WIDTH>8),
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parameter KEEP_WIDTH = (DATA_WIDTH/8),
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parameter ID_ENABLE = 0,
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parameter ID_WIDTH = 8,
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parameter DEST_ENABLE = 0,
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parameter DEST_WIDTH = 8,
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parameter USER_ENABLE = 1,
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parameter USER_WIDTH = 1
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI input
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*/
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input wire [DATA_WIDTH-1:0] input_axis_tdata,
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input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
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input wire input_axis_tvalid,
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output wire input_axis_tready,
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input wire input_axis_tlast,
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input wire input_axis_tuser,
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input wire [ID_WIDTH-1:0] input_axis_tid,
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input wire [DEST_WIDTH-1:0] input_axis_tdest,
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input wire [USER_WIDTH-1:0] input_axis_tuser,
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/*
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* AXI outputs
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*/
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output wire [DATA_WIDTH-1:0] output_0_axis_tdata,
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output wire [KEEP_WIDTH-1:0] output_0_axis_tkeep,
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output wire output_0_axis_tvalid,
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input wire output_0_axis_tready,
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output wire output_0_axis_tlast,
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output wire output_0_axis_tuser,
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output wire [ID_WIDTH-1:0] output_0_axis_tid,
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output wire [DEST_WIDTH-1:0] output_0_axis_tdest,
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output wire [USER_WIDTH-1:0] output_0_axis_tuser,
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output wire [DATA_WIDTH-1:0] output_1_axis_tdata,
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output wire [KEEP_WIDTH-1:0] output_1_axis_tkeep,
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output wire output_1_axis_tvalid,
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input wire output_1_axis_tready,
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output wire output_1_axis_tlast,
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output wire output_1_axis_tuser,
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output wire [ID_WIDTH-1:0] output_1_axis_tid,
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output wire [DEST_WIDTH-1:0] output_1_axis_tdest,
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output wire [USER_WIDTH-1:0] output_1_axis_tuser,
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output wire [DATA_WIDTH-1:0] output_2_axis_tdata,
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output wire [KEEP_WIDTH-1:0] output_2_axis_tkeep,
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output wire output_2_axis_tvalid,
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input wire output_2_axis_tready,
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output wire output_2_axis_tlast,
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output wire output_2_axis_tuser,
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output wire [ID_WIDTH-1:0] output_2_axis_tid,
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output wire [DEST_WIDTH-1:0] output_2_axis_tdest,
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output wire [USER_WIDTH-1:0] output_2_axis_tuser,
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output wire [DATA_WIDTH-1:0] output_3_axis_tdata,
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output wire [KEEP_WIDTH-1:0] output_3_axis_tkeep,
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output wire output_3_axis_tvalid,
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input wire output_3_axis_tready,
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output wire output_3_axis_tlast,
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output wire output_3_axis_tuser,
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output wire [ID_WIDTH-1:0] output_3_axis_tid,
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output wire [DEST_WIDTH-1:0] output_3_axis_tdest,
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output wire [USER_WIDTH-1:0] output_3_axis_tuser,
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/*
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* Control
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@ -86,12 +109,15 @@ reg frame_reg = 1'b0, frame_next;
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reg input_axis_tready_reg = 1'b0, input_axis_tready_next;
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// internal datapath
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reg [DATA_WIDTH-1:0] output_axis_tdata_int;
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reg output_axis_tvalid_int;
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reg output_axis_tready_int_reg = 1'b0;
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reg output_axis_tlast_int;
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reg output_axis_tuser_int;
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wire output_axis_tready_int_early;
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reg [DATA_WIDTH-1:0] output_axis_tdata_int;
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reg [KEEP_WIDTH-1:0] output_axis_tkeep_int;
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reg output_axis_tvalid_int;
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reg output_axis_tready_int_reg = 1'b0;
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reg output_axis_tlast_int;
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reg [ID_WIDTH-1:0] output_axis_tid_int;
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reg [DEST_WIDTH-1:0] output_axis_tdest_int;
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reg [USER_WIDTH-1:0] output_axis_tuser_int;
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wire output_axis_tready_int_early;
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assign input_axis_tready = input_axis_tready_reg;
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@ -144,10 +170,13 @@ always @* begin
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input_axis_tready_next = output_axis_tready_int_early & frame_next;
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output_axis_tdata_int = input_axis_tdata;
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output_axis_tdata_int = input_axis_tdata;
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output_axis_tkeep_int = input_axis_tkeep;
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output_axis_tvalid_int = input_axis_tvalid & input_axis_tready;
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output_axis_tlast_int = input_axis_tlast;
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output_axis_tuser_int = input_axis_tuser;
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output_axis_tlast_int = input_axis_tlast;
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output_axis_tid_int = input_axis_tid;
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output_axis_tdest_int = input_axis_tdest;
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output_axis_tuser_int = input_axis_tuser;
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end
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always @(posedge clk) begin
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@ -163,43 +192,61 @@ always @(posedge clk) begin
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end
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// output datapath logic
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reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}};
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reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}};
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reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
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reg output_0_axis_tvalid_reg = 1'b0, output_0_axis_tvalid_next;
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reg output_1_axis_tvalid_reg = 1'b0, output_1_axis_tvalid_next;
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reg output_2_axis_tvalid_reg = 1'b0, output_2_axis_tvalid_next;
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reg output_3_axis_tvalid_reg = 1'b0, output_3_axis_tvalid_next;
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reg output_axis_tlast_reg = 1'b0;
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reg output_axis_tuser_reg = 1'b0;
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reg output_axis_tlast_reg = 1'b0;
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reg [ID_WIDTH-1:0] output_axis_tid_reg = {ID_WIDTH{1'b0}};
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reg [DEST_WIDTH-1:0] output_axis_tdest_reg = {DEST_WIDTH{1'b0}};
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reg [USER_WIDTH-1:0] output_axis_tuser_reg = {USER_WIDTH{1'b0}};
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reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = {DATA_WIDTH{1'b0}};
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reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = {DATA_WIDTH{1'b0}};
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reg [KEEP_WIDTH-1:0] temp_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
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reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next;
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reg temp_axis_tlast_reg = 1'b0;
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reg temp_axis_tuser_reg = 1'b0;
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reg temp_axis_tlast_reg = 1'b0;
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reg [ID_WIDTH-1:0] temp_axis_tid_reg = {ID_WIDTH{1'b0}};
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reg [DEST_WIDTH-1:0] temp_axis_tdest_reg = {DEST_WIDTH{1'b0}};
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reg [USER_WIDTH-1:0] temp_axis_tuser_reg = {USER_WIDTH{1'b0}};
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// datapath control
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reg store_axis_int_to_output;
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reg store_axis_int_to_temp;
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reg store_axis_temp_to_output;
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assign output_0_axis_tdata = output_axis_tdata_reg;
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assign output_0_axis_tdata = output_axis_tdata_reg;
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assign output_0_axis_tkeep = KEEP_ENABLE ? output_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
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assign output_0_axis_tvalid = output_0_axis_tvalid_reg;
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assign output_0_axis_tlast = output_axis_tlast_reg;
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assign output_0_axis_tuser = output_axis_tuser_reg;
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assign output_0_axis_tlast = output_axis_tlast_reg;
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assign output_0_axis_tid = ID_ENABLE ? output_axis_tid_reg : {ID_WIDTH{1'b0}};
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assign output_0_axis_tdest = DEST_ENABLE ? output_axis_tdest_reg : {DEST_WIDTH{1'b0}};
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assign output_0_axis_tuser = USER_ENABLE ? output_axis_tuser_int : {USER_WIDTH{1'b0}};
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assign output_1_axis_tdata = output_axis_tdata_reg;
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assign output_1_axis_tdata = output_axis_tdata_reg;
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assign output_1_axis_tkeep = KEEP_ENABLE ? output_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
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assign output_1_axis_tvalid = output_1_axis_tvalid_reg;
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assign output_1_axis_tlast = output_axis_tlast_reg;
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assign output_1_axis_tuser = output_axis_tuser_reg;
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assign output_1_axis_tlast = output_axis_tlast_reg;
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assign output_1_axis_tid = ID_ENABLE ? output_axis_tid_reg : {ID_WIDTH{1'b0}};
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assign output_1_axis_tdest = DEST_ENABLE ? output_axis_tdest_reg : {DEST_WIDTH{1'b0}};
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assign output_1_axis_tuser = USER_ENABLE ? output_axis_tuser_int : {USER_WIDTH{1'b0}};
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|
||||
assign output_2_axis_tdata = output_axis_tdata_reg;
|
||||
assign output_2_axis_tdata = output_axis_tdata_reg;
|
||||
assign output_2_axis_tkeep = KEEP_ENABLE ? output_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
|
||||
assign output_2_axis_tvalid = output_2_axis_tvalid_reg;
|
||||
assign output_2_axis_tlast = output_axis_tlast_reg;
|
||||
assign output_2_axis_tuser = output_axis_tuser_reg;
|
||||
assign output_2_axis_tlast = output_axis_tlast_reg;
|
||||
assign output_2_axis_tid = ID_ENABLE ? output_axis_tid_reg : {ID_WIDTH{1'b0}};
|
||||
assign output_2_axis_tdest = DEST_ENABLE ? output_axis_tdest_reg : {DEST_WIDTH{1'b0}};
|
||||
assign output_2_axis_tuser = USER_ENABLE ? output_axis_tuser_int : {USER_WIDTH{1'b0}};
|
||||
|
||||
assign output_3_axis_tdata = output_axis_tdata_reg;
|
||||
assign output_3_axis_tdata = output_axis_tdata_reg;
|
||||
assign output_3_axis_tkeep = KEEP_ENABLE ? output_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
|
||||
assign output_3_axis_tvalid = output_3_axis_tvalid_reg;
|
||||
assign output_3_axis_tlast = output_axis_tlast_reg;
|
||||
assign output_3_axis_tuser = output_axis_tuser_reg;
|
||||
assign output_3_axis_tlast = output_axis_tlast_reg;
|
||||
assign output_3_axis_tid = ID_ENABLE ? output_axis_tid_reg : {ID_WIDTH{1'b0}};
|
||||
assign output_3_axis_tdest = DEST_ENABLE ? output_axis_tdest_reg : {DEST_WIDTH{1'b0}};
|
||||
assign output_3_axis_tuser = USER_ENABLE ? output_axis_tuser_int : {USER_WIDTH{1'b0}};
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
assign output_axis_tready_int_early = current_output_tready | (~temp_axis_tvalid_reg & (~current_output_tvalid | ~output_axis_tvalid_int));
|
||||
@ -215,7 +262,7 @@ always @* begin
|
||||
store_axis_int_to_output = 1'b0;
|
||||
store_axis_int_to_temp = 1'b0;
|
||||
store_axis_temp_to_output = 1'b0;
|
||||
|
||||
|
||||
if (output_axis_tready_int_reg) begin
|
||||
// input is ready
|
||||
if (current_output_tready | ~current_output_tvalid) begin
|
||||
@ -261,17 +308,26 @@ always @(posedge clk) begin
|
||||
// datapath
|
||||
if (store_axis_int_to_output) begin
|
||||
output_axis_tdata_reg <= output_axis_tdata_int;
|
||||
output_axis_tkeep_reg <= output_axis_tkeep_int;
|
||||
output_axis_tlast_reg <= output_axis_tlast_int;
|
||||
output_axis_tid_reg <= output_axis_tid_int;
|
||||
output_axis_tdest_reg <= output_axis_tdest_int;
|
||||
output_axis_tuser_reg <= output_axis_tuser_int;
|
||||
end else if (store_axis_temp_to_output) begin
|
||||
output_axis_tdata_reg <= temp_axis_tdata_reg;
|
||||
output_axis_tkeep_reg <= temp_axis_tkeep_reg;
|
||||
output_axis_tlast_reg <= temp_axis_tlast_reg;
|
||||
output_axis_tid_reg <= temp_axis_tid_reg;
|
||||
output_axis_tdest_reg <= temp_axis_tdest_reg;
|
||||
output_axis_tuser_reg <= temp_axis_tuser_reg;
|
||||
end
|
||||
|
||||
if (store_axis_int_to_temp) begin
|
||||
temp_axis_tdata_reg <= output_axis_tdata_int;
|
||||
temp_axis_tkeep_reg <= output_axis_tkeep_int;
|
||||
temp_axis_tlast_reg <= output_axis_tlast_int;
|
||||
temp_axis_tid_reg <= output_axis_tid_int;
|
||||
temp_axis_tdest_reg <= output_axis_tdest_int;
|
||||
temp_axis_tuser_reg <= output_axis_tuser_int;
|
||||
end
|
||||
end
|
||||
|
||||
@ -1,297 +0,0 @@
|
||||
#!/usr/bin/env python
|
||||
"""
|
||||
Generates an AXI Stream demux with the specified number of ports
|
||||
"""
|
||||
|
||||
from __future__ import print_function
|
||||
|
||||
import argparse
|
||||
import math
|
||||
from jinja2 import Template
|
||||
|
||||
def main():
|
||||
parser = argparse.ArgumentParser(description=__doc__.strip())
|
||||
parser.add_argument('-p', '--ports', type=int, default=4, help="number of ports")
|
||||
parser.add_argument('-n', '--name', type=str, help="module name")
|
||||
parser.add_argument('-o', '--output', type=str, help="output file name")
|
||||
|
||||
args = parser.parse_args()
|
||||
|
||||
try:
|
||||
generate(**args.__dict__)
|
||||
except IOError as ex:
|
||||
print(ex)
|
||||
exit(1)
|
||||
|
||||
def generate(ports=4, name=None, output=None):
|
||||
if name is None:
|
||||
name = "axis_demux_64_{0}".format(ports)
|
||||
|
||||
if output is None:
|
||||
output = name + ".v"
|
||||
|
||||
print("Opening file '{0}'...".format(output))
|
||||
|
||||
output_file = open(output, 'w')
|
||||
|
||||
print("Generating {0} port AXI Stream demux {1}...".format(ports, name))
|
||||
|
||||
select_width = int(math.ceil(math.log(ports, 2)))
|
||||
|
||||
t = Template(u"""/*
|
||||
|
||||
Copyright (c) 2014-2017 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* AXI4-Stream {{n}} port demultiplexer (64 bit datapath)
|
||||
*/
|
||||
module {{name}} #
|
||||
(
|
||||
parameter DATA_WIDTH = 64,
|
||||
parameter KEEP_WIDTH = (DATA_WIDTH/8)
|
||||
)
|
||||
(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
|
||||
/*
|
||||
* AXI input
|
||||
*/
|
||||
input wire [DATA_WIDTH-1:0] input_axis_tdata,
|
||||
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
|
||||
input wire input_axis_tvalid,
|
||||
output wire input_axis_tready,
|
||||
input wire input_axis_tlast,
|
||||
input wire input_axis_tuser,
|
||||
|
||||
/*
|
||||
* AXI outputs
|
||||
*/
|
||||
{%- for p in ports %}
|
||||
output wire [DATA_WIDTH-1:0] output_{{p}}_axis_tdata,
|
||||
output wire [KEEP_WIDTH-1:0] output_{{p}}_axis_tkeep,
|
||||
output wire output_{{p}}_axis_tvalid,
|
||||
input wire output_{{p}}_axis_tready,
|
||||
output wire output_{{p}}_axis_tlast,
|
||||
output wire output_{{p}}_axis_tuser,
|
||||
{% endfor %}
|
||||
/*
|
||||
* Control
|
||||
*/
|
||||
input wire enable,
|
||||
input wire [{{w-1}}:0] select
|
||||
);
|
||||
|
||||
reg [{{w-1}}:0] select_reg = {{w}}'d0, select_next;
|
||||
reg frame_reg = 1'b0, frame_next;
|
||||
|
||||
reg input_axis_tready_reg = 1'b0, input_axis_tready_next;
|
||||
|
||||
// internal datapath
|
||||
reg [DATA_WIDTH-1:0] output_axis_tdata_int;
|
||||
reg [KEEP_WIDTH-1:0] output_axis_tkeep_int;
|
||||
reg output_axis_tvalid_int;
|
||||
reg output_axis_tready_int_reg = 1'b0;
|
||||
reg output_axis_tlast_int;
|
||||
reg output_axis_tuser_int;
|
||||
wire output_axis_tready_int_early;
|
||||
|
||||
assign input_axis_tready = input_axis_tready_reg;
|
||||
|
||||
// mux for output control signals
|
||||
reg current_output_tready;
|
||||
reg current_output_tvalid;
|
||||
always @* begin
|
||||
case (select_reg)
|
||||
{%- for p in ports %}
|
||||
{{w}}'d{{p}}: begin
|
||||
current_output_tvalid = output_{{p}}_axis_tvalid;
|
||||
current_output_tready = output_{{p}}_axis_tready;
|
||||
end
|
||||
{%- endfor %}
|
||||
default: begin
|
||||
current_output_tvalid = 1'b0;
|
||||
current_output_tready = 1'b0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always @* begin
|
||||
select_next = select_reg;
|
||||
frame_next = frame_reg;
|
||||
|
||||
input_axis_tready_next = 1'b0;
|
||||
|
||||
if (input_axis_tvalid & input_axis_tready) begin
|
||||
// end of frame detection
|
||||
if (input_axis_tlast) begin
|
||||
frame_next = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
if (~frame_reg & enable & input_axis_tvalid & ~current_output_tvalid) begin
|
||||
// start of frame, grab select value
|
||||
frame_next = 1'b1;
|
||||
select_next = select;
|
||||
end
|
||||
|
||||
input_axis_tready_next = output_axis_tready_int_early & frame_next;
|
||||
|
||||
output_axis_tdata_int = input_axis_tdata;
|
||||
output_axis_tkeep_int = input_axis_tkeep;
|
||||
output_axis_tvalid_int = input_axis_tvalid & input_axis_tready;
|
||||
output_axis_tlast_int = input_axis_tlast;
|
||||
output_axis_tuser_int = input_axis_tuser;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
select_reg <= {{w}}'d0;
|
||||
frame_reg <= 1'b0;
|
||||
input_axis_tready_reg <= 1'b0;
|
||||
end else begin
|
||||
select_reg <= select_next;
|
||||
frame_reg <= frame_next;
|
||||
input_axis_tready_reg <= input_axis_tready_next;
|
||||
end
|
||||
end
|
||||
|
||||
// output datapath logic
|
||||
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}};
|
||||
reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
|
||||
{%- for p in ports %}
|
||||
reg output_{{p}}_axis_tvalid_reg = 1'b0, output_{{p}}_axis_tvalid_next;
|
||||
{%- endfor %}
|
||||
reg output_axis_tlast_reg = 1'b0;
|
||||
reg output_axis_tuser_reg = 1'b0;
|
||||
|
||||
reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = {DATA_WIDTH{1'b0}};
|
||||
reg [KEEP_WIDTH-1:0] temp_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
|
||||
reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next;
|
||||
reg temp_axis_tlast_reg = 1'b0;
|
||||
reg temp_axis_tuser_reg = 1'b0;
|
||||
|
||||
// datapath control
|
||||
reg store_axis_int_to_output;
|
||||
reg store_axis_int_to_temp;
|
||||
reg store_axis_temp_to_output;
|
||||
{% for p in ports %}
|
||||
assign output_{{p}}_axis_tdata = output_axis_tdata_reg;
|
||||
assign output_{{p}}_axis_tkeep = output_axis_tkeep_reg;
|
||||
assign output_{{p}}_axis_tvalid = output_{{p}}_axis_tvalid_reg;
|
||||
assign output_{{p}}_axis_tlast = output_axis_tlast_reg;
|
||||
assign output_{{p}}_axis_tuser = output_axis_tuser_reg;
|
||||
{% endfor %}
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
assign output_axis_tready_int_early = current_output_tready | (~temp_axis_tvalid_reg & (~current_output_tvalid | ~output_axis_tvalid_int));
|
||||
|
||||
always @* begin
|
||||
// transfer sink ready state to source
|
||||
{%- for p in ports %}
|
||||
output_{{p}}_axis_tvalid_next = output_{{p}}_axis_tvalid_reg;
|
||||
{%- endfor %}
|
||||
temp_axis_tvalid_next = temp_axis_tvalid_reg;
|
||||
|
||||
store_axis_int_to_output = 1'b0;
|
||||
store_axis_int_to_temp = 1'b0;
|
||||
store_axis_temp_to_output = 1'b0;
|
||||
|
||||
if (output_axis_tready_int_reg) begin
|
||||
// input is ready
|
||||
if (current_output_tready | ~current_output_tvalid) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
{%- for p in ports %}
|
||||
output_{{p}}_axis_tvalid_next = output_axis_tvalid_int & (select_reg == {{w}}'d{{p}});
|
||||
{%- endfor %}
|
||||
store_axis_int_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_axis_tvalid_next = output_axis_tvalid_int;
|
||||
store_axis_int_to_temp = 1'b1;
|
||||
end
|
||||
end else if (current_output_tready) begin
|
||||
// input is not ready, but output is ready
|
||||
{%- for p in ports %}
|
||||
output_{{p}}_axis_tvalid_next = temp_axis_tvalid_reg & (select_reg == {{w}}'d{{p}});
|
||||
{%- endfor %}
|
||||
temp_axis_tvalid_next = 1'b0;
|
||||
store_axis_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
{%- for p in ports %}
|
||||
output_{{p}}_axis_tvalid_reg <= 1'b0;
|
||||
{%- endfor %}
|
||||
output_axis_tready_int_reg <= 1'b0;
|
||||
temp_axis_tvalid_reg <= 1'b0;
|
||||
end else begin
|
||||
{%- for p in ports %}
|
||||
output_{{p}}_axis_tvalid_reg <= output_{{p}}_axis_tvalid_next;
|
||||
{%- endfor %}
|
||||
output_axis_tready_int_reg <= output_axis_tready_int_early;
|
||||
temp_axis_tvalid_reg <= temp_axis_tvalid_next;
|
||||
end
|
||||
|
||||
// datapath
|
||||
if (store_axis_int_to_output) begin
|
||||
output_axis_tdata_reg <= output_axis_tdata_int;
|
||||
output_axis_tkeep_reg <= output_axis_tkeep_int;
|
||||
output_axis_tlast_reg <= output_axis_tlast_int;
|
||||
output_axis_tuser_reg <= output_axis_tuser_int;
|
||||
end else if (store_axis_temp_to_output) begin
|
||||
output_axis_tdata_reg <= temp_axis_tdata_reg;
|
||||
output_axis_tkeep_reg <= temp_axis_tkeep_reg;
|
||||
output_axis_tlast_reg <= temp_axis_tlast_reg;
|
||||
output_axis_tuser_reg <= temp_axis_tuser_reg;
|
||||
end
|
||||
|
||||
if (store_axis_int_to_temp) begin
|
||||
temp_axis_tdata_reg <= output_axis_tdata_int;
|
||||
temp_axis_tkeep_reg <= output_axis_tkeep_int;
|
||||
temp_axis_tlast_reg <= output_axis_tlast_int;
|
||||
temp_axis_tuser_reg <= output_axis_tuser_int;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
""")
|
||||
|
||||
output_file.write(t.render(
|
||||
n=ports,
|
||||
w=select_width,
|
||||
name=name,
|
||||
ports=range(ports)
|
||||
))
|
||||
|
||||
print("Done")
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
|
||||
@ -1,296 +0,0 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2017 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* AXI4-Stream 4 port demultiplexer (64 bit datapath)
|
||||
*/
|
||||
module axis_demux_64_4 #
|
||||
(
|
||||
parameter DATA_WIDTH = 64,
|
||||
parameter KEEP_WIDTH = (DATA_WIDTH/8)
|
||||
)
|
||||
(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
|
||||
/*
|
||||
* AXI input
|
||||
*/
|
||||
input wire [DATA_WIDTH-1:0] input_axis_tdata,
|
||||
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
|
||||
input wire input_axis_tvalid,
|
||||
output wire input_axis_tready,
|
||||
input wire input_axis_tlast,
|
||||
input wire input_axis_tuser,
|
||||
|
||||
/*
|
||||
* AXI outputs
|
||||
*/
|
||||
output wire [DATA_WIDTH-1:0] output_0_axis_tdata,
|
||||
output wire [KEEP_WIDTH-1:0] output_0_axis_tkeep,
|
||||
output wire output_0_axis_tvalid,
|
||||
input wire output_0_axis_tready,
|
||||
output wire output_0_axis_tlast,
|
||||
output wire output_0_axis_tuser,
|
||||
|
||||
output wire [DATA_WIDTH-1:0] output_1_axis_tdata,
|
||||
output wire [KEEP_WIDTH-1:0] output_1_axis_tkeep,
|
||||
output wire output_1_axis_tvalid,
|
||||
input wire output_1_axis_tready,
|
||||
output wire output_1_axis_tlast,
|
||||
output wire output_1_axis_tuser,
|
||||
|
||||
output wire [DATA_WIDTH-1:0] output_2_axis_tdata,
|
||||
output wire [KEEP_WIDTH-1:0] output_2_axis_tkeep,
|
||||
output wire output_2_axis_tvalid,
|
||||
input wire output_2_axis_tready,
|
||||
output wire output_2_axis_tlast,
|
||||
output wire output_2_axis_tuser,
|
||||
|
||||
output wire [DATA_WIDTH-1:0] output_3_axis_tdata,
|
||||
output wire [KEEP_WIDTH-1:0] output_3_axis_tkeep,
|
||||
output wire output_3_axis_tvalid,
|
||||
input wire output_3_axis_tready,
|
||||
output wire output_3_axis_tlast,
|
||||
output wire output_3_axis_tuser,
|
||||
|
||||
/*
|
||||
* Control
|
||||
*/
|
||||
input wire enable,
|
||||
input wire [1:0] select
|
||||
);
|
||||
|
||||
reg [1:0] select_reg = 2'd0, select_next;
|
||||
reg frame_reg = 1'b0, frame_next;
|
||||
|
||||
reg input_axis_tready_reg = 1'b0, input_axis_tready_next;
|
||||
|
||||
// internal datapath
|
||||
reg [DATA_WIDTH-1:0] output_axis_tdata_int;
|
||||
reg [KEEP_WIDTH-1:0] output_axis_tkeep_int;
|
||||
reg output_axis_tvalid_int;
|
||||
reg output_axis_tready_int_reg = 1'b0;
|
||||
reg output_axis_tlast_int;
|
||||
reg output_axis_tuser_int;
|
||||
wire output_axis_tready_int_early;
|
||||
|
||||
assign input_axis_tready = input_axis_tready_reg;
|
||||
|
||||
// mux for output control signals
|
||||
reg current_output_tready;
|
||||
reg current_output_tvalid;
|
||||
always @* begin
|
||||
case (select_reg)
|
||||
2'd0: begin
|
||||
current_output_tvalid = output_0_axis_tvalid;
|
||||
current_output_tready = output_0_axis_tready;
|
||||
end
|
||||
2'd1: begin
|
||||
current_output_tvalid = output_1_axis_tvalid;
|
||||
current_output_tready = output_1_axis_tready;
|
||||
end
|
||||
2'd2: begin
|
||||
current_output_tvalid = output_2_axis_tvalid;
|
||||
current_output_tready = output_2_axis_tready;
|
||||
end
|
||||
2'd3: begin
|
||||
current_output_tvalid = output_3_axis_tvalid;
|
||||
current_output_tready = output_3_axis_tready;
|
||||
end
|
||||
default: begin
|
||||
current_output_tvalid = 1'b0;
|
||||
current_output_tready = 1'b0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always @* begin
|
||||
select_next = select_reg;
|
||||
frame_next = frame_reg;
|
||||
|
||||
input_axis_tready_next = 1'b0;
|
||||
|
||||
if (input_axis_tvalid & input_axis_tready) begin
|
||||
// end of frame detection
|
||||
if (input_axis_tlast) begin
|
||||
frame_next = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
if (~frame_reg & enable & input_axis_tvalid & ~current_output_tvalid) begin
|
||||
// start of frame, grab select value
|
||||
frame_next = 1'b1;
|
||||
select_next = select;
|
||||
end
|
||||
|
||||
input_axis_tready_next = output_axis_tready_int_early & frame_next;
|
||||
|
||||
output_axis_tdata_int = input_axis_tdata;
|
||||
output_axis_tkeep_int = input_axis_tkeep;
|
||||
output_axis_tvalid_int = input_axis_tvalid & input_axis_tready;
|
||||
output_axis_tlast_int = input_axis_tlast;
|
||||
output_axis_tuser_int = input_axis_tuser;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
select_reg <= 2'd0;
|
||||
frame_reg <= 1'b0;
|
||||
input_axis_tready_reg <= 1'b0;
|
||||
end else begin
|
||||
select_reg <= select_next;
|
||||
frame_reg <= frame_next;
|
||||
input_axis_tready_reg <= input_axis_tready_next;
|
||||
end
|
||||
end
|
||||
|
||||
// output datapath logic
|
||||
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}};
|
||||
reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
|
||||
reg output_0_axis_tvalid_reg = 1'b0, output_0_axis_tvalid_next;
|
||||
reg output_1_axis_tvalid_reg = 1'b0, output_1_axis_tvalid_next;
|
||||
reg output_2_axis_tvalid_reg = 1'b0, output_2_axis_tvalid_next;
|
||||
reg output_3_axis_tvalid_reg = 1'b0, output_3_axis_tvalid_next;
|
||||
reg output_axis_tlast_reg = 1'b0;
|
||||
reg output_axis_tuser_reg = 1'b0;
|
||||
|
||||
reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = {DATA_WIDTH{1'b0}};
|
||||
reg [KEEP_WIDTH-1:0] temp_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
|
||||
reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next;
|
||||
reg temp_axis_tlast_reg = 1'b0;
|
||||
reg temp_axis_tuser_reg = 1'b0;
|
||||
|
||||
// datapath control
|
||||
reg store_axis_int_to_output;
|
||||
reg store_axis_int_to_temp;
|
||||
reg store_axis_temp_to_output;
|
||||
|
||||
assign output_0_axis_tdata = output_axis_tdata_reg;
|
||||
assign output_0_axis_tkeep = output_axis_tkeep_reg;
|
||||
assign output_0_axis_tvalid = output_0_axis_tvalid_reg;
|
||||
assign output_0_axis_tlast = output_axis_tlast_reg;
|
||||
assign output_0_axis_tuser = output_axis_tuser_reg;
|
||||
|
||||
assign output_1_axis_tdata = output_axis_tdata_reg;
|
||||
assign output_1_axis_tkeep = output_axis_tkeep_reg;
|
||||
assign output_1_axis_tvalid = output_1_axis_tvalid_reg;
|
||||
assign output_1_axis_tlast = output_axis_tlast_reg;
|
||||
assign output_1_axis_tuser = output_axis_tuser_reg;
|
||||
|
||||
assign output_2_axis_tdata = output_axis_tdata_reg;
|
||||
assign output_2_axis_tkeep = output_axis_tkeep_reg;
|
||||
assign output_2_axis_tvalid = output_2_axis_tvalid_reg;
|
||||
assign output_2_axis_tlast = output_axis_tlast_reg;
|
||||
assign output_2_axis_tuser = output_axis_tuser_reg;
|
||||
|
||||
assign output_3_axis_tdata = output_axis_tdata_reg;
|
||||
assign output_3_axis_tkeep = output_axis_tkeep_reg;
|
||||
assign output_3_axis_tvalid = output_3_axis_tvalid_reg;
|
||||
assign output_3_axis_tlast = output_axis_tlast_reg;
|
||||
assign output_3_axis_tuser = output_axis_tuser_reg;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
assign output_axis_tready_int_early = current_output_tready | (~temp_axis_tvalid_reg & (~current_output_tvalid | ~output_axis_tvalid_int));
|
||||
|
||||
always @* begin
|
||||
// transfer sink ready state to source
|
||||
output_0_axis_tvalid_next = output_0_axis_tvalid_reg;
|
||||
output_1_axis_tvalid_next = output_1_axis_tvalid_reg;
|
||||
output_2_axis_tvalid_next = output_2_axis_tvalid_reg;
|
||||
output_3_axis_tvalid_next = output_3_axis_tvalid_reg;
|
||||
temp_axis_tvalid_next = temp_axis_tvalid_reg;
|
||||
|
||||
store_axis_int_to_output = 1'b0;
|
||||
store_axis_int_to_temp = 1'b0;
|
||||
store_axis_temp_to_output = 1'b0;
|
||||
|
||||
if (output_axis_tready_int_reg) begin
|
||||
// input is ready
|
||||
if (current_output_tready | ~current_output_tvalid) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
output_0_axis_tvalid_next = output_axis_tvalid_int & (select_reg == 2'd0);
|
||||
output_1_axis_tvalid_next = output_axis_tvalid_int & (select_reg == 2'd1);
|
||||
output_2_axis_tvalid_next = output_axis_tvalid_int & (select_reg == 2'd2);
|
||||
output_3_axis_tvalid_next = output_axis_tvalid_int & (select_reg == 2'd3);
|
||||
store_axis_int_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_axis_tvalid_next = output_axis_tvalid_int;
|
||||
store_axis_int_to_temp = 1'b1;
|
||||
end
|
||||
end else if (current_output_tready) begin
|
||||
// input is not ready, but output is ready
|
||||
output_0_axis_tvalid_next = temp_axis_tvalid_reg & (select_reg == 2'd0);
|
||||
output_1_axis_tvalid_next = temp_axis_tvalid_reg & (select_reg == 2'd1);
|
||||
output_2_axis_tvalid_next = temp_axis_tvalid_reg & (select_reg == 2'd2);
|
||||
output_3_axis_tvalid_next = temp_axis_tvalid_reg & (select_reg == 2'd3);
|
||||
temp_axis_tvalid_next = 1'b0;
|
||||
store_axis_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
output_0_axis_tvalid_reg <= 1'b0;
|
||||
output_1_axis_tvalid_reg <= 1'b0;
|
||||
output_2_axis_tvalid_reg <= 1'b0;
|
||||
output_3_axis_tvalid_reg <= 1'b0;
|
||||
output_axis_tready_int_reg <= 1'b0;
|
||||
temp_axis_tvalid_reg <= 1'b0;
|
||||
end else begin
|
||||
output_0_axis_tvalid_reg <= output_0_axis_tvalid_next;
|
||||
output_1_axis_tvalid_reg <= output_1_axis_tvalid_next;
|
||||
output_2_axis_tvalid_reg <= output_2_axis_tvalid_next;
|
||||
output_3_axis_tvalid_reg <= output_3_axis_tvalid_next;
|
||||
output_axis_tready_int_reg <= output_axis_tready_int_early;
|
||||
temp_axis_tvalid_reg <= temp_axis_tvalid_next;
|
||||
end
|
||||
|
||||
// datapath
|
||||
if (store_axis_int_to_output) begin
|
||||
output_axis_tdata_reg <= output_axis_tdata_int;
|
||||
output_axis_tkeep_reg <= output_axis_tkeep_int;
|
||||
output_axis_tlast_reg <= output_axis_tlast_int;
|
||||
output_axis_tuser_reg <= output_axis_tuser_int;
|
||||
end else if (store_axis_temp_to_output) begin
|
||||
output_axis_tdata_reg <= temp_axis_tdata_reg;
|
||||
output_axis_tkeep_reg <= temp_axis_tkeep_reg;
|
||||
output_axis_tlast_reg <= temp_axis_tlast_reg;
|
||||
output_axis_tuser_reg <= temp_axis_tuser_reg;
|
||||
end
|
||||
|
||||
if (store_axis_int_to_temp) begin
|
||||
temp_axis_tdata_reg <= output_axis_tdata_int;
|
||||
temp_axis_tkeep_reg <= output_axis_tkeep_int;
|
||||
temp_axis_tlast_reg <= output_axis_tlast_int;
|
||||
temp_axis_tuser_reg <= output_axis_tuser_int;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@ -44,6 +44,14 @@ def bench():
|
||||
|
||||
# Parameters
|
||||
DATA_WIDTH = 8
|
||||
KEEP_ENABLE = (DATA_WIDTH>8)
|
||||
KEEP_WIDTH = (DATA_WIDTH/8)
|
||||
ID_ENABLE = 1
|
||||
ID_WIDTH = 8
|
||||
DEST_ENABLE = 1
|
||||
DEST_WIDTH = 8
|
||||
USER_ENABLE = 1
|
||||
USER_WIDTH = 1
|
||||
|
||||
# Inputs
|
||||
clk = Signal(bool(0))
|
||||
@ -51,9 +59,12 @@ def bench():
|
||||
current_test = Signal(intbv(0)[8:])
|
||||
|
||||
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
|
||||
input_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
|
||||
input_axis_tvalid = Signal(bool(0))
|
||||
input_axis_tlast = Signal(bool(0))
|
||||
input_axis_tuser = Signal(bool(0))
|
||||
input_axis_tid = Signal(intbv(0)[ID_WIDTH:])
|
||||
input_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
|
||||
input_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
|
||||
|
||||
output_0_axis_tready = Signal(bool(0))
|
||||
output_1_axis_tready = Signal(bool(0))
|
||||
@ -67,21 +78,33 @@ def bench():
|
||||
input_axis_tready = Signal(bool(0))
|
||||
|
||||
output_0_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
|
||||
output_0_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
|
||||
output_0_axis_tvalid = Signal(bool(0))
|
||||
output_0_axis_tlast = Signal(bool(0))
|
||||
output_0_axis_tuser = Signal(bool(0))
|
||||
output_0_axis_tid = Signal(intbv(0)[ID_WIDTH:])
|
||||
output_0_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
|
||||
output_0_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
|
||||
output_1_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
|
||||
output_1_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
|
||||
output_1_axis_tvalid = Signal(bool(0))
|
||||
output_1_axis_tlast = Signal(bool(0))
|
||||
output_1_axis_tuser = Signal(bool(0))
|
||||
output_1_axis_tid = Signal(intbv(0)[ID_WIDTH:])
|
||||
output_1_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
|
||||
output_1_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
|
||||
output_2_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
|
||||
output_2_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
|
||||
output_2_axis_tvalid = Signal(bool(0))
|
||||
output_2_axis_tlast = Signal(bool(0))
|
||||
output_2_axis_tuser = Signal(bool(0))
|
||||
output_2_axis_tid = Signal(intbv(0)[ID_WIDTH:])
|
||||
output_2_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
|
||||
output_2_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
|
||||
output_3_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
|
||||
output_3_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
|
||||
output_3_axis_tvalid = Signal(bool(0))
|
||||
output_3_axis_tlast = Signal(bool(0))
|
||||
output_3_axis_tuser = Signal(bool(0))
|
||||
output_3_axis_tid = Signal(intbv(0)[ID_WIDTH:])
|
||||
output_3_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
|
||||
output_3_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
|
||||
|
||||
# sources and sinks
|
||||
source_pause = Signal(bool(0))
|
||||
@ -96,9 +119,12 @@ def bench():
|
||||
clk,
|
||||
rst,
|
||||
tdata=input_axis_tdata,
|
||||
tkeep=input_axis_tkeep,
|
||||
tvalid=input_axis_tvalid,
|
||||
tready=input_axis_tready,
|
||||
tlast=input_axis_tlast,
|
||||
tid=input_axis_tid,
|
||||
tdest=input_axis_tdest,
|
||||
tuser=input_axis_tuser,
|
||||
pause=source_pause,
|
||||
name='source'
|
||||
@ -110,9 +136,12 @@ def bench():
|
||||
clk,
|
||||
rst,
|
||||
tdata=output_0_axis_tdata,
|
||||
tkeep=output_0_axis_tkeep,
|
||||
tvalid=output_0_axis_tvalid,
|
||||
tready=output_0_axis_tready,
|
||||
tlast=output_0_axis_tlast,
|
||||
tid=output_0_axis_tid,
|
||||
tdest=output_0_axis_tdest,
|
||||
tuser=output_0_axis_tuser,
|
||||
pause=sink_0_pause,
|
||||
name='sink_0'
|
||||
@ -124,9 +153,12 @@ def bench():
|
||||
clk,
|
||||
rst,
|
||||
tdata=output_1_axis_tdata,
|
||||
tkeep=output_1_axis_tkeep,
|
||||
tvalid=output_1_axis_tvalid,
|
||||
tready=output_1_axis_tready,
|
||||
tlast=output_1_axis_tlast,
|
||||
tid=output_1_axis_tid,
|
||||
tdest=output_1_axis_tdest,
|
||||
tuser=output_1_axis_tuser,
|
||||
pause=sink_1_pause,
|
||||
name='sink_1'
|
||||
@ -138,9 +170,12 @@ def bench():
|
||||
clk,
|
||||
rst,
|
||||
tdata=output_2_axis_tdata,
|
||||
tkeep=output_2_axis_tkeep,
|
||||
tvalid=output_2_axis_tvalid,
|
||||
tready=output_2_axis_tready,
|
||||
tlast=output_2_axis_tlast,
|
||||
tid=output_2_axis_tid,
|
||||
tdest=output_2_axis_tdest,
|
||||
tuser=output_2_axis_tuser,
|
||||
pause=sink_2_pause,
|
||||
name='sink_2'
|
||||
@ -152,9 +187,12 @@ def bench():
|
||||
clk,
|
||||
rst,
|
||||
tdata=output_3_axis_tdata,
|
||||
tkeep=output_3_axis_tkeep,
|
||||
tvalid=output_3_axis_tvalid,
|
||||
tready=output_3_axis_tready,
|
||||
tlast=output_3_axis_tlast,
|
||||
tid=output_3_axis_tid,
|
||||
tdest=output_3_axis_tdest,
|
||||
tuser=output_3_axis_tuser,
|
||||
pause=sink_3_pause,
|
||||
name='sink_3'
|
||||
@ -171,30 +209,45 @@ def bench():
|
||||
current_test=current_test,
|
||||
|
||||
input_axis_tdata=input_axis_tdata,
|
||||
input_axis_tkeep=input_axis_tkeep,
|
||||
input_axis_tvalid=input_axis_tvalid,
|
||||
input_axis_tready=input_axis_tready,
|
||||
input_axis_tlast=input_axis_tlast,
|
||||
input_axis_tid=input_axis_tid,
|
||||
input_axis_tdest=input_axis_tdest,
|
||||
input_axis_tuser=input_axis_tuser,
|
||||
|
||||
output_0_axis_tdata=output_0_axis_tdata,
|
||||
output_0_axis_tkeep=output_0_axis_tkeep,
|
||||
output_0_axis_tvalid=output_0_axis_tvalid,
|
||||
output_0_axis_tready=output_0_axis_tready,
|
||||
output_0_axis_tlast=output_0_axis_tlast,
|
||||
output_0_axis_tid=output_0_axis_tid,
|
||||
output_0_axis_tdest=output_0_axis_tdest,
|
||||
output_0_axis_tuser=output_0_axis_tuser,
|
||||
output_1_axis_tdata=output_1_axis_tdata,
|
||||
output_1_axis_tkeep=output_1_axis_tkeep,
|
||||
output_1_axis_tvalid=output_1_axis_tvalid,
|
||||
output_1_axis_tready=output_1_axis_tready,
|
||||
output_1_axis_tlast=output_1_axis_tlast,
|
||||
output_1_axis_tid=output_1_axis_tid,
|
||||
output_1_axis_tdest=output_1_axis_tdest,
|
||||
output_1_axis_tuser=output_1_axis_tuser,
|
||||
output_2_axis_tdata=output_2_axis_tdata,
|
||||
output_2_axis_tkeep=output_2_axis_tkeep,
|
||||
output_2_axis_tvalid=output_2_axis_tvalid,
|
||||
output_2_axis_tready=output_2_axis_tready,
|
||||
output_2_axis_tlast=output_2_axis_tlast,
|
||||
output_2_axis_tid=output_2_axis_tid,
|
||||
output_2_axis_tdest=output_2_axis_tdest,
|
||||
output_2_axis_tuser=output_2_axis_tuser,
|
||||
output_3_axis_tdata=output_3_axis_tdata,
|
||||
output_3_axis_tkeep=output_3_axis_tkeep,
|
||||
output_3_axis_tvalid=output_3_axis_tvalid,
|
||||
output_3_axis_tready=output_3_axis_tready,
|
||||
output_3_axis_tlast=output_3_axis_tlast,
|
||||
output_3_axis_tid=output_3_axis_tid,
|
||||
output_3_axis_tdest=output_3_axis_tdest,
|
||||
output_3_axis_tuser=output_3_axis_tuser,
|
||||
|
||||
enable=enable,
|
||||
@ -225,10 +278,15 @@ def bench():
|
||||
|
||||
select.next = 0
|
||||
|
||||
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame = axis_ep.AXIStreamFrame(
|
||||
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
|
||||
id=1,
|
||||
dest=1
|
||||
)
|
||||
|
||||
source.send(test_frame)
|
||||
yield clk.posedge
|
||||
|
||||
@ -249,10 +307,15 @@ def bench():
|
||||
|
||||
select.next = 1
|
||||
|
||||
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame = axis_ep.AXIStreamFrame(
|
||||
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
|
||||
id=2,
|
||||
dest=1
|
||||
)
|
||||
|
||||
source.send(test_frame)
|
||||
yield clk.posedge
|
||||
|
||||
@ -273,14 +336,23 @@ def bench():
|
||||
|
||||
select.next = 0
|
||||
|
||||
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame1 = axis_ep.AXIStreamFrame(
|
||||
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
|
||||
id=3,
|
||||
dest=1
|
||||
)
|
||||
test_frame2 = axis_ep.AXIStreamFrame(
|
||||
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
|
||||
id=3,
|
||||
dest=2
|
||||
)
|
||||
|
||||
source.send(test_frame1)
|
||||
source.send(test_frame2)
|
||||
yield clk.posedge
|
||||
@ -306,14 +378,23 @@ def bench():
|
||||
|
||||
select.next = 1
|
||||
|
||||
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame1 = axis_ep.AXIStreamFrame(
|
||||
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
|
||||
id=4,
|
||||
dest=1
|
||||
)
|
||||
test_frame2 = axis_ep.AXIStreamFrame(
|
||||
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
|
||||
id=4,
|
||||
dest=2
|
||||
)
|
||||
|
||||
source.send(test_frame1)
|
||||
source.send(test_frame2)
|
||||
yield clk.posedge
|
||||
@ -340,14 +421,23 @@ def bench():
|
||||
|
||||
select.next = 1
|
||||
|
||||
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame1 = axis_ep.AXIStreamFrame(
|
||||
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
|
||||
id=5,
|
||||
dest=1
|
||||
)
|
||||
test_frame2 = axis_ep.AXIStreamFrame(
|
||||
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
|
||||
id=5,
|
||||
dest=2
|
||||
)
|
||||
|
||||
source.send(test_frame1)
|
||||
source.send(test_frame2)
|
||||
yield clk.posedge
|
||||
@ -379,14 +469,23 @@ def bench():
|
||||
|
||||
select.next = 1
|
||||
|
||||
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame1 = axis_ep.AXIStreamFrame(
|
||||
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
|
||||
id=6,
|
||||
dest=1
|
||||
)
|
||||
test_frame2 = axis_ep.AXIStreamFrame(
|
||||
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
|
||||
id=6,
|
||||
dest=2
|
||||
)
|
||||
|
||||
source.send(test_frame1)
|
||||
source.send(test_frame2)
|
||||
yield clk.posedge
|
||||
|
||||
@ -33,6 +33,14 @@ module test_axis_demux_4;
|
||||
|
||||
// Parameters
|
||||
parameter DATA_WIDTH = 8;
|
||||
parameter KEEP_ENABLE = (DATA_WIDTH>8);
|
||||
parameter KEEP_WIDTH = (DATA_WIDTH/8);
|
||||
parameter ID_ENABLE = 1;
|
||||
parameter ID_WIDTH = 8;
|
||||
parameter DEST_ENABLE = 1;
|
||||
parameter DEST_WIDTH = 8;
|
||||
parameter USER_ENABLE = 1;
|
||||
parameter USER_WIDTH = 1;
|
||||
|
||||
// Inputs
|
||||
reg clk = 0;
|
||||
@ -40,9 +48,12 @@ reg rst = 0;
|
||||
reg [7:0] current_test = 0;
|
||||
|
||||
reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
|
||||
reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0;
|
||||
reg input_axis_tvalid = 0;
|
||||
reg input_axis_tlast = 0;
|
||||
reg input_axis_tuser = 0;
|
||||
reg [ID_WIDTH-1:0] input_axis_tid = 0;
|
||||
reg [DEST_WIDTH-1:0] input_axis_tdest = 0;
|
||||
reg [USER_WIDTH-1:0] input_axis_tuser = 0;
|
||||
|
||||
reg output_0_axis_tready = 0;
|
||||
reg output_1_axis_tready = 0;
|
||||
@ -56,21 +67,33 @@ reg [1:0] select = 0;
|
||||
wire input_axis_tready;
|
||||
|
||||
wire [DATA_WIDTH-1:0] output_0_axis_tdata;
|
||||
wire [KEEP_WIDTH-1:0] output_0_axis_tkeep;
|
||||
wire output_0_axis_tvalid;
|
||||
wire output_0_axis_tlast;
|
||||
wire output_0_axis_tuser;
|
||||
wire [ID_WIDTH-1:0] output_0_axis_tid;
|
||||
wire [DEST_WIDTH-1:0] output_0_axis_tdest;
|
||||
wire [USER_WIDTH-1:0] output_0_axis_tuser;
|
||||
wire [DATA_WIDTH-1:0] output_1_axis_tdata;
|
||||
wire [KEEP_WIDTH-1:0] output_1_axis_tkeep;
|
||||
wire output_1_axis_tvalid;
|
||||
wire output_1_axis_tlast;
|
||||
wire output_1_axis_tuser;
|
||||
wire [ID_WIDTH-1:0] output_1_axis_tid;
|
||||
wire [DEST_WIDTH-1:0] output_1_axis_tdest;
|
||||
wire [USER_WIDTH-1:0] output_1_axis_tuser;
|
||||
wire [DATA_WIDTH-1:0] output_2_axis_tdata;
|
||||
wire [KEEP_WIDTH-1:0] output_2_axis_tkeep;
|
||||
wire output_2_axis_tvalid;
|
||||
wire output_2_axis_tlast;
|
||||
wire output_2_axis_tuser;
|
||||
wire [ID_WIDTH-1:0] output_2_axis_tid;
|
||||
wire [DEST_WIDTH-1:0] output_2_axis_tdest;
|
||||
wire [USER_WIDTH-1:0] output_2_axis_tuser;
|
||||
wire [DATA_WIDTH-1:0] output_3_axis_tdata;
|
||||
wire [KEEP_WIDTH-1:0] output_3_axis_tkeep;
|
||||
wire output_3_axis_tvalid;
|
||||
wire output_3_axis_tlast;
|
||||
wire output_3_axis_tuser;
|
||||
wire [ID_WIDTH-1:0] output_3_axis_tid;
|
||||
wire [DEST_WIDTH-1:0] output_3_axis_tdest;
|
||||
wire [USER_WIDTH-1:0] output_3_axis_tuser;
|
||||
|
||||
initial begin
|
||||
// myhdl integration
|
||||
@ -79,8 +102,11 @@ initial begin
|
||||
rst,
|
||||
current_test,
|
||||
input_axis_tdata,
|
||||
input_axis_tkeep,
|
||||
input_axis_tvalid,
|
||||
input_axis_tlast,
|
||||
input_axis_tid,
|
||||
input_axis_tdest,
|
||||
input_axis_tuser,
|
||||
output_0_axis_tready,
|
||||
output_1_axis_tready,
|
||||
@ -92,20 +118,32 @@ initial begin
|
||||
$to_myhdl(
|
||||
input_axis_tready,
|
||||
output_0_axis_tdata,
|
||||
output_0_axis_tkeep,
|
||||
output_0_axis_tvalid,
|
||||
output_0_axis_tlast,
|
||||
output_0_axis_tid,
|
||||
output_0_axis_tdest,
|
||||
output_0_axis_tuser,
|
||||
output_1_axis_tdata,
|
||||
output_1_axis_tkeep,
|
||||
output_1_axis_tvalid,
|
||||
output_1_axis_tlast,
|
||||
output_1_axis_tid,
|
||||
output_1_axis_tdest,
|
||||
output_1_axis_tuser,
|
||||
output_2_axis_tdata,
|
||||
output_2_axis_tkeep,
|
||||
output_2_axis_tvalid,
|
||||
output_2_axis_tlast,
|
||||
output_2_axis_tid,
|
||||
output_2_axis_tdest,
|
||||
output_2_axis_tuser,
|
||||
output_3_axis_tdata,
|
||||
output_3_axis_tkeep,
|
||||
output_3_axis_tvalid,
|
||||
output_3_axis_tlast,
|
||||
output_3_axis_tid,
|
||||
output_3_axis_tdest,
|
||||
output_3_axis_tuser
|
||||
);
|
||||
|
||||
@ -115,37 +153,60 @@ initial begin
|
||||
end
|
||||
|
||||
axis_demux_4 #(
|
||||
.DATA_WIDTH(DATA_WIDTH)
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.KEEP_ENABLE(KEEP_ENABLE),
|
||||
.KEEP_WIDTH(KEEP_WIDTH),
|
||||
.ID_ENABLE(ID_ENABLE),
|
||||
.ID_WIDTH(ID_WIDTH),
|
||||
.DEST_ENABLE(DEST_ENABLE),
|
||||
.DEST_WIDTH(DEST_WIDTH),
|
||||
.USER_ENABLE(USER_ENABLE),
|
||||
.USER_WIDTH(USER_WIDTH)
|
||||
)
|
||||
UUT (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
// AXI input
|
||||
.input_axis_tdata(input_axis_tdata),
|
||||
.input_axis_tkeep(input_axis_tkeep),
|
||||
.input_axis_tvalid(input_axis_tvalid),
|
||||
.input_axis_tready(input_axis_tready),
|
||||
.input_axis_tlast(input_axis_tlast),
|
||||
.input_axis_tid(input_axis_tid),
|
||||
.input_axis_tdest(input_axis_tdest),
|
||||
.input_axis_tuser(input_axis_tuser),
|
||||
// AXI outputs
|
||||
.output_0_axis_tdata(output_0_axis_tdata),
|
||||
.output_0_axis_tkeep(output_0_axis_tkeep),
|
||||
.output_0_axis_tvalid(output_0_axis_tvalid),
|
||||
.output_0_axis_tready(output_0_axis_tready),
|
||||
.output_0_axis_tlast(output_0_axis_tlast),
|
||||
.output_0_axis_tid(output_0_axis_tid),
|
||||
.output_0_axis_tdest(output_0_axis_tdest),
|
||||
.output_0_axis_tuser(output_0_axis_tuser),
|
||||
.output_1_axis_tdata(output_1_axis_tdata),
|
||||
.output_1_axis_tkeep(output_1_axis_tkeep),
|
||||
.output_1_axis_tvalid(output_1_axis_tvalid),
|
||||
.output_1_axis_tready(output_1_axis_tready),
|
||||
.output_1_axis_tlast(output_1_axis_tlast),
|
||||
.output_1_axis_tid(output_1_axis_tid),
|
||||
.output_1_axis_tdest(output_1_axis_tdest),
|
||||
.output_1_axis_tuser(output_1_axis_tuser),
|
||||
.output_2_axis_tdata(output_2_axis_tdata),
|
||||
.output_2_axis_tkeep(output_2_axis_tkeep),
|
||||
.output_2_axis_tvalid(output_2_axis_tvalid),
|
||||
.output_2_axis_tready(output_2_axis_tready),
|
||||
.output_2_axis_tlast(output_2_axis_tlast),
|
||||
.output_2_axis_tid(output_2_axis_tid),
|
||||
.output_2_axis_tdest(output_2_axis_tdest),
|
||||
.output_2_axis_tuser(output_2_axis_tuser),
|
||||
.output_3_axis_tdata(output_3_axis_tdata),
|
||||
.output_3_axis_tkeep(output_3_axis_tkeep),
|
||||
.output_3_axis_tvalid(output_3_axis_tvalid),
|
||||
.output_3_axis_tready(output_3_axis_tready),
|
||||
.output_3_axis_tlast(output_3_axis_tlast),
|
||||
.output_3_axis_tid(output_3_axis_tid),
|
||||
.output_3_axis_tdest(output_3_axis_tdest),
|
||||
.output_3_axis_tuser(output_3_axis_tuser),
|
||||
// Control
|
||||
.enable(enable),
|
||||
|
||||
@ -28,8 +28,8 @@ import os
|
||||
|
||||
import axis_ep
|
||||
|
||||
module = 'axis_demux_64_4'
|
||||
testbench = 'test_%s' % module
|
||||
module = 'axis_demux_4'
|
||||
testbench = 'test_%s_64' % module
|
||||
|
||||
srcs = []
|
||||
|
||||
@ -44,7 +44,14 @@ def bench():
|
||||
|
||||
# Parameters
|
||||
DATA_WIDTH = 64
|
||||
KEEP_ENABLE = (DATA_WIDTH>8)
|
||||
KEEP_WIDTH = (DATA_WIDTH/8)
|
||||
ID_ENABLE = 1
|
||||
ID_WIDTH = 8
|
||||
DEST_ENABLE = 1
|
||||
DEST_WIDTH = 8
|
||||
USER_ENABLE = 1
|
||||
USER_WIDTH = 1
|
||||
|
||||
# Inputs
|
||||
clk = Signal(bool(0))
|
||||
@ -52,10 +59,12 @@ def bench():
|
||||
current_test = Signal(intbv(0)[8:])
|
||||
|
||||
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
|
||||
input_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
|
||||
input_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
|
||||
input_axis_tvalid = Signal(bool(0))
|
||||
input_axis_tlast = Signal(bool(0))
|
||||
input_axis_tuser = Signal(bool(0))
|
||||
input_axis_tid = Signal(intbv(0)[ID_WIDTH:])
|
||||
input_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
|
||||
input_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
|
||||
|
||||
output_0_axis_tready = Signal(bool(0))
|
||||
output_1_axis_tready = Signal(bool(0))
|
||||
@ -69,25 +78,33 @@ def bench():
|
||||
input_axis_tready = Signal(bool(0))
|
||||
|
||||
output_0_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
|
||||
output_0_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
|
||||
output_0_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
|
||||
output_0_axis_tvalid = Signal(bool(0))
|
||||
output_0_axis_tlast = Signal(bool(0))
|
||||
output_0_axis_tuser = Signal(bool(0))
|
||||
output_0_axis_tid = Signal(intbv(0)[ID_WIDTH:])
|
||||
output_0_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
|
||||
output_0_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
|
||||
output_1_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
|
||||
output_1_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
|
||||
output_1_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
|
||||
output_1_axis_tvalid = Signal(bool(0))
|
||||
output_1_axis_tlast = Signal(bool(0))
|
||||
output_1_axis_tuser = Signal(bool(0))
|
||||
output_1_axis_tid = Signal(intbv(0)[ID_WIDTH:])
|
||||
output_1_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
|
||||
output_1_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
|
||||
output_2_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
|
||||
output_2_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
|
||||
output_2_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
|
||||
output_2_axis_tvalid = Signal(bool(0))
|
||||
output_2_axis_tlast = Signal(bool(0))
|
||||
output_2_axis_tuser = Signal(bool(0))
|
||||
output_2_axis_tid = Signal(intbv(0)[ID_WIDTH:])
|
||||
output_2_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
|
||||
output_2_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
|
||||
output_3_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
|
||||
output_3_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
|
||||
output_3_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
|
||||
output_3_axis_tvalid = Signal(bool(0))
|
||||
output_3_axis_tlast = Signal(bool(0))
|
||||
output_3_axis_tuser = Signal(bool(0))
|
||||
output_3_axis_tid = Signal(intbv(0)[ID_WIDTH:])
|
||||
output_3_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
|
||||
output_3_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
|
||||
|
||||
# sources and sinks
|
||||
source_pause = Signal(bool(0))
|
||||
@ -106,6 +123,8 @@ def bench():
|
||||
tvalid=input_axis_tvalid,
|
||||
tready=input_axis_tready,
|
||||
tlast=input_axis_tlast,
|
||||
tid=input_axis_tid,
|
||||
tdest=input_axis_tdest,
|
||||
tuser=input_axis_tuser,
|
||||
pause=source_pause,
|
||||
name='source'
|
||||
@ -121,6 +140,8 @@ def bench():
|
||||
tvalid=output_0_axis_tvalid,
|
||||
tready=output_0_axis_tready,
|
||||
tlast=output_0_axis_tlast,
|
||||
tid=output_0_axis_tid,
|
||||
tdest=output_0_axis_tdest,
|
||||
tuser=output_0_axis_tuser,
|
||||
pause=sink_0_pause,
|
||||
name='sink_0'
|
||||
@ -136,6 +157,8 @@ def bench():
|
||||
tvalid=output_1_axis_tvalid,
|
||||
tready=output_1_axis_tready,
|
||||
tlast=output_1_axis_tlast,
|
||||
tid=output_1_axis_tid,
|
||||
tdest=output_1_axis_tdest,
|
||||
tuser=output_1_axis_tuser,
|
||||
pause=sink_1_pause,
|
||||
name='sink_1'
|
||||
@ -151,6 +174,8 @@ def bench():
|
||||
tvalid=output_2_axis_tvalid,
|
||||
tready=output_2_axis_tready,
|
||||
tlast=output_2_axis_tlast,
|
||||
tid=output_2_axis_tid,
|
||||
tdest=output_2_axis_tdest,
|
||||
tuser=output_2_axis_tuser,
|
||||
pause=sink_2_pause,
|
||||
name='sink_2'
|
||||
@ -166,6 +191,8 @@ def bench():
|
||||
tvalid=output_3_axis_tvalid,
|
||||
tready=output_3_axis_tready,
|
||||
tlast=output_3_axis_tlast,
|
||||
tid=output_3_axis_tid,
|
||||
tdest=output_3_axis_tdest,
|
||||
tuser=output_3_axis_tuser,
|
||||
pause=sink_3_pause,
|
||||
name='sink_3'
|
||||
@ -186,6 +213,8 @@ def bench():
|
||||
input_axis_tvalid=input_axis_tvalid,
|
||||
input_axis_tready=input_axis_tready,
|
||||
input_axis_tlast=input_axis_tlast,
|
||||
input_axis_tid=input_axis_tid,
|
||||
input_axis_tdest=input_axis_tdest,
|
||||
input_axis_tuser=input_axis_tuser,
|
||||
|
||||
output_0_axis_tdata=output_0_axis_tdata,
|
||||
@ -193,24 +222,32 @@ def bench():
|
||||
output_0_axis_tvalid=output_0_axis_tvalid,
|
||||
output_0_axis_tready=output_0_axis_tready,
|
||||
output_0_axis_tlast=output_0_axis_tlast,
|
||||
output_0_axis_tid=output_0_axis_tid,
|
||||
output_0_axis_tdest=output_0_axis_tdest,
|
||||
output_0_axis_tuser=output_0_axis_tuser,
|
||||
output_1_axis_tdata=output_1_axis_tdata,
|
||||
output_1_axis_tkeep=output_1_axis_tkeep,
|
||||
output_1_axis_tvalid=output_1_axis_tvalid,
|
||||
output_1_axis_tready=output_1_axis_tready,
|
||||
output_1_axis_tlast=output_1_axis_tlast,
|
||||
output_1_axis_tid=output_1_axis_tid,
|
||||
output_1_axis_tdest=output_1_axis_tdest,
|
||||
output_1_axis_tuser=output_1_axis_tuser,
|
||||
output_2_axis_tdata=output_2_axis_tdata,
|
||||
output_2_axis_tkeep=output_2_axis_tkeep,
|
||||
output_2_axis_tvalid=output_2_axis_tvalid,
|
||||
output_2_axis_tready=output_2_axis_tready,
|
||||
output_2_axis_tlast=output_2_axis_tlast,
|
||||
output_2_axis_tid=output_2_axis_tid,
|
||||
output_2_axis_tdest=output_2_axis_tdest,
|
||||
output_2_axis_tuser=output_2_axis_tuser,
|
||||
output_3_axis_tdata=output_3_axis_tdata,
|
||||
output_3_axis_tkeep=output_3_axis_tkeep,
|
||||
output_3_axis_tvalid=output_3_axis_tvalid,
|
||||
output_3_axis_tready=output_3_axis_tready,
|
||||
output_3_axis_tlast=output_3_axis_tlast,
|
||||
output_3_axis_tid=output_3_axis_tid,
|
||||
output_3_axis_tdest=output_3_axis_tdest,
|
||||
output_3_axis_tuser=output_3_axis_tuser,
|
||||
|
||||
enable=enable,
|
||||
@ -241,10 +278,15 @@ def bench():
|
||||
|
||||
select.next = 0
|
||||
|
||||
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame = axis_ep.AXIStreamFrame(
|
||||
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
|
||||
id=1,
|
||||
dest=1
|
||||
)
|
||||
|
||||
source.send(test_frame)
|
||||
yield clk.posedge
|
||||
|
||||
@ -265,10 +307,15 @@ def bench():
|
||||
|
||||
select.next = 1
|
||||
|
||||
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame = axis_ep.AXIStreamFrame(
|
||||
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
|
||||
id=2,
|
||||
dest=1
|
||||
)
|
||||
|
||||
source.send(test_frame)
|
||||
yield clk.posedge
|
||||
|
||||
@ -289,14 +336,23 @@ def bench():
|
||||
|
||||
select.next = 0
|
||||
|
||||
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame1 = axis_ep.AXIStreamFrame(
|
||||
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
|
||||
id=3,
|
||||
dest=1
|
||||
)
|
||||
test_frame2 = axis_ep.AXIStreamFrame(
|
||||
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
|
||||
id=3,
|
||||
dest=2
|
||||
)
|
||||
|
||||
source.send(test_frame1)
|
||||
source.send(test_frame2)
|
||||
yield clk.posedge
|
||||
@ -322,14 +378,23 @@ def bench():
|
||||
|
||||
select.next = 1
|
||||
|
||||
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame1 = axis_ep.AXIStreamFrame(
|
||||
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
|
||||
id=4,
|
||||
dest=1
|
||||
)
|
||||
test_frame2 = axis_ep.AXIStreamFrame(
|
||||
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
|
||||
id=4,
|
||||
dest=2
|
||||
)
|
||||
|
||||
source.send(test_frame1)
|
||||
source.send(test_frame2)
|
||||
yield clk.posedge
|
||||
@ -356,14 +421,23 @@ def bench():
|
||||
|
||||
select.next = 1
|
||||
|
||||
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame1 = axis_ep.AXIStreamFrame(
|
||||
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
|
||||
id=5,
|
||||
dest=1
|
||||
)
|
||||
test_frame2 = axis_ep.AXIStreamFrame(
|
||||
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
|
||||
id=5,
|
||||
dest=2
|
||||
)
|
||||
|
||||
source.send(test_frame1)
|
||||
source.send(test_frame2)
|
||||
yield clk.posedge
|
||||
@ -395,14 +469,23 @@ def bench():
|
||||
|
||||
select.next = 1
|
||||
|
||||
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame1 = axis_ep.AXIStreamFrame(
|
||||
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
|
||||
id=6,
|
||||
dest=1
|
||||
)
|
||||
test_frame2 = axis_ep.AXIStreamFrame(
|
||||
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
|
||||
id=6,
|
||||
dest=2
|
||||
)
|
||||
|
||||
source.send(test_frame1)
|
||||
source.send(test_frame2)
|
||||
yield clk.posedge
|
||||
@ -27,13 +27,20 @@ THE SOFTWARE.
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* Testbench for axis_demux_64_4
|
||||
* Testbench for axis_demux_4
|
||||
*/
|
||||
module test_axis_demux_64_4;
|
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module test_axis_demux_4_64;
|
||||
|
||||
// Parameters
|
||||
parameter DATA_WIDTH = 64;
|
||||
parameter KEEP_ENABLE = (DATA_WIDTH>8);
|
||||
parameter KEEP_WIDTH = (DATA_WIDTH/8);
|
||||
parameter ID_ENABLE = 1;
|
||||
parameter ID_WIDTH = 8;
|
||||
parameter DEST_ENABLE = 1;
|
||||
parameter DEST_WIDTH = 8;
|
||||
parameter USER_ENABLE = 1;
|
||||
parameter USER_WIDTH = 1;
|
||||
|
||||
// Inputs
|
||||
reg clk = 0;
|
||||
@ -44,7 +51,9 @@ reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
|
||||
reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0;
|
||||
reg input_axis_tvalid = 0;
|
||||
reg input_axis_tlast = 0;
|
||||
reg input_axis_tuser = 0;
|
||||
reg [ID_WIDTH-1:0] input_axis_tid = 0;
|
||||
reg [DEST_WIDTH-1:0] input_axis_tdest = 0;
|
||||
reg [USER_WIDTH-1:0] input_axis_tuser = 0;
|
||||
|
||||
reg output_0_axis_tready = 0;
|
||||
reg output_1_axis_tready = 0;
|
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@ -61,22 +70,30 @@ wire [DATA_WIDTH-1:0] output_0_axis_tdata;
|
||||
wire [KEEP_WIDTH-1:0] output_0_axis_tkeep;
|
||||
wire output_0_axis_tvalid;
|
||||
wire output_0_axis_tlast;
|
||||
wire output_0_axis_tuser;
|
||||
wire [ID_WIDTH-1:0] output_0_axis_tid;
|
||||
wire [DEST_WIDTH-1:0] output_0_axis_tdest;
|
||||
wire [USER_WIDTH-1:0] output_0_axis_tuser;
|
||||
wire [DATA_WIDTH-1:0] output_1_axis_tdata;
|
||||
wire [KEEP_WIDTH-1:0] output_1_axis_tkeep;
|
||||
wire output_1_axis_tvalid;
|
||||
wire output_1_axis_tlast;
|
||||
wire output_1_axis_tuser;
|
||||
wire [ID_WIDTH-1:0] output_1_axis_tid;
|
||||
wire [DEST_WIDTH-1:0] output_1_axis_tdest;
|
||||
wire [USER_WIDTH-1:0] output_1_axis_tuser;
|
||||
wire [DATA_WIDTH-1:0] output_2_axis_tdata;
|
||||
wire [KEEP_WIDTH-1:0] output_2_axis_tkeep;
|
||||
wire output_2_axis_tvalid;
|
||||
wire output_2_axis_tlast;
|
||||
wire output_2_axis_tuser;
|
||||
wire [ID_WIDTH-1:0] output_2_axis_tid;
|
||||
wire [DEST_WIDTH-1:0] output_2_axis_tdest;
|
||||
wire [USER_WIDTH-1:0] output_2_axis_tuser;
|
||||
wire [DATA_WIDTH-1:0] output_3_axis_tdata;
|
||||
wire [KEEP_WIDTH-1:0] output_3_axis_tkeep;
|
||||
wire output_3_axis_tvalid;
|
||||
wire output_3_axis_tlast;
|
||||
wire output_3_axis_tuser;
|
||||
wire [ID_WIDTH-1:0] output_3_axis_tid;
|
||||
wire [DEST_WIDTH-1:0] output_3_axis_tdest;
|
||||
wire [USER_WIDTH-1:0] output_3_axis_tuser;
|
||||
|
||||
initial begin
|
||||
// myhdl integration
|
||||
@ -88,6 +105,8 @@ initial begin
|
||||
input_axis_tkeep,
|
||||
input_axis_tvalid,
|
||||
input_axis_tlast,
|
||||
input_axis_tid,
|
||||
input_axis_tdest,
|
||||
input_axis_tuser,
|
||||
output_0_axis_tready,
|
||||
output_1_axis_tready,
|
||||
@ -102,32 +121,47 @@ initial begin
|
||||
output_0_axis_tkeep,
|
||||
output_0_axis_tvalid,
|
||||
output_0_axis_tlast,
|
||||
output_0_axis_tid,
|
||||
output_0_axis_tdest,
|
||||
output_0_axis_tuser,
|
||||
output_1_axis_tdata,
|
||||
output_1_axis_tkeep,
|
||||
output_1_axis_tvalid,
|
||||
output_1_axis_tlast,
|
||||
output_1_axis_tid,
|
||||
output_1_axis_tdest,
|
||||
output_1_axis_tuser,
|
||||
output_2_axis_tdata,
|
||||
output_2_axis_tkeep,
|
||||
output_2_axis_tvalid,
|
||||
output_2_axis_tlast,
|
||||
output_2_axis_tid,
|
||||
output_2_axis_tdest,
|
||||
output_2_axis_tuser,
|
||||
output_3_axis_tdata,
|
||||
output_3_axis_tkeep,
|
||||
output_3_axis_tvalid,
|
||||
output_3_axis_tlast,
|
||||
output_3_axis_tid,
|
||||
output_3_axis_tdest,
|
||||
output_3_axis_tuser
|
||||
);
|
||||
|
||||
// dump file
|
||||
$dumpfile("test_axis_demux_64_4.lxt");
|
||||
$dumpvars(0, test_axis_demux_64_4);
|
||||
$dumpfile("test_axis_demux_4_64.lxt");
|
||||
$dumpvars(0, test_axis_demux_4_64);
|
||||
end
|
||||
|
||||
axis_demux_64_4 #(
|
||||
axis_demux_4 #(
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.KEEP_WIDTH(KEEP_WIDTH)
|
||||
.KEEP_ENABLE(KEEP_ENABLE),
|
||||
.KEEP_WIDTH(KEEP_WIDTH),
|
||||
.ID_ENABLE(ID_ENABLE),
|
||||
.ID_WIDTH(ID_WIDTH),
|
||||
.DEST_ENABLE(DEST_ENABLE),
|
||||
.DEST_WIDTH(DEST_WIDTH),
|
||||
.USER_ENABLE(USER_ENABLE),
|
||||
.USER_WIDTH(USER_WIDTH)
|
||||
)
|
||||
UUT (
|
||||
.clk(clk),
|
||||
@ -138,6 +172,8 @@ UUT (
|
||||
.input_axis_tvalid(input_axis_tvalid),
|
||||
.input_axis_tready(input_axis_tready),
|
||||
.input_axis_tlast(input_axis_tlast),
|
||||
.input_axis_tid(input_axis_tid),
|
||||
.input_axis_tdest(input_axis_tdest),
|
||||
.input_axis_tuser(input_axis_tuser),
|
||||
// AXI outputs
|
||||
.output_0_axis_tdata(output_0_axis_tdata),
|
||||
@ -145,24 +181,32 @@ UUT (
|
||||
.output_0_axis_tvalid(output_0_axis_tvalid),
|
||||
.output_0_axis_tready(output_0_axis_tready),
|
||||
.output_0_axis_tlast(output_0_axis_tlast),
|
||||
.output_0_axis_tid(output_0_axis_tid),
|
||||
.output_0_axis_tdest(output_0_axis_tdest),
|
||||
.output_0_axis_tuser(output_0_axis_tuser),
|
||||
.output_1_axis_tdata(output_1_axis_tdata),
|
||||
.output_1_axis_tkeep(output_1_axis_tkeep),
|
||||
.output_1_axis_tvalid(output_1_axis_tvalid),
|
||||
.output_1_axis_tready(output_1_axis_tready),
|
||||
.output_1_axis_tlast(output_1_axis_tlast),
|
||||
.output_1_axis_tid(output_1_axis_tid),
|
||||
.output_1_axis_tdest(output_1_axis_tdest),
|
||||
.output_1_axis_tuser(output_1_axis_tuser),
|
||||
.output_2_axis_tdata(output_2_axis_tdata),
|
||||
.output_2_axis_tkeep(output_2_axis_tkeep),
|
||||
.output_2_axis_tvalid(output_2_axis_tvalid),
|
||||
.output_2_axis_tready(output_2_axis_tready),
|
||||
.output_2_axis_tlast(output_2_axis_tlast),
|
||||
.output_2_axis_tid(output_2_axis_tid),
|
||||
.output_2_axis_tdest(output_2_axis_tdest),
|
||||
.output_2_axis_tuser(output_2_axis_tuser),
|
||||
.output_3_axis_tdata(output_3_axis_tdata),
|
||||
.output_3_axis_tkeep(output_3_axis_tkeep),
|
||||
.output_3_axis_tvalid(output_3_axis_tvalid),
|
||||
.output_3_axis_tready(output_3_axis_tready),
|
||||
.output_3_axis_tlast(output_3_axis_tlast),
|
||||
.output_3_axis_tid(output_3_axis_tid),
|
||||
.output_3_axis_tdest(output_3_axis_tdest),
|
||||
.output_3_axis_tuser(output_3_axis_tuser),
|
||||
// Control
|
||||
.enable(enable),
|
||||
Loading…
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Reference in New Issue
Block a user