From 585ccefa1534cba00ee915f54baf491a0b49df82 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Tue, 26 Mar 2019 12:42:08 -0700 Subject: [PATCH] Add TX underflow error signal --- rtl/axis_baser_tx_64.v | 11 +++++++++-- rtl/axis_gmii_tx.v | 9 ++++++++- rtl/axis_xgmii_tx_32.v | 9 ++++++++- rtl/axis_xgmii_tx_64.v | 9 ++++++++- rtl/eth_mac_10g.v | 4 +++- rtl/eth_mac_10g_fifo.v | 31 +++++++++++++++++++++++++++++++ rtl/eth_mac_1g.v | 4 +++- rtl/eth_mac_1g_fifo.v | 30 ++++++++++++++++++++++++++++++ rtl/eth_mac_1g_gmii.v | 2 ++ rtl/eth_mac_1g_gmii_fifo.v | 30 ++++++++++++++++++++++++++++++ rtl/eth_mac_1g_rgmii.v | 2 ++ rtl/eth_mac_1g_rgmii_fifo.v | 30 ++++++++++++++++++++++++++++++ rtl/eth_mac_phy_10g.v | 4 +++- rtl/eth_mac_phy_10g_fifo.v | 30 ++++++++++++++++++++++++++++++ rtl/eth_mac_phy_10g_tx.v | 6 ++++-- tb/test_axis_baser_tx_64.py | 2 ++ tb/test_axis_baser_tx_64.v | 7 +++++-- tb/test_axis_gmii_tx.py | 4 +++- tb/test_axis_gmii_tx.v | 7 +++++-- tb/test_axis_xgmii_tx_32.py | 4 +++- tb/test_axis_xgmii_tx_32.v | 7 +++++-- tb/test_axis_xgmii_tx_64.py | 4 +++- tb/test_axis_xgmii_tx_64.v | 7 +++++-- tb/test_eth_mac_10g_32.py | 2 ++ tb/test_eth_mac_10g_32.v | 3 +++ tb/test_eth_mac_10g_64.py | 2 ++ tb/test_eth_mac_10g_64.v | 3 +++ tb/test_eth_mac_10g_fifo_32.py | 2 ++ tb/test_eth_mac_10g_fifo_32.v | 3 +++ tb/test_eth_mac_10g_fifo_64.py | 2 ++ tb/test_eth_mac_10g_fifo_64.v | 3 +++ tb/test_eth_mac_1g.py | 2 ++ tb/test_eth_mac_1g.v | 3 +++ tb/test_eth_mac_1g_fifo.py | 2 ++ tb/test_eth_mac_1g_fifo.v | 3 +++ tb/test_eth_mac_1g_gmii.py | 2 ++ tb/test_eth_mac_1g_gmii.v | 3 +++ tb/test_eth_mac_1g_gmii_fifo.py | 2 ++ tb/test_eth_mac_1g_gmii_fifo.v | 3 +++ tb/test_eth_mac_1g_rgmii.py | 2 ++ tb/test_eth_mac_1g_rgmii.v | 3 +++ tb/test_eth_mac_1g_rgmii_fifo.py | 2 ++ tb/test_eth_mac_1g_rgmii_fifo.v | 3 +++ tb/test_eth_mac_phy_10g.py | 2 ++ tb/test_eth_mac_phy_10g.v | 3 +++ tb/test_eth_mac_phy_10g_fifo.py | 2 ++ tb/test_eth_mac_phy_10g_fifo.v | 3 +++ 47 files changed, 292 insertions(+), 21 deletions(-) diff --git a/rtl/axis_baser_tx_64.v b/rtl/axis_baser_tx_64.v index 7bf1d220..cd11407a 100644 --- a/rtl/axis_baser_tx_64.v +++ b/rtl/axis_baser_tx_64.v @@ -67,7 +67,8 @@ module axis_baser_tx_64 # * Status */ output wire start_packet_0, - output wire start_packet_4 + output wire start_packet_4, + output wire error_underflow ); // bus width assertions @@ -211,6 +212,7 @@ reg [3:0] output_type_reg = OUTPUT_TYPE_IDLE, output_type_next; reg start_packet_0_reg = 1'b0, start_packet_0_next; reg start_packet_4_reg = 1'b0, start_packet_4_next; +reg error_underflow_reg = 1'b0, error_underflow_next; assign s_axis_tready = s_axis_tready_reg; @@ -219,6 +221,7 @@ assign encoded_tx_hdr = encoded_tx_hdr_reg; assign start_packet_0 = start_packet_0_reg; assign start_packet_4 = start_packet_4_reg; +assign error_underflow = error_underflow_reg; lfsr #( .LFSR_WIDTH(32), @@ -474,6 +477,7 @@ always @* begin start_packet_0_next = 1'b0; start_packet_4_next = 1'b0; + error_underflow_next = 1'b0; case (state_reg) STATE_IDLE: begin @@ -554,10 +558,11 @@ always @* begin state_next = STATE_PAYLOAD; end end else begin - // tvalid deassert, fail framec + // tvalid deassert, fail frame output_type_next = OUTPUT_TYPE_ERROR; frame_ptr_next = 16'd0; ifg_count_next = 8'd8; + error_underflow_next = 1'b1; state_next = STATE_WAIT_END; end end @@ -728,6 +733,7 @@ always @(posedge clk) begin start_packet_0_reg <= 1'b0; start_packet_4_reg <= 1'b0; + error_underflow_reg <= 1'b0; crc_state <= 32'hFFFFFFFF; @@ -747,6 +753,7 @@ always @(posedge clk) begin start_packet_0_reg <= start_packet_0_next; start_packet_4_reg <= start_packet_4_next; + error_underflow_reg <= error_underflow_next; delay_type_valid <= 1'b0; diff --git a/rtl/axis_gmii_tx.v b/rtl/axis_gmii_tx.v index 8f0316c6..0acdab33 100644 --- a/rtl/axis_gmii_tx.v +++ b/rtl/axis_gmii_tx.v @@ -68,7 +68,8 @@ module axis_gmii_tx # /* * Status */ - output wire start_packet + output wire start_packet, + output wire error_underflow ); localparam [7:0] @@ -105,6 +106,7 @@ reg gmii_tx_er_reg = 1'b0, gmii_tx_er_next; reg s_axis_tready_reg = 1'b0, s_axis_tready_next; reg start_packet_reg = 1'b0, start_packet_next; +reg error_underflow_reg = 1'b0, error_underflow_next; reg [31:0] crc_state = 32'hFFFFFFFF; wire [31:0] crc_next; @@ -116,6 +118,7 @@ assign gmii_tx_en = gmii_tx_en_reg; assign gmii_tx_er = gmii_tx_er_reg; assign start_packet = start_packet_reg; +assign error_underflow = error_underflow_reg; lfsr #( .LFSR_WIDTH(32), @@ -153,6 +156,7 @@ always @* begin gmii_tx_er_next = 1'b0; start_packet_next = 1'b0; + error_underflow_next = 1'b0; if (!clk_enable) begin // clock disabled - hold state and outputs @@ -243,6 +247,7 @@ always @* begin // tvalid deassert, fail frame gmii_tx_er_next = 1'b1; frame_ptr_next = 16'd0; + error_underflow_next = 1'b1; state_next = STATE_WAIT_END; end end @@ -364,6 +369,7 @@ always @(posedge clk) begin gmii_tx_er_reg <= 1'b0; start_packet_reg <= 1'b0; + error_underflow_reg <= 1'b0; crc_state <= 32'hFFFFFFFF; end else begin @@ -377,6 +383,7 @@ always @(posedge clk) begin gmii_tx_er_reg <= gmii_tx_er_next; start_packet_reg <= start_packet_next; + error_underflow_reg <= error_underflow_next; // datapath if (reset_crc) begin diff --git a/rtl/axis_xgmii_tx_32.v b/rtl/axis_xgmii_tx_32.v index bdcda1cc..ea2ac38f 100644 --- a/rtl/axis_xgmii_tx_32.v +++ b/rtl/axis_xgmii_tx_32.v @@ -63,7 +63,8 @@ module axis_xgmii_tx_32 # /* * Status */ - output wire start_packet + output wire start_packet, + output wire error_underflow ); localparam MIN_FL_NOCRC = MIN_FRAME_LENGTH-4; @@ -129,6 +130,7 @@ reg [31:0] xgmii_txd_reg = {4{XGMII_IDLE}}, xgmii_txd_next; reg [3:0] xgmii_txc_reg = 4'b1111, xgmii_txc_next; reg start_packet_reg = 1'b0, start_packet_next; +reg error_underflow_reg = 1'b0, error_underflow_next; assign s_axis_tready = s_axis_tready_reg; @@ -136,6 +138,7 @@ assign xgmii_txd = xgmii_txd_reg; assign xgmii_txc = xgmii_txc_reg; assign start_packet = start_packet_reg; +assign error_underflow = error_underflow_reg; lfsr #( .LFSR_WIDTH(32), @@ -288,6 +291,7 @@ always @* begin xgmii_txc_next = 4'b1111; start_packet_next = 1'b0; + error_underflow_next = 1'b0; case (state_reg) STATE_IDLE: begin @@ -376,6 +380,7 @@ always @* begin xgmii_txc_next = 4'b1111; frame_ptr_next = 16'd0; ifg_count_next = 8'd10; + error_underflow_next = 1'b1; state_next = STATE_WAIT_END; end end @@ -536,6 +541,7 @@ always @(posedge clk) begin xgmii_txc_reg <= 4'b1111; start_packet_reg <= 1'b0; + error_underflow_reg <= 1'b0; crc_state <= 32'hFFFFFFFF; end else begin @@ -552,6 +558,7 @@ always @(posedge clk) begin xgmii_txc_reg <= xgmii_txc_next; start_packet_reg <= start_packet_next; + error_underflow_reg <= error_underflow_next; // datapath if (reset_crc) begin diff --git a/rtl/axis_xgmii_tx_64.v b/rtl/axis_xgmii_tx_64.v index 3f260133..2d5816b1 100644 --- a/rtl/axis_xgmii_tx_64.v +++ b/rtl/axis_xgmii_tx_64.v @@ -64,7 +64,8 @@ module axis_xgmii_tx_64 # * Status */ output wire start_packet_0, - output wire start_packet_4 + output wire start_packet_4, + output wire error_underflow ); localparam MIN_FL_NOCRC = MIN_FRAME_LENGTH-4; @@ -140,6 +141,7 @@ reg [7:0] xgmii_txc_reg = 8'b11111111, xgmii_txc_next; reg start_packet_0_reg = 1'b0, start_packet_0_next; reg start_packet_4_reg = 1'b0, start_packet_4_next; +reg error_underflow_reg = 1'b0, error_underflow_next; assign s_axis_tready = s_axis_tready_reg; @@ -148,6 +150,7 @@ assign xgmii_txc = xgmii_txc_reg; assign start_packet_0 = start_packet_0_reg; assign start_packet_4 = start_packet_4_reg; +assign error_underflow = error_underflow_reg; lfsr #( .LFSR_WIDTH(32), @@ -404,6 +407,7 @@ always @* begin start_packet_0_next = 1'b0; start_packet_4_next = 1'b0; + error_underflow_next = 1'b0; case (state_reg) STATE_IDLE: begin @@ -491,6 +495,7 @@ always @* begin xgmii_txc_next = 8'b11111111; frame_ptr_next = 16'd0; ifg_count_next = 8'd8; + error_underflow_next = 1'b1; state_next = STATE_WAIT_END; end end @@ -658,6 +663,7 @@ always @(posedge clk) begin start_packet_0_reg <= 1'b0; start_packet_4_reg <= 1'b0; + error_underflow_reg <= 1'b0; crc_state <= 32'hFFFFFFFF; @@ -674,6 +680,7 @@ always @(posedge clk) begin start_packet_0_reg <= start_packet_0_next; start_packet_4_reg <= start_packet_4_next; + error_underflow_reg <= error_underflow_next; if (swap_lanes || (lanes_swapped && !unswap_lanes)) begin lanes_swapped <= 1'b1; diff --git a/rtl/eth_mac_10g.v b/rtl/eth_mac_10g.v index 89f36874..8d3099d8 100644 --- a/rtl/eth_mac_10g.v +++ b/rtl/eth_mac_10g.v @@ -76,6 +76,7 @@ module eth_mac_10g # */ output wire tx_start_packet_0, output wire tx_start_packet_4, + output wire tx_error_underflow, output wire rx_start_packet_0, output wire rx_start_packet_4, output wire rx_error_bad_frame, @@ -139,7 +140,8 @@ axis_xgmii_tx_inst ( .xgmii_txc(xgmii_txc), .ifg_delay(ifg_delay), .start_packet_0(tx_start_packet_0), - .start_packet_4(tx_start_packet_4) + .start_packet_4(tx_start_packet_4), + .error_underflow(tx_error_underflow) ); end else begin diff --git a/rtl/eth_mac_10g_fifo.v b/rtl/eth_mac_10g_fifo.v index 207aad38..05f57b1d 100644 --- a/rtl/eth_mac_10g_fifo.v +++ b/rtl/eth_mac_10g_fifo.v @@ -85,6 +85,7 @@ module eth_mac_10g_fifo # /* * Status */ + output wire tx_error_underflow, output wire tx_fifo_overflow, output wire tx_fifo_bad_frame, output wire tx_fifo_good_frame, @@ -114,6 +115,35 @@ wire rx_fifo_axis_tlast; wire rx_fifo_axis_tuser; // synchronize MAC status signals into logic clock domain +wire tx_error_underflow_int; + +reg tx_sync_reg_1 = 1'b0; +reg tx_sync_reg_2 = 1'b0; +reg tx_sync_reg_3 = 1'b0; +reg tx_sync_reg_4 = 1'b0; + +assign tx_error_underflow = tx_sync_reg_3 ^ tx_sync_reg_4; + +always @(posedge tx_clk or posedge tx_rst) begin + if (tx_rst) begin + tx_sync_reg_1 <= 1'b0; + end else begin + tx_sync_reg_1 <= tx_sync_reg_1 ^ {tx_error_underflow_int}; + end +end + +always @(posedge logic_clk or posedge logic_rst) begin + if (logic_rst) begin + tx_sync_reg_2 <= 1'b0; + tx_sync_reg_3 <= 1'b0; + tx_sync_reg_4 <= 1'b0; + end else begin + tx_sync_reg_2 <= tx_sync_reg_1; + tx_sync_reg_3 <= tx_sync_reg_2; + tx_sync_reg_4 <= tx_sync_reg_3; + end +end + wire rx_error_bad_frame_int; wire rx_error_bad_fcs_int; @@ -173,6 +203,7 @@ eth_mac_10g_inst ( .xgmii_rxc(xgmii_rxc), .xgmii_txd(xgmii_txd), .xgmii_txc(xgmii_txc), + .tx_error_underflow(tx_error_underflow_int), .rx_error_bad_frame(rx_error_bad_frame_int), .rx_error_bad_fcs(rx_error_bad_fcs_int), .ifg_delay(ifg_delay) diff --git a/rtl/eth_mac_1g.v b/rtl/eth_mac_1g.v index 727406cc..1a37ff5c 100644 --- a/rtl/eth_mac_1g.v +++ b/rtl/eth_mac_1g.v @@ -79,6 +79,7 @@ module eth_mac_1g # * Status */ output wire tx_start_packet, + output wire tx_error_underflow, output wire rx_start_packet, output wire rx_error_bad_frame, output wire rx_error_bad_fcs, @@ -125,7 +126,8 @@ axis_gmii_tx_inst ( .clk_enable(tx_clk_enable), .mii_select(tx_mii_select), .ifg_delay(ifg_delay), - .start_packet(tx_start_packet) + .start_packet(tx_start_packet), + .error_underflow(tx_error_underflow) ); endmodule diff --git a/rtl/eth_mac_1g_fifo.v b/rtl/eth_mac_1g_fifo.v index b80fd95f..bda92a89 100644 --- a/rtl/eth_mac_1g_fifo.v +++ b/rtl/eth_mac_1g_fifo.v @@ -89,6 +89,7 @@ module eth_mac_1g_fifo # /* * Status */ + output wire tx_error_underflow, output wire tx_fifo_overflow, output wire tx_fifo_bad_frame, output wire tx_fifo_good_frame, @@ -116,6 +117,35 @@ wire rx_fifo_axis_tlast; wire rx_fifo_axis_tuser; // synchronize MAC status signals into logic clock domain +wire tx_error_underflow_int; + +reg tx_sync_reg_1 = 1'b0; +reg tx_sync_reg_2 = 1'b0; +reg tx_sync_reg_3 = 1'b0; +reg tx_sync_reg_4 = 1'b0; + +assign tx_error_underflow = tx_sync_reg_3 ^ tx_sync_reg_4; + +always @(posedge tx_clk or posedge tx_rst) begin + if (tx_rst) begin + tx_sync_reg_1 <= 1'b0; + end else begin + tx_sync_reg_1 <= tx_sync_reg_1 ^ {tx_error_underflow_int}; + end +end + +always @(posedge logic_clk or posedge logic_rst) begin + if (logic_rst) begin + tx_sync_reg_2 <= 1'b0; + tx_sync_reg_3 <= 1'b0; + tx_sync_reg_4 <= 1'b0; + end else begin + tx_sync_reg_2 <= tx_sync_reg_1; + tx_sync_reg_3 <= tx_sync_reg_2; + tx_sync_reg_4 <= tx_sync_reg_3; + end +end + wire rx_error_bad_frame_int; wire rx_error_bad_fcs_int; diff --git a/rtl/eth_mac_1g_gmii.v b/rtl/eth_mac_1g_gmii.v index c0f4ed4d..8e5d7ff6 100644 --- a/rtl/eth_mac_1g_gmii.v +++ b/rtl/eth_mac_1g_gmii.v @@ -86,6 +86,7 @@ module eth_mac_1g_gmii # /* * Status */ + output wire tx_error_underflow, output wire rx_error_bad_frame, output wire rx_error_bad_fcs, output wire [1:0] speed, @@ -244,6 +245,7 @@ eth_mac_1g_inst ( .tx_clk_enable(1'b1), .rx_mii_select(rx_mii_select_3), .tx_mii_select(tx_mii_select_3), + .tx_error_underflow(tx_error_underflow), .rx_error_bad_frame(rx_error_bad_frame), .rx_error_bad_fcs(rx_error_bad_fcs), .ifg_delay(ifg_delay) diff --git a/rtl/eth_mac_1g_gmii_fifo.v b/rtl/eth_mac_1g_gmii_fifo.v index 17d4ae35..a7c8387e 100644 --- a/rtl/eth_mac_1g_gmii_fifo.v +++ b/rtl/eth_mac_1g_gmii_fifo.v @@ -93,6 +93,7 @@ module eth_mac_1g_gmii_fifo # /* * Status */ + output wire tx_error_underflow, output wire tx_fifo_overflow, output wire tx_fifo_bad_frame, output wire tx_fifo_good_frame, @@ -126,6 +127,35 @@ wire rx_fifo_axis_tlast; wire rx_fifo_axis_tuser; // synchronize MAC status signals into logic clock domain +wire tx_error_underflow_int; + +reg tx_sync_reg_1 = 1'b0; +reg tx_sync_reg_2 = 1'b0; +reg tx_sync_reg_3 = 1'b0; +reg tx_sync_reg_4 = 1'b0; + +assign tx_error_underflow = tx_sync_reg_3 ^ tx_sync_reg_4; + +always @(posedge tx_clk or posedge tx_rst) begin + if (tx_rst) begin + tx_sync_reg_1 <= 1'b0; + end else begin + tx_sync_reg_1 <= tx_sync_reg_1 ^ {tx_error_underflow_int}; + end +end + +always @(posedge logic_clk or posedge logic_rst) begin + if (logic_rst) begin + tx_sync_reg_2 <= 1'b0; + tx_sync_reg_3 <= 1'b0; + tx_sync_reg_4 <= 1'b0; + end else begin + tx_sync_reg_2 <= tx_sync_reg_1; + tx_sync_reg_3 <= tx_sync_reg_2; + tx_sync_reg_4 <= tx_sync_reg_3; + end +end + wire rx_error_bad_frame_int; wire rx_error_bad_fcs_int; diff --git a/rtl/eth_mac_1g_rgmii.v b/rtl/eth_mac_1g_rgmii.v index e1b01902..48facace 100644 --- a/rtl/eth_mac_1g_rgmii.v +++ b/rtl/eth_mac_1g_rgmii.v @@ -86,6 +86,7 @@ module eth_mac_1g_rgmii # /* * Status */ + output wire tx_error_underflow, output wire rx_error_bad_frame, output wire rx_error_bad_fcs, output wire [1:0] speed, @@ -245,6 +246,7 @@ eth_mac_1g_inst ( .tx_clk_enable(mac_gmii_tx_clk_en), .rx_mii_select(rx_mii_select_3), .tx_mii_select(tx_mii_select_3), + .tx_error_underflow(tx_error_underflow), .rx_error_bad_frame(rx_error_bad_frame), .rx_error_bad_fcs(rx_error_bad_fcs), .ifg_delay(ifg_delay) diff --git a/rtl/eth_mac_1g_rgmii_fifo.v b/rtl/eth_mac_1g_rgmii_fifo.v index 2298d52d..88041ae6 100644 --- a/rtl/eth_mac_1g_rgmii_fifo.v +++ b/rtl/eth_mac_1g_rgmii_fifo.v @@ -93,6 +93,7 @@ module eth_mac_1g_rgmii_fifo # /* * Status */ + output wire tx_error_underflow, output wire tx_fifo_overflow, output wire tx_fifo_bad_frame, output wire tx_fifo_good_frame, @@ -126,6 +127,35 @@ wire rx_fifo_axis_tlast; wire rx_fifo_axis_tuser; // synchronize MAC status signals into logic clock domain +wire tx_error_underflow_int; + +reg tx_sync_reg_1 = 1'b0; +reg tx_sync_reg_2 = 1'b0; +reg tx_sync_reg_3 = 1'b0; +reg tx_sync_reg_4 = 1'b0; + +assign tx_error_underflow = tx_sync_reg_3 ^ tx_sync_reg_4; + +always @(posedge tx_clk or posedge tx_rst) begin + if (tx_rst) begin + tx_sync_reg_1 <= 1'b0; + end else begin + tx_sync_reg_1 <= tx_sync_reg_1 ^ {tx_error_underflow_int}; + end +end + +always @(posedge logic_clk or posedge logic_rst) begin + if (logic_rst) begin + tx_sync_reg_2 <= 1'b0; + tx_sync_reg_3 <= 1'b0; + tx_sync_reg_4 <= 1'b0; + end else begin + tx_sync_reg_2 <= tx_sync_reg_1; + tx_sync_reg_3 <= tx_sync_reg_2; + tx_sync_reg_4 <= tx_sync_reg_3; + end +end + wire rx_error_bad_frame_int; wire rx_error_bad_fcs_int; diff --git a/rtl/eth_mac_phy_10g.v b/rtl/eth_mac_phy_10g.v index 672f09a9..a06da75f 100644 --- a/rtl/eth_mac_phy_10g.v +++ b/rtl/eth_mac_phy_10g.v @@ -82,6 +82,7 @@ module eth_mac_phy_10g # */ output wire tx_start_packet_0, output wire tx_start_packet_4, + output wire tx_error_underflow, output wire rx_start_packet_0, output wire rx_start_packet_4, output wire rx_error_bad_frame, @@ -148,7 +149,8 @@ eth_mac_phy_10g_tx_inst ( .serdes_tx_hdr(serdes_tx_hdr), .ifg_delay(ifg_delay), .tx_start_packet_0(tx_start_packet_0), - .tx_start_packet_4(tx_start_packet_4) + .tx_start_packet_4(tx_start_packet_4), + .tx_error_underflow(tx_error_underflow) ); endmodule diff --git a/rtl/eth_mac_phy_10g_fifo.v b/rtl/eth_mac_phy_10g_fifo.v index e19f8981..c8dc0b9c 100644 --- a/rtl/eth_mac_phy_10g_fifo.v +++ b/rtl/eth_mac_phy_10g_fifo.v @@ -91,6 +91,7 @@ module eth_mac_phy_10g_fifo # /* * Status */ + output wire tx_error_underflow, output wire tx_fifo_overflow, output wire tx_fifo_bad_frame, output wire tx_fifo_good_frame, @@ -122,6 +123,35 @@ wire rx_fifo_axis_tlast; wire rx_fifo_axis_tuser; // synchronize MAC status signals into logic clock domain +wire tx_error_underflow_int; + +reg tx_sync_reg_1 = 1'b0; +reg tx_sync_reg_2 = 1'b0; +reg tx_sync_reg_3 = 1'b0; +reg tx_sync_reg_4 = 1'b0; + +assign tx_error_underflow = tx_sync_reg_3 ^ tx_sync_reg_4; + +always @(posedge tx_clk or posedge tx_rst) begin + if (tx_rst) begin + tx_sync_reg_1 <= 1'b0; + end else begin + tx_sync_reg_1 <= tx_sync_reg_1 ^ {tx_error_underflow_int}; + end +end + +always @(posedge logic_clk or posedge logic_rst) begin + if (logic_rst) begin + tx_sync_reg_2 <= 1'b0; + tx_sync_reg_3 <= 1'b0; + tx_sync_reg_4 <= 1'b0; + end else begin + tx_sync_reg_2 <= tx_sync_reg_1; + tx_sync_reg_3 <= tx_sync_reg_2; + tx_sync_reg_4 <= tx_sync_reg_3; + end +end + wire rx_error_bad_frame_int; wire rx_error_bad_fcs_int; diff --git a/rtl/eth_mac_phy_10g_tx.v b/rtl/eth_mac_phy_10g_tx.v index 7c4d2032..cc5b119d 100644 --- a/rtl/eth_mac_phy_10g_tx.v +++ b/rtl/eth_mac_phy_10g_tx.v @@ -70,7 +70,8 @@ module eth_mac_phy_10g_tx # * Status */ output wire tx_start_packet_0, - output wire tx_start_packet_4 + output wire tx_start_packet_4, + output wire tx_error_underflow ); // bus width assertions @@ -115,7 +116,8 @@ axis_baser_tx_inst ( .encoded_tx_hdr(encoded_tx_hdr), .ifg_delay(ifg_delay), .start_packet_0(tx_start_packet_0), - .start_packet_4(tx_start_packet_4) + .start_packet_4(tx_start_packet_4), + .error_underflow(tx_error_underflow) ); reg [57:0] tx_scrambler_state_reg = {58{1'b1}}; diff --git a/tb/test_axis_baser_tx_64.py b/tb/test_axis_baser_tx_64.py index e64be494..f1e7d762 100755 --- a/tb/test_axis_baser_tx_64.py +++ b/tb/test_axis_baser_tx_64.py @@ -71,6 +71,7 @@ def bench(): encoded_tx_hdr = Signal(intbv(1)[HDR_WIDTH:]) start_packet_0 = Signal(bool(0)) start_packet_4 = Signal(bool(0)) + error_underflow = Signal(bool(0)) # sources and sinks source_pause = Signal(bool(0)) @@ -120,6 +121,7 @@ def bench(): ifg_delay=ifg_delay, start_packet_0=start_packet_0, start_packet_4=start_packet_4, + error_underflow=error_underflow ) @always(delay(4)) diff --git a/tb/test_axis_baser_tx_64.v b/tb/test_axis_baser_tx_64.v index efa19525..bd747759 100644 --- a/tb/test_axis_baser_tx_64.v +++ b/tb/test_axis_baser_tx_64.v @@ -57,6 +57,7 @@ wire [DATA_WIDTH-1:0] encoded_tx_data; wire [HDR_WIDTH-1:0] encoded_tx_hdr; wire start_packet_0; wire start_packet_4; +wire error_underflow; initial begin // myhdl integration @@ -76,7 +77,8 @@ initial begin encoded_tx_data, encoded_tx_hdr, start_packet_0, - start_packet_4 + start_packet_4, + error_underflow ); // dump file @@ -105,7 +107,8 @@ UUT ( .encoded_tx_hdr(encoded_tx_hdr), .ifg_delay(ifg_delay), .start_packet_0(start_packet_0), - .start_packet_4(start_packet_4) + .start_packet_4(start_packet_4), + .error_underflow(error_underflow) ); endmodule diff --git a/tb/test_axis_gmii_tx.py b/tb/test_axis_gmii_tx.py index aa36f80f..f0cd1b5b 100755 --- a/tb/test_axis_gmii_tx.py +++ b/tb/test_axis_gmii_tx.py @@ -68,6 +68,7 @@ def bench(): gmii_tx_en = Signal(bool(0)) gmii_tx_er = Signal(bool(0)) start_packet = Signal(bool(0)) + error_underflow = Signal(bool(0)) # sources and sinks source_pause = Signal(bool(0)) @@ -124,7 +125,8 @@ def bench(): ifg_delay=ifg_delay, - start_packet=start_packet + start_packet=start_packet, + error_underflow=error_underflow ) @always(delay(4)) diff --git a/tb/test_axis_gmii_tx.v b/tb/test_axis_gmii_tx.v index e15d1946..99d70245 100644 --- a/tb/test_axis_gmii_tx.v +++ b/tb/test_axis_gmii_tx.v @@ -54,6 +54,7 @@ wire [7:0] gmii_txd; wire gmii_tx_en; wire gmii_tx_er; wire start_packet; +wire error_underflow; initial begin // myhdl integration @@ -74,7 +75,8 @@ initial begin gmii_txd, gmii_tx_en, gmii_tx_er, - start_packet + start_packet, + error_underflow ); // dump file @@ -100,7 +102,8 @@ UUT ( .clk_enable(clk_enable), .mii_select(mii_select), .ifg_delay(ifg_delay), - .start_packet(start_packet) + .start_packet(start_packet), + .error_underflow(error_underflow) ); endmodule diff --git a/tb/test_axis_xgmii_tx_32.py b/tb/test_axis_xgmii_tx_32.py index 86fa63b9..9fca431b 100755 --- a/tb/test_axis_xgmii_tx_32.py +++ b/tb/test_axis_xgmii_tx_32.py @@ -66,6 +66,7 @@ def bench(): xgmii_txd = Signal(intbv(0x07070707)[32:]) xgmii_txc = Signal(intbv(0xf)[4:]) start_packet = Signal(bool(0)) + error_underflow = Signal(bool(0)) # sources and sinks source_pause = Signal(bool(0)) @@ -117,7 +118,8 @@ def bench(): ifg_delay=ifg_delay, - start_packet=start_packet + start_packet=start_packet, + error_underflow=error_underflow ) @always(delay(4)) diff --git a/tb/test_axis_xgmii_tx_32.v b/tb/test_axis_xgmii_tx_32.v index aa783804..244bc341 100644 --- a/tb/test_axis_xgmii_tx_32.v +++ b/tb/test_axis_xgmii_tx_32.v @@ -52,6 +52,7 @@ wire s_axis_tready; wire [31:0] xgmii_txd; wire [3:0] xgmii_txc; wire start_packet; +wire error_underflow; initial begin // myhdl integration @@ -70,7 +71,8 @@ initial begin s_axis_tready, xgmii_txd, xgmii_txc, - start_packet + start_packet, + error_underflow ); // dump file @@ -94,7 +96,8 @@ UUT ( .xgmii_txd(xgmii_txd), .xgmii_txc(xgmii_txc), .ifg_delay(ifg_delay), - .start_packet(start_packet) + .start_packet(start_packet), + .error_underflow(error_underflow) ); endmodule diff --git a/tb/test_axis_xgmii_tx_64.py b/tb/test_axis_xgmii_tx_64.py index e4b7ee3e..ce183cdc 100755 --- a/tb/test_axis_xgmii_tx_64.py +++ b/tb/test_axis_xgmii_tx_64.py @@ -67,6 +67,7 @@ def bench(): xgmii_txc = Signal(intbv(0xff)[8:]) start_packet_0 = Signal(bool(0)) start_packet_4 = Signal(bool(0)) + error_underflow = Signal(bool(0)) # sources and sinks source_pause = Signal(bool(0)) @@ -119,7 +120,8 @@ def bench(): ifg_delay=ifg_delay, start_packet_0=start_packet_0, - start_packet_4=start_packet_4 + start_packet_4=start_packet_4, + error_underflow=error_underflow ) @always(delay(4)) diff --git a/tb/test_axis_xgmii_tx_64.v b/tb/test_axis_xgmii_tx_64.v index 6ac8654c..26597295 100644 --- a/tb/test_axis_xgmii_tx_64.v +++ b/tb/test_axis_xgmii_tx_64.v @@ -53,6 +53,7 @@ wire [63:0] xgmii_txd; wire [7:0] xgmii_txc; wire start_packet_0; wire start_packet_4; +wire error_underflow; initial begin // myhdl integration @@ -72,7 +73,8 @@ initial begin xgmii_txd, xgmii_txc, start_packet_0, - start_packet_4 + start_packet_4, + error_underflow ); // dump file @@ -97,7 +99,8 @@ UUT ( .xgmii_txc(xgmii_txc), .ifg_delay(ifg_delay), .start_packet_0(start_packet_0), - .start_packet_4(start_packet_4) + .start_packet_4(start_packet_4), + .error_underflow(error_underflow) ); endmodule diff --git a/tb/test_eth_mac_10g_32.py b/tb/test_eth_mac_10g_32.py index 305db04a..1866379d 100755 --- a/tb/test_eth_mac_10g_32.py +++ b/tb/test_eth_mac_10g_32.py @@ -84,6 +84,7 @@ def bench(): xgmii_txc = Signal(intbv(0xff)[CTRL_WIDTH:]) tx_start_packet_0 = Signal(bool(0)) tx_start_packet_4 = Signal(bool(0)) + tx_error_underflow = Signal(bool(0)) rx_start_packet_0 = Signal(bool(0)) rx_start_packet_4 = Signal(bool(0)) rx_error_bad_frame = Signal(bool(0)) @@ -176,6 +177,7 @@ def bench(): tx_start_packet_0=tx_start_packet_0, tx_start_packet_4=tx_start_packet_4, + tx_error_underflow=tx_error_underflow, rx_start_packet_0=rx_start_packet_0, rx_start_packet_4=rx_start_packet_4, rx_error_bad_frame=rx_error_bad_frame, diff --git a/tb/test_eth_mac_10g_32.v b/tb/test_eth_mac_10g_32.v index 351cf9f4..608dc024 100644 --- a/tb/test_eth_mac_10g_32.v +++ b/tb/test_eth_mac_10g_32.v @@ -68,6 +68,7 @@ wire [DATA_WIDTH-1:0] xgmii_txd; wire [CTRL_WIDTH-1:0] xgmii_txc; wire tx_start_packet_0; wire tx_start_packet_4; +wire tx_error_underflow; wire rx_start_packet_0; wire rx_start_packet_4; wire rx_error_bad_frame; @@ -103,6 +104,7 @@ initial begin xgmii_txc, tx_start_packet_0, tx_start_packet_4, + tx_error_underflow, rx_start_packet_0, rx_start_packet_4, rx_error_bad_frame, @@ -144,6 +146,7 @@ UUT ( .xgmii_txc(xgmii_txc), .tx_start_packet_0(tx_start_packet_0), .tx_start_packet_4(tx_start_packet_4), + .tx_error_underflow(tx_error_underflow), .rx_start_packet_0(rx_start_packet_0), .rx_start_packet_4(rx_start_packet_4), .rx_error_bad_frame(rx_error_bad_frame), diff --git a/tb/test_eth_mac_10g_64.py b/tb/test_eth_mac_10g_64.py index 6dbd63b2..aa0a731b 100755 --- a/tb/test_eth_mac_10g_64.py +++ b/tb/test_eth_mac_10g_64.py @@ -84,6 +84,7 @@ def bench(): xgmii_txc = Signal(intbv(0xff)[CTRL_WIDTH:]) tx_start_packet_0 = Signal(bool(0)) tx_start_packet_4 = Signal(bool(0)) + tx_error_underflow = Signal(bool(0)) rx_start_packet_0 = Signal(bool(0)) rx_start_packet_4 = Signal(bool(0)) rx_error_bad_frame = Signal(bool(0)) @@ -176,6 +177,7 @@ def bench(): tx_start_packet_0=tx_start_packet_0, tx_start_packet_4=tx_start_packet_4, + tx_error_underflow=tx_error_underflow, rx_start_packet_0=rx_start_packet_0, rx_start_packet_4=rx_start_packet_4, rx_error_bad_frame=rx_error_bad_frame, diff --git a/tb/test_eth_mac_10g_64.v b/tb/test_eth_mac_10g_64.v index 6713d056..50a164f5 100644 --- a/tb/test_eth_mac_10g_64.v +++ b/tb/test_eth_mac_10g_64.v @@ -68,6 +68,7 @@ wire [DATA_WIDTH-1:0] xgmii_txd; wire [CTRL_WIDTH-1:0] xgmii_txc; wire tx_start_packet_0; wire tx_start_packet_4; +wire tx_error_underflow; wire rx_start_packet_0; wire rx_start_packet_4; wire rx_error_bad_frame; @@ -103,6 +104,7 @@ initial begin xgmii_txc, tx_start_packet_0, tx_start_packet_4, + tx_error_underflow, rx_start_packet_0, rx_start_packet_4, rx_error_bad_frame, @@ -144,6 +146,7 @@ UUT ( .xgmii_txc(xgmii_txc), .tx_start_packet_0(tx_start_packet_0), .tx_start_packet_4(tx_start_packet_4), + .tx_error_underflow(tx_error_underflow), .rx_start_packet_0(rx_start_packet_0), .rx_start_packet_4(rx_start_packet_4), .rx_error_bad_frame(rx_error_bad_frame), diff --git a/tb/test_eth_mac_10g_fifo_32.py b/tb/test_eth_mac_10g_fifo_32.py index c68537a6..0488c8a3 100755 --- a/tb/test_eth_mac_10g_fifo_32.py +++ b/tb/test_eth_mac_10g_fifo_32.py @@ -89,6 +89,7 @@ def bench(): rx_axis_tuser = Signal(bool(0)) xgmii_txd = Signal(intbv(0x0707070707070707)[DATA_WIDTH:]) xgmii_txc = Signal(intbv(0xff)[CTRL_WIDTH:]) + tx_error_underflow = Signal(bool(0)) tx_fifo_overflow = Signal(bool(0)) tx_fifo_bad_frame = Signal(bool(0)) tx_fifo_good_frame = Signal(bool(0)) @@ -189,6 +190,7 @@ def bench(): xgmii_txd=xgmii_txd, xgmii_txc=xgmii_txc, + tx_error_underflow=tx_error_underflow, tx_fifo_overflow=tx_fifo_overflow, tx_fifo_bad_frame=tx_fifo_bad_frame, tx_fifo_good_frame=tx_fifo_good_frame, diff --git a/tb/test_eth_mac_10g_fifo_32.v b/tb/test_eth_mac_10g_fifo_32.v index f83c6893..02592b06 100644 --- a/tb/test_eth_mac_10g_fifo_32.v +++ b/tb/test_eth_mac_10g_fifo_32.v @@ -71,6 +71,7 @@ wire rx_axis_tlast; wire rx_axis_tuser; wire [DATA_WIDTH-1:0] xgmii_txd; wire [CTRL_WIDTH-1:0] xgmii_txc; +wire tx_error_underflow; wire tx_fifo_overflow; wire tx_fifo_bad_frame; wire tx_fifo_good_frame; @@ -111,6 +112,7 @@ initial begin rx_axis_tuser, xgmii_txd, xgmii_txc, + tx_error_underflow, tx_fifo_overflow, tx_fifo_bad_frame, tx_fifo_good_frame, @@ -159,6 +161,7 @@ UUT ( .xgmii_rxc(xgmii_rxc), .xgmii_txd(xgmii_txd), .xgmii_txc(xgmii_txc), + .tx_error_underflow(tx_error_underflow), .tx_fifo_overflow(tx_fifo_overflow), .tx_fifo_bad_frame(tx_fifo_bad_frame), .tx_fifo_good_frame(tx_fifo_good_frame), diff --git a/tb/test_eth_mac_10g_fifo_64.py b/tb/test_eth_mac_10g_fifo_64.py index 6d954097..71402866 100755 --- a/tb/test_eth_mac_10g_fifo_64.py +++ b/tb/test_eth_mac_10g_fifo_64.py @@ -89,6 +89,7 @@ def bench(): rx_axis_tuser = Signal(bool(0)) xgmii_txd = Signal(intbv(0x0707070707070707)[DATA_WIDTH:]) xgmii_txc = Signal(intbv(0xff)[CTRL_WIDTH:]) + tx_error_underflow = Signal(bool(0)) tx_fifo_overflow = Signal(bool(0)) tx_fifo_bad_frame = Signal(bool(0)) tx_fifo_good_frame = Signal(bool(0)) @@ -189,6 +190,7 @@ def bench(): xgmii_txd=xgmii_txd, xgmii_txc=xgmii_txc, + tx_error_underflow=tx_error_underflow, tx_fifo_overflow=tx_fifo_overflow, tx_fifo_bad_frame=tx_fifo_bad_frame, tx_fifo_good_frame=tx_fifo_good_frame, diff --git a/tb/test_eth_mac_10g_fifo_64.v b/tb/test_eth_mac_10g_fifo_64.v index cf87b62c..c035ceb0 100644 --- a/tb/test_eth_mac_10g_fifo_64.v +++ b/tb/test_eth_mac_10g_fifo_64.v @@ -71,6 +71,7 @@ wire rx_axis_tlast; wire rx_axis_tuser; wire [DATA_WIDTH-1:0] xgmii_txd; wire [CTRL_WIDTH-1:0] xgmii_txc; +wire tx_error_underflow; wire tx_fifo_overflow; wire tx_fifo_bad_frame; wire tx_fifo_good_frame; @@ -111,6 +112,7 @@ initial begin rx_axis_tuser, xgmii_txd, xgmii_txc, + tx_error_underflow, tx_fifo_overflow, tx_fifo_bad_frame, tx_fifo_good_frame, @@ -159,6 +161,7 @@ UUT ( .xgmii_rxc(xgmii_rxc), .xgmii_txd(xgmii_txd), .xgmii_txc(xgmii_txc), + .tx_error_underflow(tx_error_underflow), .tx_fifo_overflow(tx_fifo_overflow), .tx_fifo_bad_frame(tx_fifo_bad_frame), .tx_fifo_good_frame(tx_fifo_good_frame), diff --git a/tb/test_eth_mac_1g.py b/tb/test_eth_mac_1g.py index 285c373d..b1cd8816 100755 --- a/tb/test_eth_mac_1g.py +++ b/tb/test_eth_mac_1g.py @@ -83,6 +83,7 @@ def bench(): gmii_tx_en = Signal(bool(0)) gmii_tx_er = Signal(bool(0)) tx_start_packet = Signal(bool(0)) + tx_error_underflow = Signal(bool(0)) rx_start_packet = Signal(bool(0)) rx_error_bad_frame = Signal(bool(0)) rx_error_bad_fcs = Signal(bool(0)) @@ -183,6 +184,7 @@ def bench(): tx_mii_select=tx_mii_select, tx_start_packet=tx_start_packet, + tx_error_underflow=tx_error_underflow, rx_start_packet=rx_start_packet, rx_error_bad_frame=rx_error_bad_frame, rx_error_bad_fcs=rx_error_bad_fcs, diff --git a/tb/test_eth_mac_1g.v b/tb/test_eth_mac_1g.v index 12502af4..4f92c1e7 100644 --- a/tb/test_eth_mac_1g.v +++ b/tb/test_eth_mac_1g.v @@ -67,6 +67,7 @@ wire [7:0] gmii_txd; wire gmii_tx_en; wire gmii_tx_er; wire tx_start_packet; +wire tx_error_underflow; wire rx_start_packet; wire rx_error_bad_frame; wire rx_error_bad_fcs; @@ -104,6 +105,7 @@ initial begin gmii_tx_en, gmii_tx_er, tx_start_packet, + tx_error_underflow, rx_start_packet, rx_error_bad_frame, rx_error_bad_fcs @@ -143,6 +145,7 @@ UUT ( .rx_mii_select(rx_mii_select), .tx_mii_select(tx_mii_select), .tx_start_packet(tx_start_packet), + .tx_error_underflow(tx_error_underflow), .rx_start_packet(rx_start_packet), .rx_error_bad_frame(rx_error_bad_frame), .rx_error_bad_fcs(rx_error_bad_fcs), diff --git a/tb/test_eth_mac_1g_fifo.py b/tb/test_eth_mac_1g_fifo.py index bd3f6da0..df1feceb 100755 --- a/tb/test_eth_mac_1g_fifo.py +++ b/tb/test_eth_mac_1g_fifo.py @@ -89,6 +89,7 @@ def bench(): gmii_txd = Signal(intbv(0)[8:]) gmii_tx_en = Signal(bool(0)) gmii_tx_er = Signal(bool(0)) + tx_error_underflow = Signal(bool(0)) tx_fifo_overflow = Signal(bool(0)) tx_fifo_bad_frame = Signal(bool(0)) tx_fifo_good_frame = Signal(bool(0)) @@ -199,6 +200,7 @@ def bench(): rx_mii_select=rx_mii_select, tx_mii_select=tx_mii_select, + tx_error_underflow=tx_error_underflow, tx_fifo_overflow=tx_fifo_overflow, tx_fifo_bad_frame=tx_fifo_bad_frame, tx_fifo_good_frame=tx_fifo_good_frame, diff --git a/tb/test_eth_mac_1g_fifo.v b/tb/test_eth_mac_1g_fifo.v index 0b20f923..ea7e9cca 100644 --- a/tb/test_eth_mac_1g_fifo.v +++ b/tb/test_eth_mac_1g_fifo.v @@ -71,6 +71,7 @@ wire rx_axis_tuser; wire [7:0] gmii_txd; wire gmii_tx_en; wire gmii_tx_er; +wire tx_error_underflow; wire tx_fifo_overflow; wire tx_fifo_bad_frame; wire tx_fifo_good_frame; @@ -115,6 +116,7 @@ initial begin gmii_txd, gmii_tx_en, gmii_tx_er, + tx_error_underflow, tx_fifo_overflow, tx_fifo_bad_frame, tx_fifo_good_frame, @@ -163,6 +165,7 @@ UUT ( .tx_clk_enable(tx_clk_enable), .rx_mii_select(rx_mii_select), .tx_mii_select(tx_mii_select), + .tx_error_underflow(tx_error_underflow), .tx_fifo_overflow(tx_fifo_overflow), .tx_fifo_bad_frame(tx_fifo_bad_frame), .tx_fifo_good_frame(tx_fifo_good_frame), diff --git a/tb/test_eth_mac_1g_gmii.py b/tb/test_eth_mac_1g_gmii.py index 0949654a..d21f1335 100755 --- a/tb/test_eth_mac_1g_gmii.py +++ b/tb/test_eth_mac_1g_gmii.py @@ -91,6 +91,7 @@ def bench(): gmii_txd = Signal(intbv(0)[8:]) gmii_tx_en = Signal(bool(0)) gmii_tx_er = Signal(bool(0)) + tx_error_underflow = Signal(bool(0)) rx_error_bad_frame = Signal(bool(0)) rx_error_bad_fcs = Signal(bool(0)) speed = Signal(intbv(0)[2:]) @@ -190,6 +191,7 @@ def bench(): gmii_tx_en=gmii_tx_en, gmii_tx_er=gmii_tx_er, + tx_error_underflow=tx_error_underflow, rx_error_bad_frame=rx_error_bad_frame, rx_error_bad_fcs=rx_error_bad_fcs, speed=speed, diff --git a/tb/test_eth_mac_1g_gmii.v b/tb/test_eth_mac_1g_gmii.v index 1a14270f..660bd6db 100644 --- a/tb/test_eth_mac_1g_gmii.v +++ b/tb/test_eth_mac_1g_gmii.v @@ -70,6 +70,7 @@ wire gmii_tx_clk; wire [7:0] gmii_txd; wire gmii_tx_en; wire gmii_tx_er; +wire tx_error_underflow; wire rx_error_bad_frame; wire rx_error_bad_fcs; wire [1:0] speed; @@ -107,6 +108,7 @@ initial begin gmii_txd, gmii_tx_en, gmii_tx_er, + tx_error_underflow, rx_error_bad_frame, rx_error_bad_fcs, speed @@ -149,6 +151,7 @@ UUT ( .gmii_txd(gmii_txd), .gmii_tx_en(gmii_tx_en), .gmii_tx_er(gmii_tx_er), + .tx_error_underflow(tx_error_underflow), .rx_error_bad_frame(rx_error_bad_frame), .rx_error_bad_fcs(rx_error_bad_fcs), .speed(speed), diff --git a/tb/test_eth_mac_1g_gmii_fifo.py b/tb/test_eth_mac_1g_gmii_fifo.py index b62c5ed6..fef5f144 100755 --- a/tb/test_eth_mac_1g_gmii_fifo.py +++ b/tb/test_eth_mac_1g_gmii_fifo.py @@ -94,6 +94,7 @@ def bench(): gmii_txd = Signal(intbv(0)[8:]) gmii_tx_en = Signal(bool(0)) gmii_tx_er = Signal(bool(0)) + tx_error_underflow = Signal(bool(0)) tx_fifo_overflow = Signal(bool(0)) tx_fifo_bad_frame = Signal(bool(0)) tx_fifo_good_frame = Signal(bool(0)) @@ -200,6 +201,7 @@ def bench(): gmii_tx_en=gmii_tx_en, gmii_tx_er=gmii_tx_er, + tx_error_underflow=tx_error_underflow, tx_fifo_overflow=tx_fifo_overflow, tx_fifo_bad_frame=tx_fifo_bad_frame, tx_fifo_good_frame=tx_fifo_good_frame, diff --git a/tb/test_eth_mac_1g_gmii_fifo.v b/tb/test_eth_mac_1g_gmii_fifo.v index 04da0192..6c60bba7 100644 --- a/tb/test_eth_mac_1g_gmii_fifo.v +++ b/tb/test_eth_mac_1g_gmii_fifo.v @@ -71,6 +71,7 @@ wire gmii_tx_clk; wire [7:0] gmii_txd; wire gmii_tx_en; wire gmii_tx_er; +wire tx_error_underflow; wire tx_fifo_overflow; wire tx_fifo_bad_frame; wire tx_fifo_good_frame; @@ -113,6 +114,7 @@ initial begin gmii_txd, gmii_tx_en, gmii_tx_er, + tx_error_underflow, tx_fifo_overflow, tx_fifo_bad_frame, tx_fifo_good_frame, @@ -162,6 +164,7 @@ UUT ( .gmii_txd(gmii_txd), .gmii_tx_en(gmii_tx_en), .gmii_tx_er(gmii_tx_er), + .tx_error_underflow(tx_error_underflow), .tx_fifo_overflow(tx_fifo_overflow), .tx_fifo_bad_frame(tx_fifo_bad_frame), .tx_fifo_good_frame(tx_fifo_good_frame), diff --git a/tb/test_eth_mac_1g_rgmii.py b/tb/test_eth_mac_1g_rgmii.py index ba777e13..e84460f6 100755 --- a/tb/test_eth_mac_1g_rgmii.py +++ b/tb/test_eth_mac_1g_rgmii.py @@ -91,6 +91,7 @@ def bench(): rgmii_tx_clk = Signal(bool(0)) rgmii_txd = Signal(intbv(0)[4:]) rgmii_tx_ctl = Signal(bool(0)) + tx_error_underflow = Signal(bool(0)) rx_error_bad_frame = Signal(bool(0)) rx_error_bad_fcs = Signal(bool(0)) speed = Signal(intbv(0)[2:]) @@ -186,6 +187,7 @@ def bench(): rgmii_txd=rgmii_txd, rgmii_tx_ctl=rgmii_tx_ctl, + tx_error_underflow=tx_error_underflow, rx_error_bad_frame=rx_error_bad_frame, rx_error_bad_fcs=rx_error_bad_fcs, speed=speed, diff --git a/tb/test_eth_mac_1g_rgmii.v b/tb/test_eth_mac_1g_rgmii.v index 918acf72..0313fa09 100644 --- a/tb/test_eth_mac_1g_rgmii.v +++ b/tb/test_eth_mac_1g_rgmii.v @@ -69,6 +69,7 @@ wire rx_axis_tuser; wire rgmii_tx_clk; wire [3:0] rgmii_txd; wire rgmii_tx_ctl; +wire tx_error_underflow; wire rx_error_bad_frame; wire rx_error_bad_fcs; wire [1:0] speed; @@ -104,6 +105,7 @@ initial begin rgmii_tx_clk, rgmii_txd, rgmii_tx_ctl, + tx_error_underflow, rx_error_bad_frame, rx_error_bad_fcs, speed @@ -145,6 +147,7 @@ UUT ( .rgmii_tx_clk(rgmii_tx_clk), .rgmii_txd(rgmii_txd), .rgmii_tx_ctl(rgmii_tx_ctl), + .tx_error_underflow(tx_error_underflow), .rx_error_bad_frame(rx_error_bad_frame), .rx_error_bad_fcs(rx_error_bad_fcs), .speed(speed), diff --git a/tb/test_eth_mac_1g_rgmii_fifo.py b/tb/test_eth_mac_1g_rgmii_fifo.py index 764e49b9..2840402d 100755 --- a/tb/test_eth_mac_1g_rgmii_fifo.py +++ b/tb/test_eth_mac_1g_rgmii_fifo.py @@ -92,6 +92,7 @@ def bench(): rgmii_tx_clk = Signal(bool(0)) rgmii_txd = Signal(intbv(0)[4:]) rgmii_tx_ctl = Signal(bool(0)) + tx_error_underflow = Signal(bool(0)) tx_fifo_overflow = Signal(bool(0)) tx_fifo_bad_frame = Signal(bool(0)) tx_fifo_good_frame = Signal(bool(0)) @@ -194,6 +195,7 @@ def bench(): rgmii_txd=rgmii_txd, rgmii_tx_ctl=rgmii_tx_ctl, + tx_error_underflow=tx_error_underflow, tx_fifo_overflow=tx_fifo_overflow, tx_fifo_bad_frame=tx_fifo_bad_frame, tx_fifo_good_frame=tx_fifo_good_frame, diff --git a/tb/test_eth_mac_1g_rgmii_fifo.v b/tb/test_eth_mac_1g_rgmii_fifo.v index 7664454c..e141b3c2 100644 --- a/tb/test_eth_mac_1g_rgmii_fifo.v +++ b/tb/test_eth_mac_1g_rgmii_fifo.v @@ -70,6 +70,7 @@ wire rx_axis_tuser; wire rgmii_tx_clk; wire [3:0] rgmii_txd; wire rgmii_tx_ctl; +wire tx_error_underflow; wire tx_fifo_overflow; wire tx_fifo_bad_frame; wire tx_fifo_good_frame; @@ -110,6 +111,7 @@ initial begin rgmii_tx_clk, rgmii_txd, rgmii_tx_ctl, + tx_error_underflow, tx_fifo_overflow, tx_fifo_bad_frame, tx_fifo_good_frame, @@ -158,6 +160,7 @@ UUT ( .rgmii_tx_clk(rgmii_tx_clk), .rgmii_txd(rgmii_txd), .rgmii_tx_ctl(rgmii_tx_ctl), + .tx_error_underflow(tx_error_underflow), .tx_fifo_overflow(tx_fifo_overflow), .tx_fifo_bad_frame(tx_fifo_bad_frame), .tx_fifo_good_frame(tx_fifo_good_frame), diff --git a/tb/test_eth_mac_phy_10g.py b/tb/test_eth_mac_phy_10g.py index 0eda4e24..f9650fbd 100755 --- a/tb/test_eth_mac_phy_10g.py +++ b/tb/test_eth_mac_phy_10g.py @@ -98,6 +98,7 @@ def bench(): serdes_rx_bitslip = Signal(bool(0)) tx_start_packet_0 = Signal(bool(0)) tx_start_packet_4 = Signal(bool(0)) + tx_error_underflow = Signal(bool(0)) rx_start_packet_0 = Signal(bool(0)) rx_start_packet_4 = Signal(bool(0)) rx_error_bad_frame = Signal(bool(0)) @@ -185,6 +186,7 @@ def bench(): serdes_rx_bitslip=serdes_rx_bitslip, tx_start_packet_0=tx_start_packet_0, tx_start_packet_4=tx_start_packet_4, + tx_error_underflow=tx_error_underflow, rx_start_packet_0=rx_start_packet_0, rx_start_packet_4=rx_start_packet_4, rx_error_bad_frame=rx_error_bad_frame, diff --git a/tb/test_eth_mac_phy_10g.v b/tb/test_eth_mac_phy_10g.v index 2937762b..825302e1 100644 --- a/tb/test_eth_mac_phy_10g.v +++ b/tb/test_eth_mac_phy_10g.v @@ -74,6 +74,7 @@ wire [HDR_WIDTH-1:0] serdes_tx_hdr; wire serdes_rx_bitslip; wire tx_start_packet_0; wire tx_start_packet_4; +wire tx_error_underflow; wire rx_start_packet_0; wire rx_start_packet_4; wire rx_error_bad_frame; @@ -112,6 +113,7 @@ initial begin serdes_rx_bitslip, tx_start_packet_0, tx_start_packet_4, + tx_error_underflow, rx_start_packet_0, rx_start_packet_4, rx_error_bad_frame, @@ -161,6 +163,7 @@ UUT ( .serdes_rx_bitslip(serdes_rx_bitslip), .tx_start_packet_0(tx_start_packet_0), .tx_start_packet_4(tx_start_packet_4), + .tx_error_underflow(tx_error_underflow), .rx_start_packet_0(rx_start_packet_0), .rx_start_packet_4(rx_start_packet_4), .rx_error_bad_frame(rx_error_bad_frame), diff --git a/tb/test_eth_mac_phy_10g_fifo.py b/tb/test_eth_mac_phy_10g_fifo.py index df34ef40..e87bd9a4 100755 --- a/tb/test_eth_mac_phy_10g_fifo.py +++ b/tb/test_eth_mac_phy_10g_fifo.py @@ -109,6 +109,7 @@ def bench(): serdes_tx_data = Signal(intbv(0)[DATA_WIDTH:]) serdes_tx_hdr = Signal(intbv(1)[HDR_WIDTH:]) serdes_rx_bitslip = Signal(bool(0)) + tx_error_underflow = Signal(bool(0)) tx_fifo_overflow = Signal(bool(0)) tx_fifo_bad_frame = Signal(bool(0)) tx_fifo_good_frame = Signal(bool(0)) @@ -202,6 +203,7 @@ def bench(): serdes_rx_data=serdes_rx_data, serdes_rx_hdr=serdes_rx_hdr, serdes_rx_bitslip=serdes_rx_bitslip, + tx_error_underflow=tx_error_underflow, tx_fifo_overflow=tx_fifo_overflow, tx_fifo_bad_frame=tx_fifo_bad_frame, tx_fifo_good_frame=tx_fifo_good_frame, diff --git a/tb/test_eth_mac_phy_10g_fifo.v b/tb/test_eth_mac_phy_10g_fifo.v index c838c79b..7c09e923 100644 --- a/tb/test_eth_mac_phy_10g_fifo.v +++ b/tb/test_eth_mac_phy_10g_fifo.v @@ -83,6 +83,7 @@ wire rx_axis_tuser; wire [DATA_WIDTH-1:0] serdes_tx_data; wire [HDR_WIDTH-1:0] serdes_tx_hdr; wire serdes_rx_bitslip; +wire tx_error_underflow; wire tx_fifo_overflow; wire tx_fifo_bad_frame; wire tx_fifo_good_frame; @@ -126,6 +127,7 @@ initial begin serdes_tx_data, serdes_tx_hdr, serdes_rx_bitslip, + tx_error_underflow, tx_fifo_overflow, tx_fifo_bad_frame, tx_fifo_good_frame, @@ -188,6 +190,7 @@ UUT ( .serdes_rx_data(serdes_rx_data), .serdes_rx_hdr(serdes_rx_hdr), .serdes_rx_bitslip(serdes_rx_bitslip), + .tx_error_underflow(tx_error_underflow), .tx_fifo_overflow(tx_fifo_overflow), .tx_fifo_bad_frame(tx_fifo_bad_frame), .tx_fifo_good_frame(tx_fifo_good_frame),