merged changes in axis

lib/axis/rtl/axis_arb_mux.py

@@ -13,7 +13,7 @@ Usage: axis_arb_mux [OPTION]...
 import io
 import sys
 import getopt
-from math import *
+import math
 from jinja2 import Template
 
 class Usage(Exception):
@@ -66,7 +66,7 @@ def main(argv=None):
 
     print("Generating {0} port AXI Stream arbitrated mux {1}...".format(ports, name))
 
-    select_width = ceil(log2(ports))
+    select_width = int(math.ceil(math.log(ports, 2)))
 
     t = Template(u"""/*
 

lib/axis/rtl/axis_arb_mux_64.py

@@ -13,7 +13,7 @@ Usage: axis_arb_mux_64 [OPTION]...
 import io
 import sys
 import getopt
-from math import *
+import math
 from jinja2 import Template
 
 class Usage(Exception):
@@ -66,7 +66,7 @@ def main(argv=None):
 
     print("Generating {0} port AXI Stream arbitrated mux {1}...".format(ports, name))
 
-    select_width = ceil(log2(ports))
+    select_width = int(math.ceil(math.log(ports, 2)))
 
     t = Template(u"""/*
 

lib/axis/rtl/axis_async_fifo.v

@@ -78,8 +78,6 @@ reg [DATA_WIDTH+2-1:0] data_out_reg = {1'b0, 1'b0, {DATA_WIDTH{1'b0}}};
 //(* RAM_STYLE="BLOCK" *)
 reg [DATA_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0];
 
-reg output_read = 1'b0;
-
 reg output_axis_tvalid_reg = 1'b0;
 
 wire [DATA_WIDTH+2-1:0] data_in = {input_axis_tlast, input_axis_tuser, input_axis_tdata};
@@ -125,6 +123,7 @@ end
 always @(posedge input_clk or posedge input_rst_sync2) begin
     if (input_rst_sync2) begin
         wr_ptr <= 0;
+        wr_ptr_gray <= 0;
     end else if (write) begin
         mem[wr_ptr[ADDR_WIDTH-1:0]] <= data_in;
         wr_ptr_next = wr_ptr + 1;
@@ -148,6 +147,7 @@ end
 always @(posedge output_clk or posedge output_rst_sync2) begin
     if (output_rst_sync2) begin
         rd_ptr <= 0;
+        rd_ptr_gray <= 0;
     end else if (read) begin
         data_out_reg <= mem[rd_ptr[ADDR_WIDTH-1:0]];
         rd_ptr_next = rd_ptr + 1;

lib/axis/rtl/axis_async_fifo_64.v

@@ -81,8 +81,6 @@ reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] data_out_reg = {1'b0, 1'b0, {KEEP_WIDTH{1'b0}}
 //(* RAM_STYLE="BLOCK" *)
 reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0];
 
-reg output_read = 1'b0;
-
 reg output_axis_tvalid_reg = 1'b0;
 
 wire [DATA_WIDTH+KEEP_WIDTH+2-1:0] data_in = {input_axis_tlast, input_axis_tuser, input_axis_tkeep, input_axis_tdata};
@@ -128,6 +126,7 @@ end
 always @(posedge input_clk or posedge input_rst_sync2) begin
     if (input_rst_sync2) begin
         wr_ptr <= 0;
+        wr_ptr_gray <= 0;
     end else if (write) begin
         mem[wr_ptr[ADDR_WIDTH-1:0]] <= data_in;
         wr_ptr_next = wr_ptr + 1;
@@ -151,6 +150,7 @@ end
 always @(posedge output_clk or posedge output_rst_sync2) begin
     if (output_rst_sync2) begin
         rd_ptr <= 0;
+        rd_ptr_gray <= 0;
     end else if (read) begin
         data_out_reg <= mem[rd_ptr[ADDR_WIDTH-1:0]];
         rd_ptr_next = rd_ptr + 1;

lib/axis/rtl/axis_crosspoint.py

@@ -13,7 +13,7 @@ Usage: axis_crosspoint [OPTION]...
 import io
 import sys
 import getopt
-from math import *
+import math
 from jinja2 import Template
 
 class Usage(Exception):
@@ -66,7 +66,7 @@ def main(argv=None):
 
     print("Generating {0} port AXI Stream crosspoint {1}...".format(ports, name))
 
-    select_width = ceil(log2(ports))
+    select_width = int(math.ceil(math.log(ports, 2)))
 
     t = Template(u"""/*
 

lib/axis/rtl/axis_crosspoint_64.py

@@ -13,7 +13,7 @@ Usage: axis_crosspoint_64 [OPTION]...
 import io
 import sys
 import getopt
-from math import *
+import math
 from jinja2 import Template
 
 class Usage(Exception):
@@ -66,7 +66,7 @@ def main(argv=None):
 
     print("Generating {0} port AXI Stream crosspoint {1}...".format(ports, name))
 
-    select_width = ceil(log2(ports))
+    select_width = int(math.ceil(math.log(ports, 2)))
 
     t = Template(u"""/*
 

lib/axis/rtl/axis_demux.py

@@ -13,7 +13,7 @@ Usage: axis_demux [OPTION]...
 import io
 import sys
 import getopt
-from math import *
+import math
 from jinja2 import Template
 
 class Usage(Exception):
@@ -66,7 +66,7 @@ def main(argv=None):
 
     print("Generating {0} port AXI Stream demux {1}...".format(ports, name))
 
-    select_width = ceil(log2(ports))
+    select_width = int(math.ceil(math.log(ports, 2)))
 
     t = Template(u"""/*
 

lib/axis/rtl/axis_demux_64.py

@@ -13,7 +13,7 @@ Usage: axis_demux_64 [OPTION]...
 import io
 import sys
 import getopt
-from math import *
+import math
 from jinja2 import Template
 
 class Usage(Exception):
@@ -66,7 +66,7 @@ def main(argv=None):
 
     print("Generating {0} port AXI Stream demux {1}...".format(ports, name))
 
-    select_width = ceil(log2(ports))
+    select_width = int(math.ceil(math.log(ports, 2)))
 
     t = Template(u"""/*
 

lib/axis/rtl/axis_fifo.v

@@ -65,8 +65,6 @@ reg [DATA_WIDTH+2-1:0] data_out_reg = {1'b0, 1'b0, {DATA_WIDTH{1'b0}}};
 //(* RAM_STYLE="BLOCK" *)
 reg [DATA_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0];
 
-reg output_read = 1'b0;
-
 reg output_axis_tvalid_reg = 1'b0;
 
 wire [DATA_WIDTH+2-1:0] data_in = {input_axis_tlast, input_axis_tuser, input_axis_tdata};

lib/axis/rtl/axis_fifo_64.v

@@ -68,8 +68,6 @@ reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] data_out_reg = {1'b0, 1'b0, {KEEP_WIDTH{1'b0}}
 //(* RAM_STYLE="BLOCK" *)
 reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0];
 
-reg output_read = 1'b0;
-
 reg output_axis_tvalid_reg = 1'b0;
 
 wire [DATA_WIDTH+KEEP_WIDTH+2-1:0] data_in = {input_axis_tlast, input_axis_tuser, input_axis_tkeep, input_axis_tdata};

lib/axis/rtl/axis_frame_join.py

@@ -13,7 +13,7 @@ Usage: axis_frame_join [OPTION]...
 import io
 import sys
 import getopt
-from math import *
+import math
 from jinja2 import Template
 
 class Usage(Exception):
@@ -66,7 +66,7 @@ def main(argv=None):
     
     print("Generating {0} port AXI Stream frame joiner {1}...".format(ports, name))
     
-    select_width = ceil(log2(ports))
+    select_width = int(math.ceil(math.log(ports, 2)))
     
     t = Template(u"""/*
 

lib/axis/rtl/axis_mux.py

@@ -13,7 +13,7 @@ Usage: axis_mux [OPTION]...
 import io
 import sys
 import getopt
-from math import *
+import math
 from jinja2 import Template
 
 class Usage(Exception):
@@ -66,7 +66,7 @@ def main(argv=None):
 
     print("Generating {0} port AXI Stream mux {1}...".format(ports, name))
 
-    select_width = ceil(log2(ports))
+    select_width = int(math.ceil(math.log(ports, 2)))
 
     t = Template(u"""/*
 

lib/axis/rtl/axis_mux_64.py

@@ -13,7 +13,7 @@ Usage: axis_mux_64 [OPTION]...
 import io
 import sys
 import getopt
-from math import *
+import math
 from jinja2 import Template
 
 class Usage(Exception):
@@ -66,7 +66,7 @@ def main(argv=None):
 
     print("Generating {0} port AXI Stream mux {1}...".format(ports, name))
 
-    select_width = ceil(log2(ports))
+    select_width = int(math.ceil(math.log(ports, 2)))
 
     t = Template(u"""/*
 

lib/axis/tb/test_axis_async_fifo.py

@@ -401,6 +401,90 @@ def bench():
 
         yield delay(100)
 
+        yield input_clk.posedge
+        print("test 8: initial sink pause")
+        current_test.next = 8
+
+        test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+        sink_pause.next = 0
+
+        yield output_axis_tlast.posedge
+        yield output_clk.posedge
+        yield output_clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame
+
+        yield delay(100)
+
+        yield input_clk.posedge
+        print("test 9: initial sink pause, input reset")
+        current_test.next = 9
+
+        test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+
+        input_rst.next = 1
+        yield input_clk.posedge
+        input_rst.next = 0
+
+        sink_pause.next = 0
+
+        yield delay(100)
+
+        yield output_clk.posedge
+        yield output_clk.posedge
+        yield output_clk.posedge
+
+        assert sink_queue.empty()
+
+        yield delay(100)
+
+        yield input_clk.posedge
+        print("test 10: initial sink pause, output reset")
+        current_test.next = 10
+
+        test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+
+        output_rst.next = 1
+        yield output_clk.posedge
+        output_rst.next = 0
+
+        sink_pause.next = 0
+
+        yield delay(100)
+
+        yield output_clk.posedge
+        yield output_clk.posedge
+        yield output_clk.posedge
+
+        assert sink_queue.empty()
+
+        yield delay(100)
+
         raise StopSimulation
 
     return dut, source, sink, input_clkgen, output_clkgen, check

lib/axis/tb/test_axis_async_fifo_64.py

@@ -411,6 +411,90 @@ def bench():
 
         yield delay(100)
 
+        yield input_clk.posedge
+        print("test 8: initial sink pause")
+        current_test.next = 8
+
+        test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+        sink_pause.next = 0
+
+        yield output_axis_tlast.posedge
+        yield output_clk.posedge
+        yield output_clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame
+
+        yield delay(100)
+
+        yield input_clk.posedge
+        print("test 9: initial sink pause, input reset")
+        current_test.next = 9
+
+        test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+
+        input_rst.next = 1
+        yield input_clk.posedge
+        input_rst.next = 0
+
+        sink_pause.next = 0
+
+        yield delay(100)
+
+        yield output_clk.posedge
+        yield output_clk.posedge
+        yield output_clk.posedge
+
+        assert sink_queue.empty()
+
+        yield delay(100)
+
+        yield input_clk.posedge
+        print("test 10: initial sink pause, output reset")
+        current_test.next = 10
+
+        test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+
+        output_rst.next = 1
+        yield output_clk.posedge
+        output_rst.next = 0
+
+        sink_pause.next = 0
+
+        yield delay(100)
+
+        yield output_clk.posedge
+        yield output_clk.posedge
+        yield output_clk.posedge
+
+        assert sink_queue.empty()
+
+        yield delay(100)
+
         raise StopSimulation
 
     return dut, source, sink, input_clkgen, output_clkgen, check

lib/axis/tb/test_axis_async_frame_fifo.py

@@ -510,6 +510,90 @@ def bench():
 
         yield delay(100)
 
+        yield input_clk.posedge
+        print("test 9: initial sink pause")
+        current_test.next = 9
+
+        test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+        sink_pause.next = 0
+
+        yield output_axis_tlast.posedge
+        yield output_clk.posedge
+        yield output_clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame
+
+        yield delay(100)
+
+        yield input_clk.posedge
+        print("test 10: initial sink pause, input reset")
+        current_test.next = 10
+
+        test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+
+        input_rst.next = 1
+        yield input_clk.posedge
+        input_rst.next = 0
+
+        sink_pause.next = 0
+
+        yield delay(100)
+
+        yield output_clk.posedge
+        yield output_clk.posedge
+        yield output_clk.posedge
+
+        assert sink_queue.empty()
+
+        yield delay(100)
+
+        yield input_clk.posedge
+        print("test 11: initial sink pause, output reset")
+        current_test.next = 11
+
+        test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+
+        output_rst.next = 1
+        yield output_clk.posedge
+        output_rst.next = 0
+
+        sink_pause.next = 0
+
+        yield delay(100)
+
+        yield output_clk.posedge
+        yield output_clk.posedge
+        yield output_clk.posedge
+
+        assert sink_queue.empty()
+
+        yield delay(100)
+
         raise StopSimulation
 
     return dut, monitor, source, sink, input_clkgen, output_clkgen, check

lib/axis/tb/test_axis_async_frame_fifo_64.py

@@ -520,6 +520,90 @@ def bench():
 
         yield delay(100)
 
+        yield input_clk.posedge
+        print("test 9: initial sink pause")
+        current_test.next = 9
+
+        test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+        sink_pause.next = 0
+
+        yield output_axis_tlast.posedge
+        yield output_clk.posedge
+        yield output_clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame
+
+        yield delay(100)
+
+        yield input_clk.posedge
+        print("test 10: initial sink pause, input reset")
+        current_test.next = 10
+
+        test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+
+        input_rst.next = 1
+        yield input_clk.posedge
+        input_rst.next = 0
+
+        sink_pause.next = 0
+
+        yield delay(100)
+
+        yield output_clk.posedge
+        yield output_clk.posedge
+        yield output_clk.posedge
+
+        assert sink_queue.empty()
+
+        yield delay(100)
+
+        yield input_clk.posedge
+        print("test 11: initial sink pause, output reset")
+        current_test.next = 11
+
+        test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+
+        output_rst.next = 1
+        yield output_clk.posedge
+        output_rst.next = 0
+
+        sink_pause.next = 0
+
+        yield delay(100)
+
+        yield output_clk.posedge
+        yield output_clk.posedge
+        yield output_clk.posedge
+
+        assert sink_queue.empty()
+
+        yield delay(100)
+
         raise StopSimulation
 
     return dut, monitor, source, sink, input_clkgen, output_clkgen, check

lib/axis/tb/test_axis_fifo.py

@@ -385,6 +385,61 @@ def bench():
 
         yield delay(100)
 
+        yield clk.posedge
+        print("test 8: initial sink pause")
+        current_test.next = 8
+
+        test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+        sink_pause.next = 0
+
+        yield output_axis_tlast.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 9: initial sink pause, reset")
+        current_test.next = 9
+
+        test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rst.next = 1
+        yield clk.posedge
+        rst.next = 0
+
+        sink_pause.next = 0
+
+        yield delay(100)
+
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        assert sink_queue.empty()
+
+        yield delay(100)
+
         raise StopSimulation
 
     return dut, source, sink, clkgen, check

lib/axis/tb/test_axis_fifo_64.py

@@ -395,6 +395,61 @@ def bench():
 
         yield delay(100)
 
+        yield clk.posedge
+        print("test 8: initial sink pause")
+        current_test.next = 8
+
+        test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+        sink_pause.next = 0
+
+        yield output_axis_tlast.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 9: initial sink pause, reset")
+        current_test.next = 9
+
+        test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rst.next = 1
+        yield clk.posedge
+        rst.next = 0
+
+        sink_pause.next = 0
+
+        yield delay(100)
+
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        assert sink_queue.empty()
+
+        yield delay(100)
+
         raise StopSimulation
 
     return dut, source, sink, clkgen, check

lib/axis/tb/test_axis_frame_fifo.py

@@ -490,6 +490,61 @@ def bench():
 
         yield delay(100)
 
+        yield clk.posedge
+        print("test 9: initial sink pause")
+        current_test.next = 9
+
+        test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+        sink_pause.next = 0
+
+        yield output_axis_tlast.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 10: initial sink pause, reset")
+        current_test.next = 10
+
+        test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rst.next = 1
+        yield clk.posedge
+        rst.next = 0
+
+        sink_pause.next = 0
+
+        yield delay(100)
+
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        assert sink_queue.empty()
+
+        yield delay(100)
+
         raise StopSimulation
 
     return dut, monitor, source, sink, clkgen, check

lib/axis/tb/test_axis_frame_fifo_64.py

@@ -505,6 +505,61 @@ def bench():
 
         yield delay(100)
 
+        yield clk.posedge
+        print("test 9: initial sink pause")
+        current_test.next = 9
+
+        test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+        sink_pause.next = 0
+
+        yield output_axis_tlast.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 10: initial sink pause, reset")
+        current_test.next = 10
+
+        test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rst.next = 1
+        yield clk.posedge
+        rst.next = 0
+
+        sink_pause.next = 0
+
+        yield delay(100)
+
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        assert sink_queue.empty()
+
+        yield delay(100)
+
         raise StopSimulation
 
     return dut, monitor, source, sink, clkgen, check