Add transceiver reset watchdog

rtl/eth_phy_10g.v

@@ -65,6 +65,7 @@ module eth_phy_10g #
     input  wire [DATA_WIDTH-1:0] serdes_rx_data,
     input  wire [HDR_WIDTH-1:0]  serdes_rx_hdr,
     output wire                  serdes_rx_bitslip,
+    output wire                  serdes_rx_reset_req,
 
     /*
      * Status
@@ -103,6 +104,7 @@ eth_phy_10g_rx_inst (
     .serdes_rx_data(serdes_rx_data),
     .serdes_rx_hdr(serdes_rx_hdr),
     .serdes_rx_bitslip(serdes_rx_bitslip),
+    .serdes_rx_reset_req(serdes_rx_reset_req),
     .rx_error_count(rx_error_count),
     .rx_bad_block(rx_bad_block),
     .rx_sequence_error(rx_sequence_error),

rtl/eth_phy_10g_rx.v

@@ -58,6 +58,7 @@ module eth_phy_10g_rx #
     input  wire [DATA_WIDTH-1:0] serdes_rx_data,
     input  wire [HDR_WIDTH-1:0]  serdes_rx_hdr,
     output wire                  serdes_rx_bitslip,
+    output wire                  serdes_rx_reset_req,
 
     /*
      * Status
@@ -114,6 +115,9 @@ eth_phy_10g_rx_if_inst (
     .serdes_rx_data(serdes_rx_data),
     .serdes_rx_hdr(serdes_rx_hdr),
     .serdes_rx_bitslip(serdes_rx_bitslip),
+    .serdes_rx_reset_req(serdes_rx_reset_req),
+    .rx_bad_block(rx_bad_block),
+    .rx_sequence_error(rx_sequence_error),
     .rx_error_count(rx_error_count),
     .rx_block_lock(rx_block_lock),
     .rx_high_ber(rx_high_ber),

rtl/eth_phy_10g_rx_if.v

@@ -57,10 +57,13 @@ module eth_phy_10g_rx_if #
     input  wire [DATA_WIDTH-1:0] serdes_rx_data,
     input  wire [HDR_WIDTH-1:0]  serdes_rx_hdr,
     output wire                  serdes_rx_bitslip,
+    output wire                  serdes_rx_reset_req,
 
     /*
      * Status
      */
+    input  wire                  rx_bad_block,
+    input  wire                  rx_sequence_error,
     output wire [6:0]            rx_error_count,
     output wire                  rx_block_lock,
     output wire                  rx_high_ber,
@@ -215,7 +218,9 @@ assign encoded_rx_hdr = encoded_rx_hdr_reg;
 assign rx_error_count = rx_error_count_reg;
 
 wire serdes_rx_bitslip_int;
+wire serdes_rx_reset_req_int;
 assign serdes_rx_bitslip = serdes_rx_bitslip_int && !(PRBS31_ENABLE && rx_prbs31_enable);
+assign serdes_rx_reset_req = serdes_rx_reset_req_int && !(PRBS31_ENABLE && rx_prbs31_enable);
 
 eth_phy_10g_rx_frame_sync #(
     .HDR_WIDTH(HDR_WIDTH),
@@ -241,4 +246,19 @@ eth_phy_10g_rx_ber_mon_inst (
     .rx_high_ber(rx_high_ber)
 );
 
+eth_phy_10g_rx_watchdog #(
+    .HDR_WIDTH(HDR_WIDTH),
+    .COUNT_125US(COUNT_125US)
+)
+eth_phy_10g_rx_watchdog_inst (
+    .clk(clk),
+    .rst(rst),
+    .serdes_rx_hdr(serdes_rx_hdr_int),
+    .serdes_rx_reset_req(serdes_rx_reset_req_int),
+    .rx_bad_block(rx_bad_block),
+    .rx_sequence_error(rx_sequence_error),
+    .rx_block_lock(rx_block_lock),
+    .rx_high_ber(rx_high_ber)
+);
+
 endmodule

rtl/eth_phy_10g_rx_watchdog.v

@@ -0,0 +1,140 @@
+/*
+
+Copyright (c) 2021 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * 10G Ethernet PHY serdes watchdog
+ */
+module eth_phy_10g_rx_watchdog #
+(
+    parameter HDR_WIDTH = 2,
+    parameter COUNT_125US = 125000/6.4
+)
+(
+    input  wire                  clk,
+    input  wire                  rst,
+
+    /*
+     * SERDES interface
+     */
+    input  wire [HDR_WIDTH-1:0]  serdes_rx_hdr,
+    output wire                  serdes_rx_reset_req,
+
+    /*
+     * Monitor inputs
+     */
+    input  wire                  rx_bad_block,
+    input  wire                  rx_sequence_error,
+    input  wire                  rx_block_lock,
+    input  wire                  rx_high_ber
+);
+
+// bus width assertions
+initial begin
+    if (HDR_WIDTH != 2) begin
+        $error("Error: HDR_WIDTH must be 2");
+        $finish;
+    end
+end
+
+parameter COUNT_WIDTH = $clog2(COUNT_125US);
+
+localparam [1:0]
+    SYNC_DATA = 2'b10,
+    SYNC_CTRL = 2'b01;
+
+reg [COUNT_WIDTH-1:0] time_count_reg = 0, time_count_next;
+reg [3:0] error_count_reg = 0, error_count_next;
+
+reg saw_ctrl_sh_reg = 1'b0, saw_ctrl_sh_next;
+reg [9:0] block_error_count_reg = 0, block_error_count_next;
+
+reg serdes_rx_reset_req_reg = 1'b0, serdes_rx_reset_req_next;
+
+assign serdes_rx_reset_req = serdes_rx_reset_req_reg;
+
+always @* begin
+    error_count_next = error_count_reg;
+
+    saw_ctrl_sh_next = saw_ctrl_sh_reg;
+    block_error_count_next = block_error_count_reg;
+
+    serdes_rx_reset_req_next = 1'b0;
+
+    if (rx_block_lock) begin
+        if (serdes_rx_hdr == SYNC_CTRL) begin
+            saw_ctrl_sh_next = 1'b1;
+        end
+        if ((rx_bad_block || rx_sequence_error) && !(&block_error_count_reg)) begin
+            block_error_count_next = block_error_count_reg + 1;
+        end
+    end
+
+    if (time_count_reg != 0) begin
+        time_count_next = time_count_reg-1;
+    end else begin
+        time_count_next = COUNT_125US;
+
+        if (!saw_ctrl_sh_reg || &block_error_count_reg) begin
+            error_count_next = error_count_reg + 1;
+        end else begin
+            error_count_next = 0;
+        end
+
+        if (&error_count_reg) begin
+            error_count_next = 0;
+            serdes_rx_reset_req_next = 1'b1;
+        end
+
+        saw_ctrl_sh_next = 1'b0;
+        block_error_count_next = 0;
+    end
+end
+
+always @(posedge clk) begin
+    time_count_reg <= time_count_next;
+    error_count_reg <= error_count_next;
+    saw_ctrl_sh_reg <= saw_ctrl_sh_next;
+    block_error_count_reg <= block_error_count_next;
+
+    if (rst) begin
+        time_count_reg <= COUNT_125US;
+        error_count_reg <= 0;
+        saw_ctrl_sh_reg <= 1'b0;
+        block_error_count_reg <= 0;
+    end
+end
+
+always @(posedge clk or posedge rst) begin
+    if (rst) begin
+        serdes_rx_reset_req_reg <= 1'b0;
+    end else begin
+        serdes_rx_reset_req_reg <= serdes_rx_reset_req_next;
+    end
+end
+
+endmodule

tb/eth_mac_phy_10g/Makefile

@@ -35,6 +35,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT)_tx.v
 VERILOG_SOURCES += ../../rtl/eth_phy_10g_rx_if.v
 VERILOG_SOURCES += ../../rtl/eth_phy_10g_rx_ber_mon.v
 VERILOG_SOURCES += ../../rtl/eth_phy_10g_rx_frame_sync.v
+VERILOG_SOURCES += ../../rtl/eth_phy_10g_rx_watchdog.v
 VERILOG_SOURCES += ../../rtl/eth_phy_10g_tx_if.v
 VERILOG_SOURCES += ../../rtl/axis_baser_rx_64.v
 VERILOG_SOURCES += ../../rtl/axis_baser_tx_64.v

tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py

@@ -312,6 +312,7 @@ def test_eth_mac_phy_10g(request, data_width, enable_dic):
         os.path.join(rtl_dir, "eth_phy_10g_rx_if.v"),
         os.path.join(rtl_dir, "eth_phy_10g_rx_ber_mon.v"),
         os.path.join(rtl_dir, "eth_phy_10g_rx_frame_sync.v"),
+        os.path.join(rtl_dir, "eth_phy_10g_rx_watchdog.v"),
         os.path.join(rtl_dir, "eth_phy_10g_tx_if.v"),
         os.path.join(rtl_dir, "axis_baser_rx_64.v"),
         os.path.join(rtl_dir, "axis_baser_tx_64.v"),

tb/eth_mac_phy_10g_fifo/Makefile

@@ -36,6 +36,7 @@ VERILOG_SOURCES += ../../rtl/eth_mac_phy_10g_tx.v
 VERILOG_SOURCES += ../../rtl/eth_phy_10g_rx_if.v
 VERILOG_SOURCES += ../../rtl/eth_phy_10g_rx_ber_mon.v
 VERILOG_SOURCES += ../../rtl/eth_phy_10g_rx_frame_sync.v
+VERILOG_SOURCES += ../../rtl/eth_phy_10g_rx_watchdog.v
 VERILOG_SOURCES += ../../rtl/eth_phy_10g_tx_if.v
 VERILOG_SOURCES += ../../rtl/axis_baser_rx_64.v
 VERILOG_SOURCES += ../../rtl/axis_baser_tx_64.v

tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py

@@ -319,6 +319,7 @@ def test_eth_mac_phy_10g_fifo(request, data_width, enable_dic):
         os.path.join(rtl_dir, "eth_phy_10g_rx_if.v"),
         os.path.join(rtl_dir, "eth_phy_10g_rx_ber_mon.v"),
         os.path.join(rtl_dir, "eth_phy_10g_rx_frame_sync.v"),
+        os.path.join(rtl_dir, "eth_phy_10g_rx_watchdog.v"),
         os.path.join(rtl_dir, "eth_phy_10g_tx_if.v"),
         os.path.join(rtl_dir, "axis_baser_rx_64.v"),
         os.path.join(rtl_dir, "axis_baser_tx_64.v"),

tb/eth_phy_10g/Makefile

@@ -35,6 +35,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT)_rx.v
 VERILOG_SOURCES += ../../rtl/$(DUT)_rx_if.v
 VERILOG_SOURCES += ../../rtl/$(DUT)_rx_ber_mon.v
 VERILOG_SOURCES += ../../rtl/$(DUT)_rx_frame_sync.v
+VERILOG_SOURCES += ../../rtl/$(DUT)_rx_watchdog.v
 VERILOG_SOURCES += ../../rtl/$(DUT)_tx.v
 VERILOG_SOURCES += ../../rtl/$(DUT)_tx_if.v
 VERILOG_SOURCES += ../../rtl/xgmii_baser_dec_64.v

tb/eth_phy_10g/test_eth_phy_10g.py

@@ -226,6 +226,7 @@ def test_eth_phy_10g(request):
         os.path.join(rtl_dir, f"{dut}_rx_if.v"),
         os.path.join(rtl_dir, f"{dut}_rx_ber_mon.v"),
         os.path.join(rtl_dir, f"{dut}_rx_frame_sync.v"),
+        os.path.join(rtl_dir, f"{dut}_rx_watchdog.v"),
         os.path.join(rtl_dir, f"{dut}_tx.v"),
         os.path.join(rtl_dir, f"{dut}_tx_if.v"),
         os.path.join(rtl_dir, "xgmii_baser_dec_64.v"),