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https://github.com/alexforencich/verilog-ethernet.git
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Add clock frequency annotation
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@ -111,6 +111,7 @@ set_property -dict {LOC AL21 IOSTANDARD LVCMOS18} [get_ports qsfp1_modprsl]
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set_property -dict {LOC AP21 IOSTANDARD LVCMOS18} [get_ports qsfp1_intl]
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set_property -dict {LOC AN21 IOSTANDARD LVCMOS18} [get_ports qsfp1_lpmode]
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# 156.25 MHz MGT reference clock
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create_clock -period 6.400 -name qsfp1_mgt_refclk_0 [get_ports qsfp1_mgt_refclk_0_p]
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set_clock_groups -asynchronous -group [get_clocks qsfp1_mgt_refclk_0 -include_generated_clocks]
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@ -142,6 +143,7 @@ set_property -dict {LOC AN24 IOSTANDARD LVCMOS18} [get_ports qsfp2_modprsl]
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set_property -dict {LOC AT21 IOSTANDARD LVCMOS18} [get_ports qsfp2_intl]
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set_property -dict {LOC AT24 IOSTANDARD LVCMOS18} [get_ports qsfp2_lpmode]
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# 156.25 MHz MGT reference clock
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create_clock -period 6.400 -name qsfp2_mgt_refclk_0 [get_ports qsfp2_mgt_refclk_0_p]
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set_clock_groups -asynchronous -group [get_clocks qsfp2_mgt_refclk_0 -include_generated_clocks]
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@ -111,6 +111,7 @@ set_clock_groups -asynchronous -group [get_clocks phy_sgmii_clk -include_generat
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#set_property -dict {LOC AP21 IOSTANDARD LVCMOS18} [get_ports qsfp1_intl]
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#set_property -dict {LOC AN21 IOSTANDARD LVCMOS18} [get_ports qsfp1_lpmode]
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# 156.25 MHz MGT reference clock
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#create_clock -period 6.400 -name qsfp1_mgt_refclk_0 [get_ports qsfp1_mgt_refclk_0_p]
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#set_clock_groups -asynchronous -group [get_clocks qsfp1_mgt_refclk_0 -include_generated_clocks]
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@ -142,6 +143,7 @@ set_clock_groups -asynchronous -group [get_clocks phy_sgmii_clk -include_generat
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#set_property -dict {LOC AT21 IOSTANDARD LVCMOS18} [get_ports qsfp2_intl]
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#set_property -dict {LOC AT24 IOSTANDARD LVCMOS18} [get_ports qsfp2_lpmode]
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# 156.25 MHz MGT reference clock
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#create_clock -period 6.400 -name qsfp2_mgt_refclk_0 [get_ports qsfp2_mgt_refclk_0_p]
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#set_clock_groups -asynchronous -group [get_clocks qsfp2_mgt_refclk_0 -include_generated_clocks]
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