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merged changes in axis

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This commit is contained in:
Alex Forencich 2016-09-12 14:08:45 -07:00
commit 64354e0b60
98 changed files with 6493 additions and 8267 deletions
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2
lib/axis/rtl/axis_async_fifo.v
View File

@ -198,7 +198,7 @@ always @* begin
mem_read_data_valid_next = mem_read_data_valid_reg;
if (output_axis_tready | ~output_axis_tvalid) begin
if (store_output | ~mem_read_data_valid_reg) begin
// output data not valid OR currently being transferred
if (~empty) begin
// not empty, perform read

2
lib/axis/rtl/axis_async_fifo_64.v
View File

@ -201,7 +201,7 @@ always @* begin
mem_read_data_valid_next = mem_read_data_valid_reg;
if (output_axis_tready | ~output_axis_tvalid) begin
if (store_output | ~mem_read_data_valid_reg) begin
// output data not valid OR currently being transferred
if (~empty) begin
// not empty, perform read

2
lib/axis/rtl/axis_async_frame_fifo.v
View File

@ -314,7 +314,7 @@ always @* begin
mem_read_data_valid_next = mem_read_data_valid_reg;
if (output_axis_tready | ~output_axis_tvalid) begin
if (store_output | ~mem_read_data_valid_reg) begin
// output data not valid OR currently being transferred
if (~empty) begin
// not empty, perform read

2
lib/axis/rtl/axis_async_frame_fifo_64.v
View File

@ -317,7 +317,7 @@ always @* begin
mem_read_data_valid_next = mem_read_data_valid_reg;
if (output_axis_tready | ~output_axis_tvalid) begin
if (store_output | ~mem_read_data_valid_reg) begin
// output data not valid OR currently being transferred
if (~empty) begin
// not empty, perform read

2
lib/axis/rtl/axis_fifo.v
View File

@ -127,7 +127,7 @@ always @* begin
mem_read_data_valid_next = mem_read_data_valid_reg;
if (output_axis_tready | ~output_axis_tvalid) begin
if (store_output | ~mem_read_data_valid_reg) begin
// output data not valid OR currently being transferred
if (~empty) begin
// not empty, perform read

2
lib/axis/rtl/axis_fifo_64.v
View File

@ -130,7 +130,7 @@ always @* begin
mem_read_data_valid_next = mem_read_data_valid_reg;
if (output_axis_tready | ~output_axis_tvalid) begin
if (store_output | ~mem_read_data_valid_reg) begin
// output data not valid OR currently being transferred
if (~empty) begin
// not empty, perform read

2
lib/axis/rtl/axis_frame_fifo.v
View File

@ -189,7 +189,7 @@ always @* begin
mem_read_data_valid_next = mem_read_data_valid_reg;
if (output_axis_tready | ~output_axis_tvalid) begin
if (store_output | ~mem_read_data_valid_reg) begin
// output data not valid OR currently being transferred
if (~empty) begin
// not empty, perform read

2
lib/axis/rtl/axis_frame_fifo_64.v
View File

@ -192,7 +192,7 @@ always @* begin
mem_read_data_valid_next = mem_read_data_valid_reg;
if (output_axis_tready | ~output_axis_tvalid) begin
if (store_output | ~mem_read_data_valid_reg) begin
// output data not valid OR currently being transferred
if (~empty) begin
// not empty, perform read

420
lib/axis/tb/axis_ep.py
View File

@ -176,204 +176,258 @@ class AXIStreamFrame(object):
def __iter__(self):
return self.data.__iter__()
def AXIStreamSource(clk, rst,
tdata=None,
tkeep=Signal(bool(True)),
tvalid=Signal(bool(False)),
tready=Signal(bool(True)),
tlast=Signal(bool(False)),
tdest=Signal(intbv(0)),
tuser=Signal(bool(False)),
fifo=None,
pause=0,
name=None):
tready_int = Signal(bool(False))
tvalid_int = Signal(bool(False))
class AXIStreamSource(object):
def __init__(self):
self.has_logic = False
self.queue = []
@always_comb
def pause_logic():
tready_int.next = tready and not pause
tvalid.next = tvalid_int and not pause
def send(self, frame):
self.queue.append(AXIStreamFrame(frame))
@instance
def logic():
frame = AXIStreamFrame()
data = []
keep = []
dest = []
user = []
B = 0
N = len(tdata)
M = len(tkeep)
WL = int((len(tdata)+M-1)/M)
def write(self, data):
self.send(data)
if type(tdata) is list or type(tdata) is tuple:
# multiple tdata signals
B = len(tdata)
N = [len(b) for b in tdata]
M = 1
WL = [1]*B
def count(self):
return len(self.queue)
while True:
yield clk.posedge, rst.posedge
def empty(self):
return self.count() == 0
if rst:
if B > 0:
for s in tdata:
s.next = 0
else:
tdata.next = 0
tkeep.next = 0
tdest.next = 0
tuser.next = False
tvalid_int.next = False
tlast.next = False
else:
if tready_int and tvalid:
if len(data) > 0:
if B > 0:
l = data.pop(0)
for i in range(B):
tdata[i].next = l[i]
else:
tdata.next = data.pop(0)
tkeep.next = keep.pop(0)
tdest.next = dest.pop(0)
tuser.next = user.pop(0)
tvalid_int.next = True
tlast.next = len(data) == 0
else:
tvalid_int.next = False
tlast.next = False
if (tlast and tready_int and tvalid) or not tvalid_int:
if not fifo.empty():
frame = fifo.get()
frame = AXIStreamFrame(frame)
frame.B = B
frame.N = N
frame.M = M
frame.WL = WL
data, keep, dest, user = frame.build()
if name is not None:
print("[%s] Sending frame %s" % (name, repr(frame)))
if B > 0:
l = data.pop(0)
for i in range(B):
tdata[i].next = l[i]
else:
tdata.next = data.pop(0)
tkeep.next = keep.pop(0)
tdest.next = dest.pop(0)
tuser.next = user.pop(0)
tvalid_int.next = True
tlast.next = len(data) == 0
def create_logic(self,
clk,
rst,
tdata=None,
tkeep=Signal(bool(True)),
tvalid=Signal(bool(False)),
tready=Signal(bool(True)),
tlast=Signal(bool(False)),
tdest=Signal(intbv(0)),
tuser=Signal(bool(False)),
pause=0,
name=None
):
return logic, pause_logic
assert not self.has_logic
self.has_logic = True
def AXIStreamSink(clk, rst,
tdata=None,
tkeep=Signal(bool(True)),
tvalid=Signal(bool(True)),
tready=Signal(bool(True)),
tlast=Signal(bool(True)),
tdest=Signal(intbv(0)),
tuser=Signal(bool(False)),
fifo=None,
pause=0,
name=None):
tready_int = Signal(bool(False))
tvalid_int = Signal(bool(False))
tready_int = Signal(bool(False))
tvalid_int = Signal(bool(False))
@always_comb
def pause_logic():
tready_int.next = tready and not pause
tvalid.next = tvalid_int and not pause
@always_comb
def pause_logic():
tready.next = tready_int and not pause
tvalid_int.next = tvalid and not pause
@instance
def logic():
frame = AXIStreamFrame()
data = []
keep = []
dest = []
user = []
B = 0
N = len(tdata)
M = len(tkeep)
WL = int((len(tdata)+M-1)/M)
@instance
def logic():
frame = AXIStreamFrame()
data = []
keep = []
dest = []
user = []
B = 0
N = len(tdata)
M = len(tkeep)
WL = int((len(tdata)+M-1)/M)
first = True
if type(tdata) is list or type(tdata) is tuple:
# multiple tdata signals
B = len(tdata)
N = [len(b) for b in tdata]
M = 1
WL = [1]*B
if type(tdata) is list or type(tdata) is tuple:
# multiple tdata signals
B = len(tdata)
N = [len(b) for b in tdata]
M = 1
WL = [1]*B
while True:
yield clk.posedge, rst.posedge
if rst:
tready_int.next = False
frame = AXIStreamFrame()
data = []
keep = []
dest = []
user = []
first = True
else:
tready_int.next = True
if tvalid_int:
if not skip_asserts:
# zero tkeep not allowed
assert int(tkeep) != 0
# tkeep must be contiguous
# i.e. 0b00011110 allowed, but 0b00011010 not allowed
b = int(tkeep)
while b & 1 == 0:
b = b >> 1
while b & 1 == 1:
b = b >> 1
assert b == 0
# tkeep must not have gaps across cycles
if not first:
# not first cycle; lowest bit must be set
assert int(tkeep) & 1
if not tlast:
# not last cycle; highest bit must be set
assert int(tkeep) & (1 << len(tkeep)-1)
while True:
yield clk.posedge, rst.posedge
if rst:
if B > 0:
l = []
for i in range(B):
l.append(int(tdata[i]))
data.append(l)
for s in tdata:
s.next = 0
else:
data.append(int(tdata))
keep.append(int(tkeep))
dest.append(int(tdest))
user.append(int(tuser))
first = False
if tlast:
frame.B = B
frame.N = N
frame.M = M
frame.WL = WL
frame.parse(data, keep, dest, user)
if fifo is not None:
fifo.put(frame)
if name is not None:
print("[%s] Got frame %s" % (name, repr(frame)))
frame = AXIStreamFrame()
data = []
keep = []
dest = []
user = []
first = True
tdata.next = 0
tkeep.next = 0
tdest.next = 0
tuser.next = False
tvalid_int.next = False
tlast.next = False
else:
if tready_int and tvalid:
if len(data) > 0:
if B > 0:
l = data.pop(0)
for i in range(B):
tdata[i].next = l[i]
else:
tdata.next = data.pop(0)
tkeep.next = keep.pop(0)
tdest.next = dest.pop(0)
tuser.next = user.pop(0)
tvalid_int.next = True
tlast.next = len(data) == 0
else:
tvalid_int.next = False
tlast.next = False
if (tlast and tready_int and tvalid) or not tvalid_int:
if len(self.queue) > 0:
frame = self.queue.pop(0)
frame.B = B
frame.N = N
frame.M = M
frame.WL = WL
data, keep, dest, user = frame.build()
if name is not None:
print("[%s] Sending frame %s" % (name, repr(frame)))
if B > 0:
l = data.pop(0)
for i in range(B):
tdata[i].next = l[i]
else:
tdata.next = data.pop(0)
tkeep.next = keep.pop(0)
tdest.next = dest.pop(0)
tuser.next = user.pop(0)
tvalid_int.next = True
tlast.next = len(data) == 0
return logic, pause_logic
return logic, pause_logic
class AXIStreamSink(object):
def __init__(self):
self.has_logic = False
self.queue = []
self.read_queue = []
def recv(self):
if len(self.queue) > 0:
return self.queue.pop(0)
return None
def read(self, count=-1):
while len(self.queue) > 0:
self.read_queue.extend(self.queue.pop(0).data)
if count < 0:
count = len(self.read_queue)
data = self.read_queue[:count]
del self.read_queue[:count]
return data
def count(self):
return len(self.queue)
def empty(self):
return self.count() == 0
def create_logic(self,
clk,
rst,
tdata=None,
tkeep=Signal(bool(True)),
tvalid=Signal(bool(False)),
tready=Signal(bool(True)),
tlast=Signal(bool(True)),
tdest=Signal(intbv(0)),
tuser=Signal(bool(False)),
pause=0,
name=None
):
assert not self.has_logic
self.has_logic = True
tready_int = Signal(bool(False))
tvalid_int = Signal(bool(False))
@always_comb
def pause_logic():
tready.next = tready_int and not pause
tvalid_int.next = tvalid and not pause
@instance
def logic():
frame = AXIStreamFrame()
data = []
keep = []
dest = []
user = []
B = 0
N = len(tdata)
M = len(tkeep)
WL = int((len(tdata)+M-1)/M)
first = True
if type(tdata) is list or type(tdata) is tuple:
# multiple tdata signals
B = len(tdata)
N = [len(b) for b in tdata]
M = 1
WL = [1]*B
while True:
yield clk.posedge, rst.posedge
if rst:
tready_int.next = False
frame = AXIStreamFrame()
data = []
keep = []
dest = []
user = []
first = True
else:
tready_int.next = True
if tvalid_int:
if not skip_asserts:
# zero tkeep not allowed
assert int(tkeep) != 0
# tkeep must be contiguous
# i.e. 0b00011110 allowed, but 0b00011010 not allowed
b = int(tkeep)
while b & 1 == 0:
b = b >> 1
while b & 1 == 1:
b = b >> 1
assert b == 0
# tkeep must not have gaps across cycles
if not first:
# not first cycle; lowest bit must be set
assert int(tkeep) & 1
if not tlast:
# not last cycle; highest bit must be set
assert int(tkeep) & (1 << len(tkeep)-1)
if B > 0:
l = []
for i in range(B):
l.append(int(tdata[i]))
data.append(l)
else:
data.append(int(tdata))
keep.append(int(tkeep))
dest.append(int(tdest))
user.append(int(tuser))
first = False
if tlast:
frame.B = B
frame.N = N
frame.M = M
frame.WL = WL
frame.parse(data, keep, dest, user)
self.queue.append(frame)
if name is not None:
print("[%s] Got frame %s" % (name, repr(frame)))
frame = AXIStreamFrame()
data = []
keep = []
dest = []
user = []
first = True
return logic, pause_logic

201
lib/axis/tb/ll_ep.py
View File

@ -24,100 +24,139 @@ THE SOFTWARE.
from myhdl import *
def LocalLinkSource(clk, rst,
data_out,
sof_out_n,
eof_out_n,
src_rdy_out_n,
dst_rdy_in_n,
fifo,
pause=0,
name=None):
class LocalLinkSource(object):
def __init__(self):
self.has_logic = False
self.queue = []
src_rdy_out_n_int = Signal(bool(True))
dst_rdy_in_n_int = Signal(bool(True))
def send(self, frame):
self.queue.append(bytearray(frame))
@always_comb
def pause_logic():
dst_rdy_in_n_int.next = dst_rdy_in_n or pause
src_rdy_out_n.next = src_rdy_out_n_int or pause
def count(self):
return len(self.queue)
@instance
def logic():
frame = []
def empty(self):
return self.count() == 0
while True:
yield clk.posedge, rst.posedge
def create_logic(self,
clk,
rst,
data_out,
sof_out_n,
eof_out_n,
src_rdy_out_n,
dst_rdy_in_n,
pause=0,
name=None):
if rst:
data_out.next = 0
src_rdy_out_n_int.next = True
sof_out_n.next = True
eof_out_n.next = True
else:
if not dst_rdy_in_n_int and not src_rdy_out_n:
if len(frame) > 0:
data_out.next = frame.pop(0)
src_rdy_out_n_int.next = False
sof_out_n.next = True
eof_out_n.next = len(frame) != 0
else:
src_rdy_out_n_int.next = True
eof_out_n.next = True
if (not eof_out_n and not dst_rdy_in_n_int and not src_rdy_out_n) or src_rdy_out_n_int:
if not fifo.empty():
frame = fifo.get()
if name is not None:
print("[%s] Sending frame %s" % (name, repr(frame)))
data_out.next = frame.pop(0)
src_rdy_out_n_int.next = False
sof_out_n.next = False
eof_out_n.next = len(frame) != 0
assert not self.has_logic
return logic, pause_logic
self.has_logic = True
src_rdy_out_n_int = Signal(bool(True))
dst_rdy_in_n_int = Signal(bool(True))
@always_comb
def pause_logic():
dst_rdy_in_n_int.next = dst_rdy_in_n or pause
src_rdy_out_n.next = src_rdy_out_n_int or pause
@instance
def logic():
frame = []
while True:
yield clk.posedge, rst.posedge
if rst:
data_out.next = 0
src_rdy_out_n_int.next = True
sof_out_n.next = True
eof_out_n.next = True
else:
if not dst_rdy_in_n_int and not src_rdy_out_n:
if len(frame) > 0:
data_out.next = frame.pop(0)
src_rdy_out_n_int.next = False
sof_out_n.next = True
eof_out_n.next = len(frame) != 0
else:
src_rdy_out_n_int.next = True
eof_out_n.next = True
if (not eof_out_n and not dst_rdy_in_n_int and not src_rdy_out_n) or src_rdy_out_n_int:
if len(self.queue) > 0:
frame = self.queue.pop(0)
if name is not None:
print("[%s] Sending frame %s" % (name, repr(frame)))
data_out.next = frame.pop(0)
src_rdy_out_n_int.next = False
sof_out_n.next = False
eof_out_n.next = len(frame) != 0
return logic, pause_logic
def LocalLinkSink(clk, rst,
data_in,
sof_in_n,
eof_in_n,
src_rdy_in_n,
dst_rdy_out_n,
fifo=None,
pause=0,
name=None):
class LocalLinkSink(object):
def __init__(self):
self.has_logic = False
self.queue = []
src_rdy_in_n_int = Signal(bool(True))
dst_rdy_out_n_int = Signal(bool(True))
def recv(self):
if len(self.queue) > 0:
return self.queue.pop(0)
return None
@always_comb
def pause_logic():
dst_rdy_out_n.next = dst_rdy_out_n_int or pause
src_rdy_in_n_int.next = src_rdy_in_n or pause
def count(self):
return len(self.queue)
@instance
def logic():
frame = []
def empty(self):
return self.count() == 0
while True:
yield clk.posedge, rst.posedge
def create_logic(self,
clk,
rst,
data_in,
sof_in_n,
eof_in_n,
src_rdy_in_n,
dst_rdy_out_n,
pause=0,
name=None):
if rst:
dst_rdy_out_n_int.next = True
frame = []
else:
dst_rdy_out_n_int.next = False
assert not self.has_logic
if not src_rdy_in_n_int:
if not sof_in_n:
frame = []
frame.append(int(data_in))
if not eof_in_n:
if fifo is not None:
fifo.put(frame)
if name is not None:
print("[%s] Got frame %s" % (name, repr(frame)))
frame = []
self.has_logic = True
return logic, pause_logic
src_rdy_in_n_int = Signal(bool(True))
dst_rdy_out_n_int = Signal(bool(True))
@always_comb
def pause_logic():
dst_rdy_out_n.next = dst_rdy_out_n_int or pause
src_rdy_in_n_int.next = src_rdy_in_n or pause
@instance
def logic():
frame = []
while True:
yield clk.posedge, rst.posedge
if rst:
dst_rdy_out_n_int.next = True
frame = []
else:
dst_rdy_out_n_int.next = False
if not src_rdy_in_n_int:
if not sof_in_n:
frame = []
frame.append(int(data_in))
if not eof_in_n:
self.queue.append(frame)
if name is not None:
print("[%s] Got frame %s" % (name, repr(frame)))
frame = []
return logic, pause_logic

65
lib/axis/tb/test_arbiter.py
View File

@ -27,68 +27,55 @@ from myhdl import *
import os
module = 'arbiter'
testbench = 'test_%s' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/priority_encoder.v")
srcs.append("test_%s.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_arbiter(clk,
rst,
current_test,
request,
acknowledge,
grant,
grant_valid,
grant_encoded):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
request=request,
acknowledge=acknowledge,
grant=grant,
grant_valid=grant_valid,
grant_encoded=grant_encoded)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
PORTS = 32
TYPE = "PRIORITY"
BLOCK = "REQUEST"
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
request = Signal(intbv(0)[32:])
acknowledge = Signal(intbv(0)[32:])
request = Signal(intbv(0)[PORTS:])
acknowledge = Signal(intbv(0)[PORTS:])
# Outputs
grant = Signal(intbv(0)[32:])
grant = Signal(intbv(0)[PORTS:])
grant_valid = Signal(bool(0))
grant_encoded = Signal(intbv(0)[5:])
# DUT
dut = dut_arbiter(clk,
rst,
current_test,
if os.system(build_cmd):
raise Exception("Error running build command")
request,
acknowledge,
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
grant,
grant_valid,
grant_encoded)
request=request,
acknowledge=acknowledge,
grant=grant,
grant_valid=grant_valid,
grant_encoded=grant_encoded
)
@always(delay(4))
def clkgen():
@ -133,7 +120,7 @@ def bench():
print("test 2: two bits")
current_test.next = 2
for i in range(32):
for j in range(32):
l = [i, j]

27
lib/axis/tb/test_arbiter.v
View File

@ -24,11 +24,14 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1 ns / 1 ps
`timescale 1ns / 1ps
/*
* Testbench for arbiter
*/
module test_arbiter;
// parameters
// Parameters
localparam PORTS = 32;
localparam TYPE = "PRIORITY";
localparam BLOCK = "REQUEST";
@ -48,14 +51,18 @@ wire [$clog2(PORTS)-1:0] grant_encoded;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
request,
acknowledge);
$to_myhdl(grant,
grant_valid,
grant_encoded);
$from_myhdl(
clk,
rst,
current_test,
request,
acknowledge
);
$to_myhdl(
grant,
grant_valid,
grant_encoded
);
// dump file
$dumpfile("test_arbiter.lxt");

65
lib/axis/tb/test_arbiter_rr.py
View File

@ -27,68 +27,55 @@ from myhdl import *
import os
module = 'arbiter'
testbench = 'test_%s' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/priority_encoder.v")
srcs.append("test_%s_rr.v" % module)
srcs.append("%s_rr.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_arbiter_rr(clk,
rst,
current_test,
request,
acknowledge,
grant,
grant_valid,
grant_encoded):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
request=request,
acknowledge=acknowledge,
grant=grant,
grant_valid=grant_valid,
grant_encoded=grant_encoded)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
PORTS = 32
TYPE = "ROUND_ROBIN"
BLOCK = "REQUEST"
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
request = Signal(intbv(0)[32:])
acknowledge = Signal(intbv(0)[32:])
request = Signal(intbv(0)[PORTS:])
acknowledge = Signal(intbv(0)[PORTS:])
# Outputs
grant = Signal(intbv(0)[32:])
grant = Signal(intbv(0)[PORTS:])
grant_valid = Signal(bool(0))
grant_encoded = Signal(intbv(0)[5:])
# DUT
dut = dut_arbiter_rr(clk,
rst,
current_test,
if os.system(build_cmd):
raise Exception("Error running build command")
request,
acknowledge,
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
grant,
grant_valid,
grant_encoded)
request=request,
acknowledge=acknowledge,
grant=grant,
grant_valid=grant_valid,
grant_encoded=grant_encoded
)
@always(delay(4))
def clkgen():
@ -173,7 +160,7 @@ def bench():
print("test 3: two bits")
current_test.next = 3
for i in range(32):
for j in range(32):
l = [i, j]

27
lib/axis/tb/test_arbiter_rr.v
View File

@ -24,11 +24,14 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1 ns / 1 ps
`timescale 1ns / 1ps
/*
* Testbench for arbiter
*/
module test_arbiter_rr;
// parameters
// Parameters
localparam PORTS = 32;
localparam TYPE = "ROUND_ROBIN";
localparam BLOCK = "REQUEST";
@ -48,14 +51,18 @@ wire [$clog2(PORTS)-1:0] grant_encoded;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
request,
acknowledge);
$to_myhdl(grant,
grant_valid,
grant_encoded);
$from_myhdl(
clk,
rst,
current_test,
request,
acknowledge
);
$to_myhdl(
grant,
grant_valid,
grant_encoded
);
// dump file
$dumpfile("test_arbiter_rr.lxt");

189
lib/axis/tb/test_axis_adapter_64_8.py
View File

@ -26,72 +26,35 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_adapter'
testbench = 'test_%s_64_8' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s_64_8.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_axis_adapter_64_8(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
INPUT_DATA_WIDTH = 64
INPUT_KEEP_WIDTH = (INPUT_DATA_WIDTH/8)
OUTPUT_DATA_WIDTH = 8
OUTPUT_KEEP_WIDTH = (OUTPUT_DATA_WIDTH/8)
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[64:])
input_axis_tkeep = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[INPUT_DATA_WIDTH:])
input_axis_tkeep = Signal(intbv(0)[INPUT_KEEP_WIDTH:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
@ -99,60 +62,70 @@ def bench():
# Outputs
input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[8:])
output_axis_tkeep = Signal(intbv(0)[1:])
output_axis_tdata = Signal(intbv(0)[OUTPUT_DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(0)[OUTPUT_KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
source = axis_ep.AXIStreamSource()
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
source_logic = source.create_logic(
clk,
rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
pause=source_pause,
name='source'
)
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink'
)
# DUT
dut = dut_axis_adapter_64_8(clk,
rst,
current_test,
if os.system(build_cmd):
raise Exception("Error running build command")
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser)
input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser
)
@always(delay(4))
def clkgen():
@ -202,7 +175,7 @@ def bench():
bytearray(range(payload_len)))
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield clk.posedge
@ -212,13 +185,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
assert sink_queue.empty()
assert sink.empty()
yield delay(100)
@ -236,8 +207,8 @@ def bench():
bytearray(range(payload_len)))
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
yield clk.posedge
@ -247,19 +218,15 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
assert sink_queue.empty()
assert sink.empty()
yield delay(100)
@ -279,8 +246,8 @@ def bench():
test_frame1.user = 1
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
yield clk.posedge
@ -290,26 +257,22 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
assert rx_frame.user[-1]
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
assert sink_queue.empty()
assert sink.empty()
yield delay(100)
raise StopSimulation
return dut, source, sink, clkgen, check
return dut, source_logic, sink_logic, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))

41
lib/axis/tb/test_axis_adapter_64_8.v
View File

@ -24,11 +24,14 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1 ns / 1 ps
`timescale 1ns / 1ps
/*
* Testbench for axis_adapter
*/
module test_axis_adapter_64_8;
// parameters
// Parameters
localparam INPUT_DATA_WIDTH = 64;
localparam INPUT_KEEP_WIDTH = (INPUT_DATA_WIDTH/8);
localparam OUTPUT_DATA_WIDTH = 8;
@ -56,21 +59,25 @@ wire output_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
$from_myhdl(
clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready
);
$to_myhdl(
input_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser
);
// dump file
$dumpfile("test_axis_adapter_64_8.lxt");

189
lib/axis/tb/test_axis_adapter_8_64.py
View File

@ -26,72 +26,35 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_adapter'
testbench = 'test_%s_8_64' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s_8_64.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_axis_adapter_8_64(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
INPUT_DATA_WIDTH = 8
INPUT_KEEP_WIDTH = (INPUT_DATA_WIDTH/8)
OUTPUT_DATA_WIDTH = 64
OUTPUT_KEEP_WIDTH = (OUTPUT_DATA_WIDTH/8)
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[8:])
input_axis_tkeep = Signal(intbv(0)[1:])
input_axis_tdata = Signal(intbv(0)[INPUT_DATA_WIDTH:])
input_axis_tkeep = Signal(intbv(0)[INPUT_KEEP_WIDTH:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
@ -99,60 +62,70 @@ def bench():
# Outputs
input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[64:])
output_axis_tkeep = Signal(intbv(0)[8:])
output_axis_tdata = Signal(intbv(0)[OUTPUT_DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(0)[OUTPUT_KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
source = axis_ep.AXIStreamSource()
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
source_logic = source.create_logic(
clk,
rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
pause=source_pause,
name='source'
)
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink'
)
# DUT
dut = dut_axis_adapter_8_64(clk,
rst,
current_test,
if os.system(build_cmd):
raise Exception("Error running build command")
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser)
input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser
)
@always(delay(4))
def clkgen():
@ -202,7 +175,7 @@ def bench():
bytearray(range(payload_len)))
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield clk.posedge
@ -212,13 +185,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
assert sink_queue.empty()
assert sink.empty()
yield delay(100)
@ -236,8 +207,8 @@ def bench():
bytearray(range(payload_len)))
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
yield clk.posedge
@ -247,19 +218,15 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
assert sink_queue.empty()
assert sink.empty()
yield delay(100)
@ -279,8 +246,8 @@ def bench():
test_frame1.user = 1
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
yield clk.posedge
@ -290,26 +257,22 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
assert rx_frame.user[-1]
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
assert sink_queue.empty()
assert sink.empty()
yield delay(100)
raise StopSimulation
return dut, source, sink, clkgen, check
return dut, source_logic, sink_logic, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))

41
lib/axis/tb/test_axis_adapter_8_64.v
View File

@ -24,11 +24,14 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1 ns / 1 ps
`timescale 1ns / 1ps
/*
* Testbench for axis_adapter
*/
module test_axis_adapter_8_64;
// parameters
// Parameters
localparam INPUT_DATA_WIDTH = 8;
localparam INPUT_KEEP_WIDTH = (INPUT_DATA_WIDTH/8);
localparam OUTPUT_DATA_WIDTH = 64;
@ -56,21 +59,25 @@ wire output_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
$from_myhdl(
clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready
);
$to_myhdl(
input_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser
);
// dump file
$dumpfile("test_axis_adapter_8_64.lxt");

379
lib/axis/tb/test_axis_arb_mux_4.py
View File

@ -26,14 +26,10 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_arb_mux_4'
testbench = 'test_%s' % module
srcs = []
@ -41,97 +37,35 @@ srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/axis_mux_4.v")
srcs.append("../rtl/arbiter.v")
srcs.append("../rtl/priority_encoder.v")
srcs.append("test_%s.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_axis_arb_mux_4(clk,
rst,
current_test,
input_0_axis_tdata,
input_0_axis_tvalid,
input_0_axis_tready,
input_0_axis_tlast,
input_0_axis_tuser,
input_1_axis_tdata,
input_1_axis_tvalid,
input_1_axis_tready,
input_1_axis_tlast,
input_1_axis_tuser,
input_2_axis_tdata,
input_2_axis_tvalid,
input_2_axis_tready,
input_2_axis_tlast,
input_2_axis_tuser,
input_3_axis_tdata,
input_3_axis_tvalid,
input_3_axis_tready,
input_3_axis_tlast,
input_3_axis_tuser,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_0_axis_tdata=input_0_axis_tdata,
input_0_axis_tvalid=input_0_axis_tvalid,
input_0_axis_tready=input_0_axis_tready,
input_0_axis_tlast=input_0_axis_tlast,
input_0_axis_tuser=input_0_axis_tuser,
input_1_axis_tdata=input_1_axis_tdata,
input_1_axis_tvalid=input_1_axis_tvalid,
input_1_axis_tready=input_1_axis_tready,
input_1_axis_tlast=input_1_axis_tlast,
input_1_axis_tuser=input_1_axis_tuser,
input_2_axis_tdata=input_2_axis_tdata,
input_2_axis_tvalid=input_2_axis_tvalid,
input_2_axis_tready=input_2_axis_tready,
input_2_axis_tlast=input_2_axis_tlast,
input_2_axis_tuser=input_2_axis_tuser,
input_3_axis_tdata=input_3_axis_tdata,
input_3_axis_tvalid=input_3_axis_tvalid,
input_3_axis_tready=input_3_axis_tready,
input_3_axis_tlast=input_3_axis_tlast,
input_3_axis_tuser=input_3_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
DATA_WIDTH = 8
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_0_axis_tdata = Signal(intbv(0)[8:])
input_0_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_0_axis_tvalid = Signal(bool(0))
input_0_axis_tlast = Signal(bool(0))
input_0_axis_tuser = Signal(bool(0))
input_1_axis_tdata = Signal(intbv(0)[8:])
input_1_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_1_axis_tvalid = Signal(bool(0))
input_1_axis_tlast = Signal(bool(0))
input_1_axis_tuser = Signal(bool(0))
input_2_axis_tdata = Signal(intbv(0)[8:])
input_2_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_2_axis_tvalid = Signal(bool(0))
input_2_axis_tlast = Signal(bool(0))
input_2_axis_tuser = Signal(bool(0))
input_3_axis_tdata = Signal(intbv(0)[8:])
input_3_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_3_axis_tvalid = Signal(bool(0))
input_3_axis_tlast = Signal(bool(0))
input_3_axis_tuser = Signal(bool(0))
@ -144,106 +78,125 @@ def bench():
input_2_axis_tready = Signal(bool(0))
input_3_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[8:])
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
# sources and sinks
source_0_queue = Queue()
source_0_pause = Signal(bool(0))
source_1_queue = Queue()
source_1_pause = Signal(bool(0))
source_2_queue = Queue()
source_2_pause = Signal(bool(0))
source_3_queue = Queue()
source_3_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source_0 = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_0_axis_tdata,
tvalid=input_0_axis_tvalid,
tready=input_0_axis_tready,
tlast=input_0_axis_tlast,
tuser=input_0_axis_tuser,
fifo=source_0_queue,
pause=source_0_pause,
name='source0')
source_1 = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_1_axis_tdata,
tvalid=input_1_axis_tvalid,
tready=input_1_axis_tready,
tlast=input_1_axis_tlast,
tuser=input_1_axis_tuser,
fifo=source_1_queue,
pause=source_1_pause,
name='source1')
source_2 = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_2_axis_tdata,
tvalid=input_2_axis_tvalid,
tready=input_2_axis_tready,
tlast=input_2_axis_tlast,
tuser=input_2_axis_tuser,
fifo=source_2_queue,
pause=source_2_pause,
name='source2')
source_3 = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_3_axis_tdata,
tvalid=input_3_axis_tvalid,
tready=input_3_axis_tready,
tlast=input_3_axis_tlast,
tuser=input_3_axis_tuser,
fifo=source_3_queue,
pause=source_3_pause,
name='source3')
source_0 = axis_ep.AXIStreamSource()
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
source_0_logic = source_0.create_logic(
clk,
rst,
tdata=input_0_axis_tdata,
tvalid=input_0_axis_tvalid,
tready=input_0_axis_tready,
tlast=input_0_axis_tlast,
tuser=input_0_axis_tuser,
pause=source_0_pause,
name='source_0'
)
source_1 = axis_ep.AXIStreamSource()
source_1_logic = source_1.create_logic(
clk,
rst,
tdata=input_1_axis_tdata,
tvalid=input_1_axis_tvalid,
tready=input_1_axis_tready,
tlast=input_1_axis_tlast,
tuser=input_1_axis_tuser,
pause=source_1_pause,
name='source_1'
)
source_2 = axis_ep.AXIStreamSource()
source_2_logic = source_2.create_logic(
clk,
rst,
tdata=input_2_axis_tdata,
tvalid=input_2_axis_tvalid,
tready=input_2_axis_tready,
tlast=input_2_axis_tlast,
tuser=input_2_axis_tuser,
pause=source_2_pause,
name='source_2'
)
source_3 = axis_ep.AXIStreamSource()
source_3_logic = source_3.create_logic(
clk,
rst,
tdata=input_3_axis_tdata,
tvalid=input_3_axis_tvalid,
tready=input_3_axis_tready,
tlast=input_3_axis_tlast,
tuser=input_3_axis_tuser,
pause=source_3_pause,
name='source_3'
)
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink'
)
# DUT
dut = dut_axis_arb_mux_4(clk,
rst,
current_test,
if os.system(build_cmd):
raise Exception("Error running build command")
input_0_axis_tdata,
input_0_axis_tvalid,
input_0_axis_tready,
input_0_axis_tlast,
input_0_axis_tuser,
input_1_axis_tdata,
input_1_axis_tvalid,
input_1_axis_tready,
input_1_axis_tlast,
input_1_axis_tuser,
input_2_axis_tdata,
input_2_axis_tvalid,
input_2_axis_tready,
input_2_axis_tlast,
input_2_axis_tuser,
input_3_axis_tdata,
input_3_axis_tvalid,
input_3_axis_tready,
input_3_axis_tlast,
input_3_axis_tuser,
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser)
input_0_axis_tdata=input_0_axis_tdata,
input_0_axis_tvalid=input_0_axis_tvalid,
input_0_axis_tready=input_0_axis_tready,
input_0_axis_tlast=input_0_axis_tlast,
input_0_axis_tuser=input_0_axis_tuser,
input_1_axis_tdata=input_1_axis_tdata,
input_1_axis_tvalid=input_1_axis_tvalid,
input_1_axis_tready=input_1_axis_tready,
input_1_axis_tlast=input_1_axis_tlast,
input_1_axis_tuser=input_1_axis_tuser,
input_2_axis_tdata=input_2_axis_tdata,
input_2_axis_tvalid=input_2_axis_tvalid,
input_2_axis_tready=input_2_axis_tready,
input_2_axis_tlast=input_2_axis_tlast,
input_2_axis_tuser=input_2_axis_tuser,
input_3_axis_tdata=input_3_axis_tdata,
input_3_axis_tvalid=input_3_axis_tvalid,
input_3_axis_tready=input_3_axis_tready,
input_3_axis_tlast=input_3_axis_tlast,
input_3_axis_tuser=input_3_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser
)
@always(delay(4))
def clkgen():
@ -270,7 +223,7 @@ def bench():
b'\x5A\x00\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_0_queue.put(test_frame)
source_0.send(test_frame)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
@ -278,9 +231,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -294,7 +245,7 @@ def bench():
b'\x5A\x01\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_1_queue.put(test_frame)
source_1.send(test_frame)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
@ -302,9 +253,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -322,8 +271,8 @@ def bench():
b'\x5A\x00\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_0_queue.put(test_frame1)
source_0_queue.put(test_frame2)
source_0.send(test_frame1)
source_0.send(test_frame2)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
@ -331,15 +280,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -357,8 +302,8 @@ def bench():
b'\x5A\x02\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_1_queue.put(test_frame1)
source_2_queue.put(test_frame2)
source_1.send(test_frame1)
source_2.send(test_frame2)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
@ -366,15 +311,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -392,8 +333,8 @@ def bench():
b'\x5A\x02\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_1_queue.put(test_frame1)
source_2_queue.put(test_frame2)
source_1.send(test_frame1)
source_2.send(test_frame2)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
@ -412,15 +353,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -438,8 +375,8 @@ def bench():
b'\x5A\x02\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_1_queue.put(test_frame1)
source_2_queue.put(test_frame2)
source_1.send(test_frame1)
source_2.send(test_frame2)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
@ -452,23 +389,19 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 4: back-to-back packets, different ports, arbitration test")
current_test.next = 4
print("test 7: back-to-back packets, different ports, arbitration test")
current_test.next = 7
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x01\x52\x53\x54\x55' +
@ -478,56 +411,44 @@ def bench():
b'\x5A\x02\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_1_queue.put(test_frame1)
source_2_queue.put(test_frame2)
source_2_queue.put(test_frame2)
source_2_queue.put(test_frame2)
source_2_queue.put(test_frame2)
source_2_queue.put(test_frame2)
source_1.send(test_frame1)
source_2.send(test_frame2)
source_2.send(test_frame2)
source_2.send(test_frame2)
source_2.send(test_frame2)
source_2.send(test_frame2)
yield clk.posedge
yield delay(800)
yield clk.posedge
source_1_queue.put(test_frame1)
source_1.send(test_frame1)
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -535,7 +456,7 @@ def bench():
raise StopSimulation
return dut, source_0, source_1, source_2, source_3, sink, clkgen, check
return dut, source_0_logic, source_1_logic, source_2_logic, source_3_logic, sink_logic, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))

80
lib/axis/tb/test_axis_arb_mux_4.v
View File

@ -24,28 +24,34 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1 ns / 1 ps
`timescale 1ns / 1ps
/*
* Testbench for axis_arb_mux_4
*/
module test_axis_arb_mux_4;
// Parameters
localparam DATA_WIDTH = 8;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] input_0_axis_tdata = 0;
reg [DATA_WIDTH-1:0] input_0_axis_tdata = 0;
reg input_0_axis_tvalid = 0;
reg input_0_axis_tlast = 0;
reg input_0_axis_tuser = 0;
reg [7:0] input_1_axis_tdata = 0;
reg [DATA_WIDTH-1:0] input_1_axis_tdata = 0;
reg input_1_axis_tvalid = 0;
reg input_1_axis_tlast = 0;
reg input_1_axis_tuser = 0;
reg [7:0] input_2_axis_tdata = 0;
reg [DATA_WIDTH-1:0] input_2_axis_tdata = 0;
reg input_2_axis_tvalid = 0;
reg input_2_axis_tlast = 0;
reg input_2_axis_tuser = 0;
reg [7:0] input_3_axis_tdata = 0;
reg [DATA_WIDTH-1:0] input_3_axis_tdata = 0;
reg input_3_axis_tvalid = 0;
reg input_3_axis_tlast = 0;
reg input_3_axis_tuser = 0;
@ -58,41 +64,45 @@ wire input_1_axis_tready;
wire input_2_axis_tready;
wire input_3_axis_tready;
wire [7:0] output_axis_tdata;
wire [DATA_WIDTH-1:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_0_axis_tdata,
input_0_axis_tvalid,
input_0_axis_tlast,
input_0_axis_tuser,
input_1_axis_tdata,
input_1_axis_tvalid,
input_1_axis_tlast,
input_1_axis_tuser,
input_2_axis_tdata,
input_2_axis_tvalid,
input_2_axis_tlast,
input_2_axis_tuser,
input_3_axis_tdata,
input_3_axis_tvalid,
input_3_axis_tlast,
input_3_axis_tuser,
output_axis_tready);
$to_myhdl(input_0_axis_tready,
input_1_axis_tready,
input_2_axis_tready,
input_3_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
$from_myhdl(
clk,
rst,
current_test,
input_0_axis_tdata,
input_0_axis_tvalid,
input_0_axis_tlast,
input_0_axis_tuser,
input_1_axis_tdata,
input_1_axis_tvalid,
input_1_axis_tlast,
input_1_axis_tuser,
input_2_axis_tdata,
input_2_axis_tvalid,
input_2_axis_tlast,
input_2_axis_tuser,
input_3_axis_tdata,
input_3_axis_tvalid,
input_3_axis_tlast,
input_3_axis_tuser,
output_axis_tready
);
$to_myhdl(
input_0_axis_tready,
input_1_axis_tready,
input_2_axis_tready,
input_3_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser
);
// dump file
$dumpfile("test_axis_arb_mux_4.lxt");
@ -100,7 +110,7 @@ initial begin
end
axis_arb_mux_4 #(
.DATA_WIDTH(8)
.DATA_WIDTH(DATA_WIDTH)
)
UUT (
.clk(clk),

420
lib/axis/tb/test_axis_arb_mux_64_4.py
View File

@ -26,14 +26,10 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_arb_mux_64_4'
testbench = 'test_%s' % module
srcs = []
@ -41,111 +37,40 @@ srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/axis_mux_64_4.v")
srcs.append("../rtl/arbiter.v")
srcs.append("../rtl/priority_encoder.v")
srcs.append("test_%s.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_axis_arb_mux_64_4(clk,
rst,
current_test,
input_0_axis_tdata,
input_0_axis_tkeep,
input_0_axis_tvalid,
input_0_axis_tready,
input_0_axis_tlast,
input_0_axis_tuser,
input_1_axis_tdata,
input_1_axis_tkeep,
input_1_axis_tvalid,
input_1_axis_tready,
input_1_axis_tlast,
input_1_axis_tuser,
input_2_axis_tdata,
input_2_axis_tkeep,
input_2_axis_tvalid,
input_2_axis_tready,
input_2_axis_tlast,
input_2_axis_tuser,
input_3_axis_tdata,
input_3_axis_tkeep,
input_3_axis_tvalid,
input_3_axis_tready,
input_3_axis_tlast,
input_3_axis_tuser,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_0_axis_tdata=input_0_axis_tdata,
input_0_axis_tkeep=input_0_axis_tkeep,
input_0_axis_tvalid=input_0_axis_tvalid,
input_0_axis_tready=input_0_axis_tready,
input_0_axis_tlast=input_0_axis_tlast,
input_0_axis_tuser=input_0_axis_tuser,
input_1_axis_tdata=input_1_axis_tdata,
input_1_axis_tkeep=input_1_axis_tkeep,
input_1_axis_tvalid=input_1_axis_tvalid,
input_1_axis_tready=input_1_axis_tready,
input_1_axis_tlast=input_1_axis_tlast,
input_1_axis_tuser=input_1_axis_tuser,
input_2_axis_tdata=input_2_axis_tdata,
input_2_axis_tkeep=input_2_axis_tkeep,
input_2_axis_tvalid=input_2_axis_tvalid,
input_2_axis_tready=input_2_axis_tready,
input_2_axis_tlast=input_2_axis_tlast,
input_2_axis_tuser=input_2_axis_tuser,
input_3_axis_tdata=input_3_axis_tdata,
input_3_axis_tkeep=input_3_axis_tkeep,
input_3_axis_tvalid=input_3_axis_tvalid,
input_3_axis_tready=input_3_axis_tready,
input_3_axis_tlast=input_3_axis_tlast,
input_3_axis_tuser=input_3_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
DATA_WIDTH = 64
KEEP_WIDTH = (DATA_WIDTH/8)
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_0_axis_tdata = Signal(intbv(0)[64:])
input_0_axis_tkeep = Signal(intbv(0)[8:])
input_0_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_0_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
input_0_axis_tvalid = Signal(bool(0))
input_0_axis_tlast = Signal(bool(0))
input_0_axis_tuser = Signal(bool(0))
input_1_axis_tdata = Signal(intbv(0)[64:])
input_1_axis_tkeep = Signal(intbv(0)[8:])
input_1_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_1_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
input_1_axis_tvalid = Signal(bool(0))
input_1_axis_tlast = Signal(bool(0))
input_1_axis_tuser = Signal(bool(0))
input_2_axis_tdata = Signal(intbv(0)[64:])
input_2_axis_tkeep = Signal(intbv(0)[8:])
input_2_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_2_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
input_2_axis_tvalid = Signal(bool(0))
input_2_axis_tlast = Signal(bool(0))
input_2_axis_tuser = Signal(bool(0))
input_3_axis_tdata = Signal(intbv(0)[64:])
input_3_axis_tkeep = Signal(intbv(0)[8:])
input_3_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_3_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
input_3_axis_tvalid = Signal(bool(0))
input_3_axis_tlast = Signal(bool(0))
input_3_axis_tuser = Signal(bool(0))
@ -158,117 +83,136 @@ def bench():
input_2_axis_tready = Signal(bool(0))
input_3_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[64:])
output_axis_tkeep = Signal(intbv(0)[8:])
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
# sources and sinks
source_0_queue = Queue()
source_0_pause = Signal(bool(0))
source_1_queue = Queue()
source_1_pause = Signal(bool(0))
source_2_queue = Queue()
source_2_pause = Signal(bool(0))
source_3_queue = Queue()
source_3_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source_0 = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_0_axis_tdata,
tkeep=input_0_axis_tkeep,
tvalid=input_0_axis_tvalid,
tready=input_0_axis_tready,
tlast=input_0_axis_tlast,
tuser=input_0_axis_tuser,
fifo=source_0_queue,
pause=source_0_pause,
name='source0')
source_1 = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_1_axis_tdata,
tkeep=input_1_axis_tkeep,
tvalid=input_1_axis_tvalid,
tready=input_1_axis_tready,
tlast=input_1_axis_tlast,
tuser=input_1_axis_tuser,
fifo=source_1_queue,
pause=source_1_pause,
name='source1')
source_2 = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_2_axis_tdata,
tkeep=input_2_axis_tkeep,
tvalid=input_2_axis_tvalid,
tready=input_2_axis_tready,
tlast=input_2_axis_tlast,
tuser=input_2_axis_tuser,
fifo=source_2_queue,
pause=source_2_pause,
name='source2')
source_3 = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_3_axis_tdata,
tkeep=input_3_axis_tkeep,
tvalid=input_3_axis_tvalid,
tready=input_3_axis_tready,
tlast=input_3_axis_tlast,
tuser=input_3_axis_tuser,
fifo=source_3_queue,
pause=source_3_pause,
name='source3')
source_0 = axis_ep.AXIStreamSource()
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
source_0_logic = source_0.create_logic(
clk,
rst,
tdata=input_0_axis_tdata,
tkeep=input_0_axis_tkeep,
tvalid=input_0_axis_tvalid,
tready=input_0_axis_tready,
tlast=input_0_axis_tlast,
tuser=input_0_axis_tuser,
pause=source_0_pause,
name='source_0'
)
source_1 = axis_ep.AXIStreamSource()
source_1_logic = source_1.create_logic(
clk,
rst,
tdata=input_1_axis_tdata,
tkeep=input_1_axis_tkeep,
tvalid=input_1_axis_tvalid,
tready=input_1_axis_tready,
tlast=input_1_axis_tlast,
tuser=input_1_axis_tuser,
pause=source_1_pause,
name='source_1'
)
source_2 = axis_ep.AXIStreamSource()
source_2_logic = source_2.create_logic(
clk,
rst,
tdata=input_2_axis_tdata,
tkeep=input_2_axis_tkeep,
tvalid=input_2_axis_tvalid,
tready=input_2_axis_tready,
tlast=input_2_axis_tlast,
tuser=input_2_axis_tuser,
pause=source_2_pause,
name='source_2'
)
source_3 = axis_ep.AXIStreamSource()
source_3_logic = source_3.create_logic(
clk,
rst,
tdata=input_3_axis_tdata,
tkeep=input_3_axis_tkeep,
tvalid=input_3_axis_tvalid,
tready=input_3_axis_tready,
tlast=input_3_axis_tlast,
tuser=input_3_axis_tuser,
pause=source_3_pause,
name='source_3'
)
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink'
)
# DUT
dut = dut_axis_arb_mux_64_4(clk,
rst,
current_test,
if os.system(build_cmd):
raise Exception("Error running build command")
input_0_axis_tdata,
input_0_axis_tkeep,
input_0_axis_tvalid,
input_0_axis_tready,
input_0_axis_tlast,
input_0_axis_tuser,
input_1_axis_tdata,
input_1_axis_tkeep,
input_1_axis_tvalid,
input_1_axis_tready,
input_1_axis_tlast,
input_1_axis_tuser,
input_2_axis_tdata,
input_2_axis_tkeep,
input_2_axis_tvalid,
input_2_axis_tready,
input_2_axis_tlast,
input_2_axis_tuser,
input_3_axis_tdata,
input_3_axis_tkeep,
input_3_axis_tvalid,
input_3_axis_tready,
input_3_axis_tlast,
input_3_axis_tuser,
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser)
input_0_axis_tdata=input_0_axis_tdata,
input_0_axis_tkeep=input_0_axis_tkeep,
input_0_axis_tvalid=input_0_axis_tvalid,
input_0_axis_tready=input_0_axis_tready,
input_0_axis_tlast=input_0_axis_tlast,
input_0_axis_tuser=input_0_axis_tuser,
input_1_axis_tdata=input_1_axis_tdata,
input_1_axis_tkeep=input_1_axis_tkeep,
input_1_axis_tvalid=input_1_axis_tvalid,
input_1_axis_tready=input_1_axis_tready,
input_1_axis_tlast=input_1_axis_tlast,
input_1_axis_tuser=input_1_axis_tuser,
input_2_axis_tdata=input_2_axis_tdata,
input_2_axis_tkeep=input_2_axis_tkeep,
input_2_axis_tvalid=input_2_axis_tvalid,
input_2_axis_tready=input_2_axis_tready,
input_2_axis_tlast=input_2_axis_tlast,
input_2_axis_tuser=input_2_axis_tuser,
input_3_axis_tdata=input_3_axis_tdata,
input_3_axis_tkeep=input_3_axis_tkeep,
input_3_axis_tvalid=input_3_axis_tvalid,
input_3_axis_tready=input_3_axis_tready,
input_3_axis_tlast=input_3_axis_tlast,
input_3_axis_tuser=input_3_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser
)
@always(delay(4))
def clkgen():
@ -295,7 +239,7 @@ def bench():
b'\x5A\x00\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_0_queue.put(test_frame)
source_0.send(test_frame)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
@ -303,9 +247,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -319,7 +261,7 @@ def bench():
b'\x5A\x01\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_1_queue.put(test_frame)
source_1.send(test_frame)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
@ -327,9 +269,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -347,8 +287,8 @@ def bench():
b'\x5A\x00\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_0_queue.put(test_frame1)
source_0_queue.put(test_frame2)
source_0.send(test_frame1)
source_0.send(test_frame2)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
@ -356,15 +296,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -382,8 +318,8 @@ def bench():
b'\x5A\x02\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_1_queue.put(test_frame1)
source_2_queue.put(test_frame2)
source_1.send(test_frame1)
source_2.send(test_frame2)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
@ -391,15 +327,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -417,8 +349,8 @@ def bench():
b'\x5A\x02\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_1_queue.put(test_frame1)
source_2_queue.put(test_frame2)
source_1.send(test_frame1)
source_2.send(test_frame2)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
@ -437,15 +369,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -463,8 +391,8 @@ def bench():
b'\x5A\x02\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_1_queue.put(test_frame1)
source_2_queue.put(test_frame2)
source_1.send(test_frame1)
source_2.send(test_frame2)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
@ -477,23 +405,19 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 4: back-to-back packets, different ports, arbitration test")
current_test.next = 4
print("test 7: back-to-back packets, different ports, arbitration test")
current_test.next = 7
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x01\x52\x53\x54\x55' +
@ -503,56 +427,44 @@ def bench():
b'\x5A\x02\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_1_queue.put(test_frame1)
source_2_queue.put(test_frame2)
source_2_queue.put(test_frame2)
source_2_queue.put(test_frame2)
source_2_queue.put(test_frame2)
source_2_queue.put(test_frame2)
source_1.send(test_frame1)
source_2.send(test_frame2)
source_2.send(test_frame2)
source_2.send(test_frame2)
source_2.send(test_frame2)
source_2.send(test_frame2)
yield clk.posedge
yield delay(150)
yield clk.posedge
source_1_queue.put(test_frame1)
source_1.send(test_frame1)
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -560,7 +472,7 @@ def bench():
raise StopSimulation
return dut, source_0, source_1, source_2, source_3, sink, clkgen, check
return dut, source_0_logic, source_1_logic, source_2_logic, source_3_logic, sink_logic, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))

101
lib/axis/tb/test_axis_arb_mux_64_4.v
View File

@ -24,32 +24,39 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1 ns / 1 ps
`timescale 1ns / 1ps
/*
* Testbench for axis_arb_mux_64_4
*/
module test_axis_arb_mux_64_4;
// Parameters
localparam DATA_WIDTH = 64;
localparam KEEP_WIDTH = (DATA_WIDTH/8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [63:0] input_0_axis_tdata = 0;
reg [7:0] input_0_axis_tkeep = 0;
reg [DATA_WIDTH-1:0] input_0_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_0_axis_tkeep = 0;
reg input_0_axis_tvalid = 0;
reg input_0_axis_tlast = 0;
reg input_0_axis_tuser = 0;
reg [63:0] input_1_axis_tdata = 0;
reg [7:0] input_1_axis_tkeep = 0;
reg [DATA_WIDTH-1:0] input_1_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_1_axis_tkeep = 0;
reg input_1_axis_tvalid = 0;
reg input_1_axis_tlast = 0;
reg input_1_axis_tuser = 0;
reg [63:0] input_2_axis_tdata = 0;
reg [7:0] input_2_axis_tkeep = 0;
reg [DATA_WIDTH-1:0] input_2_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_2_axis_tkeep = 0;
reg input_2_axis_tvalid = 0;
reg input_2_axis_tlast = 0;
reg input_2_axis_tuser = 0;
reg [63:0] input_3_axis_tdata = 0;
reg [7:0] input_3_axis_tkeep = 0;
reg [DATA_WIDTH-1:0] input_3_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_3_axis_tkeep = 0;
reg input_3_axis_tvalid = 0;
reg input_3_axis_tlast = 0;
reg input_3_axis_tuser = 0;
@ -62,47 +69,51 @@ wire input_1_axis_tready;
wire input_2_axis_tready;
wire input_3_axis_tready;
wire [63:0] output_axis_tdata;
wire [7:0] output_axis_tkeep;
wire [DATA_WIDTH-1:0] output_axis_tdata;
wire [KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_0_axis_tdata,
input_0_axis_tkeep,
input_0_axis_tvalid,
input_0_axis_tlast,
input_0_axis_tuser,
input_1_axis_tdata,
input_1_axis_tkeep,
input_1_axis_tvalid,
input_1_axis_tlast,
input_1_axis_tuser,
input_2_axis_tdata,
input_2_axis_tkeep,
input_2_axis_tvalid,
input_2_axis_tlast,
input_2_axis_tuser,
input_3_axis_tdata,
input_3_axis_tkeep,
input_3_axis_tvalid,
input_3_axis_tlast,
input_3_axis_tuser,
output_axis_tready);
$to_myhdl(input_0_axis_tready,
input_1_axis_tready,
input_2_axis_tready,
input_3_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
$from_myhdl(
clk,
rst,
current_test,
input_0_axis_tdata,
input_0_axis_tkeep,
input_0_axis_tvalid,
input_0_axis_tlast,
input_0_axis_tuser,
input_1_axis_tdata,
input_1_axis_tkeep,
input_1_axis_tvalid,
input_1_axis_tlast,
input_1_axis_tuser,
input_2_axis_tdata,
input_2_axis_tkeep,
input_2_axis_tvalid,
input_2_axis_tlast,
input_2_axis_tuser,
input_3_axis_tdata,
input_3_axis_tkeep,
input_3_axis_tvalid,
input_3_axis_tlast,
input_3_axis_tuser,
output_axis_tready
);
$to_myhdl(
input_0_axis_tready,
input_1_axis_tready,
input_2_axis_tready,
input_3_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser
);
// dump file
$dumpfile("test_axis_arb_mux_64_4.lxt");
@ -110,7 +121,7 @@ initial begin
end
axis_arb_mux_64_4 #(
.DATA_WIDTH(64)
.DATA_WIDTH(DATA_WIDTH)
)
UUT (
.clk(clk),

209
lib/axis/tb/test_axis_async_fifo.py
View File

@ -26,70 +26,33 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_async_fifo'
testbench = 'test_%s' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_axis_async_fifo(async_rst,
input_clk,
output_clk,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
async_rst=async_rst,
input_clk=input_clk,
output_clk=output_clk,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
ADDR_WIDTH = 2
DATA_WIDTH = 8
# Inputs
async_rst = Signal(bool(0))
input_clk = Signal(bool(0))
output_clk = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
@ -97,56 +60,66 @@ def bench():
# Outputs
input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[8:])
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(input_clk,
async_rst,
tdata=input_axis_tdata,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
source = axis_ep.AXIStreamSource()
sink = axis_ep.AXIStreamSink(output_clk,
async_rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
source_logic = source.create_logic(
input_clk,
async_rst,
tdata=input_axis_tdata,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
pause=source_pause,
name='source'
)
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
output_clk,
async_rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink'
)
# DUT
dut = dut_axis_async_fifo(async_rst,
input_clk,
output_clk,
current_test,
if os.system(build_cmd):
raise Exception("Error running build command")
input_axis_tdata,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
async_rst=async_rst,
input_clk=input_clk,
output_clk=output_clk,
current_test=current_test,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser)
input_axis_tdata=input_axis_tdata,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser
)
@always(delay(4))
def input_clkgen():
@ -179,16 +152,14 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame)
source.send(test_frame)
yield input_clk.posedge
yield output_axis_tlast.posedge
yield output_clk.posedge
yield output_clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -202,16 +173,14 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
source_queue.put(test_frame)
source.send(test_frame)
yield input_clk.posedge
yield output_axis_tlast.posedge
yield output_clk.posedge
yield output_clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -223,7 +192,7 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame)
source.send(test_frame)
yield input_clk.posedge
yield delay(64)
@ -244,9 +213,7 @@ def bench():
yield output_clk.posedge
yield output_clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -264,8 +231,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield input_clk.posedge
yield output_axis_tlast.posedge
@ -274,15 +241,11 @@ def bench():
yield output_clk.posedge
yield output_clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -300,8 +263,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield input_clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -315,15 +278,11 @@ def bench():
yield output_clk.posedge
yield output_clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -341,8 +300,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield input_clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -356,15 +315,11 @@ def bench():
yield output_clk.posedge
yield output_clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -379,16 +334,14 @@ def bench():
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame.user = 1
source_queue.put(test_frame)
source.send(test_frame)
yield input_clk.posedge
yield output_axis_tlast.posedge
yield output_clk.posedge
yield output_clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
assert rx_frame.user[-1]
@ -402,7 +355,7 @@ def bench():
test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
sink_pause.next = 1
source_queue.put(test_frame)
source.send(test_frame)
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
@ -413,9 +366,7 @@ def bench():
yield output_clk.posedge
yield output_clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -428,7 +379,7 @@ def bench():
test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
sink_pause.next = 1
source_queue.put(test_frame)
source.send(test_frame)
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
@ -446,13 +397,13 @@ def bench():
yield output_clk.posedge
yield output_clk.posedge
assert sink_queue.empty()
assert sink.empty()
yield delay(100)
raise StopSimulation
return dut, source, sink, input_clkgen, output_clkgen, check
return dut, source_logic, sink_logic, input_clkgen, output_clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))

49
lib/axis/tb/test_axis_async_fifo.v
View File

@ -24,17 +24,24 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1 ns / 1 ps
`timescale 1ns / 1ps
/*
* Testbench for axis_async_fifo
*/
module test_axis_async_fifo;
// Parameters
parameter ADDR_WIDTH = 2;
parameter DATA_WIDTH = 8;
// Inputs
reg async_rst = 0;
reg input_clk = 0;
reg output_clk = 0;
reg [7:0] current_test = 0;
reg [7:0] input_axis_tdata = 0;
reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
@ -42,27 +49,31 @@ reg output_axis_tready = 0;
// Outputs
wire input_axis_tready;
wire [7:0] output_axis_tdata;
wire [DATA_WIDTH-1:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(async_rst,
input_clk,
output_clk,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
$from_myhdl(
async_rst,
input_clk,
output_clk,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready
);
$to_myhdl(
input_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser
);
// dump file
$dumpfile("test_axis_async_fifo.lxt");
@ -70,8 +81,8 @@ initial begin
end
axis_async_fifo #(
.ADDR_WIDTH(2),
.DATA_WIDTH(8)
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH)
)
UUT (
// Common reset

226
lib/axis/tb/test_axis_async_fifo_64.py
View File

@ -26,75 +26,35 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_async_fifo_64'
testbench = 'test_%s' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_axis_async_fifo_64(async_rst,
input_clk,
output_clk,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
async_rst=async_rst,
input_clk=input_clk,
output_clk=output_clk,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
ADDR_WIDTH = 2
DATA_WIDTH = 64
KEEP_WIDTH = (DATA_WIDTH/8)
# Inputs
async_rst = Signal(bool(0))
input_clk = Signal(bool(0))
output_clk = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[64:])
input_axis_tkeep = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
@ -102,61 +62,71 @@ def bench():
# Outputs
input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[64:])
output_axis_tkeep = Signal(intbv(0)[8:])
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(input_clk,
async_rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
source = axis_ep.AXIStreamSource()
sink = axis_ep.AXIStreamSink(output_clk,
async_rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
source_logic = source.create_logic(
input_clk,
async_rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
pause=source_pause,
name='source'
)
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
output_clk,
async_rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink'
)
# DUT
dut = dut_axis_async_fifo_64(async_rst,
input_clk,
output_clk,
current_test,
if os.system(build_cmd):
raise Exception("Error running build command")
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
async_rst=async_rst,
input_clk=input_clk,
output_clk=output_clk,
current_test=current_test,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser)
input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser
)
@always(delay(4))
def input_clkgen():
@ -189,16 +159,14 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame)
source.send(test_frame)
yield input_clk.posedge
yield output_axis_tlast.posedge
yield output_clk.posedge
yield output_clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -212,16 +180,14 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
source_queue.put(test_frame)
source.send(test_frame)
yield input_clk.posedge
yield output_axis_tlast.posedge
yield output_clk.posedge
yield output_clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -233,7 +199,7 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
source_queue.put(test_frame)
source.send(test_frame)
yield input_clk.posedge
yield delay(64)
@ -254,9 +220,7 @@ def bench():
yield output_clk.posedge
yield output_clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -274,8 +238,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield input_clk.posedge
yield output_axis_tlast.posedge
@ -284,15 +248,11 @@ def bench():
yield output_clk.posedge
yield output_clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -310,8 +270,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield input_clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -325,15 +285,11 @@ def bench():
yield output_clk.posedge
yield output_clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -351,8 +307,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield input_clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -366,15 +322,11 @@ def bench():
yield output_clk.posedge
yield output_clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -389,16 +341,14 @@ def bench():
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame.user = 1
source_queue.put(test_frame)
source.send(test_frame)
yield input_clk.posedge
yield output_axis_tlast.posedge
yield output_clk.posedge
yield output_clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
assert rx_frame.user[-1]
@ -412,7 +362,7 @@ def bench():
test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
sink_pause.next = 1
source_queue.put(test_frame)
source.send(test_frame)
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
@ -423,9 +373,7 @@ def bench():
yield output_clk.posedge
yield output_clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -438,7 +386,7 @@ def bench():
test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
sink_pause.next = 1
source_queue.put(test_frame)
source.send(test_frame)
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
@ -456,13 +404,13 @@ def bench():
yield output_clk.posedge
yield output_clk.posedge
assert sink_queue.empty()
assert sink.empty()
yield delay(100)
raise StopSimulation
return dut, source, sink, input_clkgen, output_clkgen, check
return dut, source_logic, sink_logic, input_clkgen, output_clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))

59
lib/axis/tb/test_axis_async_fifo_64.v
View File

@ -24,18 +24,26 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1 ns / 1 ps
`timescale 1ns / 1ps
/*
* Testbench for axis_async_fifo_64
*/
module test_axis_async_fifo_64;
// Parameters
parameter ADDR_WIDTH = 2;
parameter DATA_WIDTH = 64;
parameter KEEP_WIDTH = (DATA_WIDTH/8);
// Inputs
reg async_rst = 0;
reg input_clk = 0;
reg output_clk = 0;
reg [7:0] current_test = 0;
reg [63:0] input_axis_tdata = 0;
reg [7:0] input_axis_tkeep = 0;
reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
@ -43,30 +51,34 @@ reg output_axis_tready = 0;
// Outputs
wire input_axis_tready;
wire [63:0] output_axis_tdata;
wire [7:0] output_axis_tkeep;
wire [DATA_WIDTH-1:0] output_axis_tdata;
wire [KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(async_rst,
input_clk,
output_clk,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
$from_myhdl(
async_rst,
input_clk,
output_clk,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready
);
$to_myhdl(
input_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser
);
// dump file
$dumpfile("test_axis_async_fifo_64.lxt");
@ -74,8 +86,9 @@ initial begin
end
axis_async_fifo_64 #(
.ADDR_WIDTH(2),
.DATA_WIDTH(64)
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH)
)
UUT (
// Common reset

232
lib/axis/tb/test_axis_async_frame_fifo.py
View File

@ -26,82 +26,34 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_async_frame_fifo'
testbench = 'test_%s' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_axis_async_frame_fifo(async_rst,
input_clk,
output_clk,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
input_status_overflow,
input_status_bad_frame,
input_status_good_frame,
output_status_overflow,
output_status_bad_frame,
output_status_good_frame):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
async_rst=async_rst,
input_clk=input_clk,
output_clk=output_clk,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
input_status_overflow=input_status_overflow,
input_status_bad_frame=input_status_bad_frame,
input_status_good_frame=input_status_good_frame,
output_status_overflow=output_status_overflow,
output_status_bad_frame=output_status_bad_frame,
output_status_good_frame=output_status_good_frame)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
ADDR_WIDTH = 9
DATA_WIDTH = 8
DROP_WHEN_FULL = 0
# Inputs
async_rst = Signal(bool(0))
input_clk = Signal(bool(0))
output_clk = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
@ -109,7 +61,7 @@ def bench():
# Outputs
input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[8:])
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
input_status_overflow = Signal(bool(0))
@ -120,55 +72,65 @@ def bench():
output_status_good_frame = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(input_clk,
async_rst,
tdata=input_axis_tdata,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
source = axis_ep.AXIStreamSource()
sink = axis_ep.AXIStreamSink(output_clk,
async_rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
fifo=sink_queue,
pause=sink_pause,
name='sink')
source_logic = source.create_logic(
input_clk,
async_rst,
tdata=input_axis_tdata,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
pause=source_pause,
name='source'
)
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
output_clk,
async_rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
pause=sink_pause,
name='sink'
)
# DUT
dut = dut_axis_async_frame_fifo(async_rst,
input_clk,
output_clk,
current_test,
if os.system(build_cmd):
raise Exception("Error running build command")
input_axis_tdata,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
async_rst=async_rst,
input_clk=input_clk,
output_clk=output_clk,
current_test=current_test,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
input_axis_tdata=input_axis_tdata,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
input_status_overflow,
input_status_bad_frame,
input_status_good_frame,
output_status_overflow,
output_status_bad_frame,
output_status_good_frame)
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
input_status_overflow=input_status_overflow,
input_status_bad_frame=input_status_bad_frame,
input_status_good_frame=input_status_good_frame,
output_status_overflow=output_status_overflow,
output_status_bad_frame=output_status_bad_frame,
output_status_good_frame=output_status_good_frame
)
@always(delay(4))
def input_clkgen():
@ -234,16 +196,14 @@ def bench():
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source_queue.put(test_frame)
source.send(test_frame)
yield input_clk.posedge
yield output_axis_tlast.posedge
yield output_clk.posedge
yield output_clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -272,16 +232,14 @@ def bench():
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source_queue.put(test_frame)
source.send(test_frame)
yield input_clk.posedge
yield output_axis_tlast.posedge
yield output_clk.posedge
yield output_clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -308,7 +266,7 @@ def bench():
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source_queue.put(test_frame)
source.send(test_frame)
yield input_clk.posedge
yield delay(64)
@ -329,9 +287,7 @@ def bench():
yield output_clk.posedge
yield output_clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -364,8 +320,8 @@ def bench():
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield input_clk.posedge
yield output_axis_tlast.posedge
@ -374,15 +330,11 @@ def bench():
yield output_clk.posedge
yield output_clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -415,8 +367,8 @@ def bench():
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield input_clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -434,15 +386,11 @@ def bench():
yield output_clk.posedge
yield output_clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -475,8 +423,8 @@ def bench():
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield input_clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -490,15 +438,11 @@ def bench():
yield output_clk.posedge
yield output_clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -528,12 +472,12 @@ def bench():
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source_queue.put(test_frame)
source.send(test_frame)
yield input_clk.posedge
yield delay(1000)
assert sink_queue.empty()
assert sink.empty()
assert not input_status_overflow_asserted
assert input_status_bad_frame_asserted
@ -560,12 +504,12 @@ def bench():
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source_queue.put(test_frame)
source.send(test_frame)
yield input_clk.posedge
yield delay(10000)
assert sink_queue.empty()
assert sink.empty()
assert input_status_overflow_asserted
assert not input_status_bad_frame_asserted
@ -583,7 +527,7 @@ def bench():
test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
sink_pause.next = 1
source_queue.put(test_frame)
source.send(test_frame)
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
@ -594,9 +538,7 @@ def bench():
yield output_clk.posedge
yield output_clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -609,7 +551,7 @@ def bench():
test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
sink_pause.next = 1
source_queue.put(test_frame)
source.send(test_frame)
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
@ -627,13 +569,13 @@ def bench():
yield output_clk.posedge
yield output_clk.posedge
assert sink_queue.empty()
assert sink.empty()
yield delay(100)
raise StopSimulation
return dut, monitor_1, monitor_2, source, sink, input_clkgen, output_clkgen, check
return dut, monitor_1, monitor_2, source_logic, sink_logic, input_clkgen, output_clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))

62
lib/axis/tb/test_axis_async_frame_fifo.v
View File

@ -24,17 +24,25 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1 ns / 1 ps
`timescale 1ns / 1ps
/*
* Testbench for axis_async_frame_fifo
*/
module test_axis_async_frame_fifo;
// Parameters
parameter ADDR_WIDTH = 9;
parameter DATA_WIDTH = 8;
parameter DROP_WHEN_FULL = 0;
// Inputs
reg async_rst = 0;
reg input_clk = 0;
reg output_clk = 0;
reg [7:0] current_test = 0;
reg [7:0] input_axis_tdata = 0;
reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
@ -42,7 +50,7 @@ reg output_axis_tready = 0;
// Outputs
wire input_axis_tready;
wire [7:0] output_axis_tdata;
wire [DATA_WIDTH-1:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
wire input_status_overflow;
@ -54,25 +62,29 @@ wire output_status_good_frame;
initial begin
// myhdl integration
$from_myhdl(async_rst,
input_clk,
output_clk,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
input_status_overflow,
input_status_bad_frame,
input_status_good_frame,
output_status_overflow,
output_status_bad_frame,
output_status_good_frame);
$from_myhdl(
async_rst,
input_clk,
output_clk,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready
);
$to_myhdl(
input_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
input_status_overflow,
input_status_bad_frame,
input_status_good_frame,
output_status_overflow,
output_status_bad_frame,
output_status_good_frame
);
// dump file
$dumpfile("test_axis_async_frame_fifo.lxt");
@ -80,9 +92,9 @@ initial begin
end
axis_async_frame_fifo #(
.ADDR_WIDTH(9),
.DATA_WIDTH(8),
.DROP_WHEN_FULL(0)
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.DROP_WHEN_FULL(DROP_WHEN_FULL)
)
UUT (
// Common reset

249
lib/axis/tb/test_axis_async_frame_fifo_64.py
View File

@ -26,87 +26,36 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_async_frame_fifo_64'
testbench = 'test_%s' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_axis_async_frame_fifo_64(async_rst,
input_clk,
output_clk,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
input_status_overflow,
input_status_bad_frame,
input_status_good_frame,
output_status_overflow,
output_status_bad_frame,
output_status_good_frame):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
async_rst=async_rst,
input_clk=input_clk,
output_clk=output_clk,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
input_status_overflow=input_status_overflow,
input_status_bad_frame=input_status_bad_frame,
input_status_good_frame=input_status_good_frame,
output_status_overflow=output_status_overflow,
output_status_bad_frame=output_status_bad_frame,
output_status_good_frame=output_status_good_frame)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
ADDR_WIDTH = 6
DATA_WIDTH = 64
KEEP_WIDTH = (DATA_WIDTH/8)
DROP_WHEN_FULL = 0
# Inputs
async_rst = Signal(bool(0))
input_clk = Signal(bool(0))
output_clk = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[64:])
input_axis_tkeep = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
@ -114,8 +63,8 @@ def bench():
# Outputs
input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[64:])
output_axis_tkeep = Signal(intbv(0)[8:])
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
input_status_overflow = Signal(bool(0))
@ -126,59 +75,69 @@ def bench():
output_status_good_frame = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(input_clk,
async_rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
source = axis_ep.AXIStreamSource()
sink = axis_ep.AXIStreamSink(output_clk,
async_rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
fifo=sink_queue,
pause=sink_pause,
name='sink')
source_logic = source.create_logic(
input_clk,
async_rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
pause=source_pause,
name='source'
)
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
output_clk,
async_rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
pause=sink_pause,
name='sink'
)
# DUT
dut = dut_axis_async_frame_fifo_64(async_rst,
input_clk,
output_clk,
current_test,
if os.system(build_cmd):
raise Exception("Error running build command")
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
async_rst=async_rst,
input_clk=input_clk,
output_clk=output_clk,
current_test=current_test,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
input_status_overflow,
input_status_bad_frame,
input_status_good_frame,
output_status_overflow,
output_status_bad_frame,
output_status_good_frame)
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
input_status_overflow=input_status_overflow,
input_status_bad_frame=input_status_bad_frame,
input_status_good_frame=input_status_good_frame,
output_status_overflow=output_status_overflow,
output_status_bad_frame=output_status_bad_frame,
output_status_good_frame=output_status_good_frame
)
@always(delay(4))
def input_clkgen():
@ -244,16 +203,14 @@ def bench():
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source_queue.put(test_frame)
source.send(test_frame)
yield input_clk.posedge
yield output_axis_tlast.posedge
yield output_clk.posedge
yield output_clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -282,16 +239,14 @@ def bench():
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source_queue.put(test_frame)
source.send(test_frame)
yield input_clk.posedge
yield output_axis_tlast.posedge
yield output_clk.posedge
yield output_clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -318,7 +273,7 @@ def bench():
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source_queue.put(test_frame)
source.send(test_frame)
yield input_clk.posedge
yield delay(64)
@ -339,9 +294,7 @@ def bench():
yield output_clk.posedge
yield output_clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -374,8 +327,8 @@ def bench():
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield input_clk.posedge
yield output_axis_tlast.posedge
@ -384,15 +337,11 @@ def bench():
yield output_clk.posedge
yield output_clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -425,8 +374,8 @@ def bench():
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield input_clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -444,15 +393,11 @@ def bench():
yield output_clk.posedge
yield output_clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -485,8 +430,8 @@ def bench():
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield input_clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -500,15 +445,11 @@ def bench():
yield output_clk.posedge
yield output_clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -538,12 +479,12 @@ def bench():
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source_queue.put(test_frame)
source.send(test_frame)
yield input_clk.posedge
yield delay(1000)
assert sink_queue.empty()
assert sink.empty()
assert not input_status_overflow_asserted
assert input_status_bad_frame_asserted
@ -570,12 +511,12 @@ def bench():
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source_queue.put(test_frame)
source.send(test_frame)
yield input_clk.posedge
yield delay(10000)
assert sink_queue.empty()
assert sink.empty()
assert input_status_overflow_asserted
assert not input_status_bad_frame_asserted
@ -593,7 +534,7 @@ def bench():
test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
sink_pause.next = 1
source_queue.put(test_frame)
source.send(test_frame)
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
@ -604,9 +545,7 @@ def bench():
yield output_clk.posedge
yield output_clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -619,7 +558,7 @@ def bench():
test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
sink_pause.next = 1
source_queue.put(test_frame)
source.send(test_frame)
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
@ -637,13 +576,13 @@ def bench():
yield output_clk.posedge
yield output_clk.posedge
assert sink_queue.empty()
assert sink.empty()
yield delay(100)
raise StopSimulation
return dut, monitor_1, monitor_2, source, sink, input_clkgen, output_clkgen, check
return dut, monitor_1, monitor_2, source_logic, sink_logic, input_clkgen, output_clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))

72
lib/axis/tb/test_axis_async_frame_fifo_64.v
View File

@ -24,18 +24,27 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1 ns / 1 ps
`timescale 1ns / 1ps
/*
* Testbench for axis_async_frame_fifo_64
*/
module test_axis_async_frame_fifo_64;
// Parameters
parameter ADDR_WIDTH = 6;
parameter DATA_WIDTH = 64;
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter DROP_WHEN_FULL = 0;
// Inputs
reg async_rst = 0;
reg input_clk = 0;
reg output_clk = 0;
reg [7:0] current_test = 0;
reg [63:0] input_axis_tdata = 0;
reg [7:0] input_axis_tkeep = 0;
reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
@ -43,8 +52,8 @@ reg output_axis_tready = 0;
// Outputs
wire input_axis_tready;
wire [63:0] output_axis_tdata;
wire [7:0] output_axis_tkeep;
wire [DATA_WIDTH-1:0] output_axis_tdata;
wire [KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid;
wire output_axis_tlast;
wire input_status_overflow;
@ -56,27 +65,31 @@ wire output_status_good_frame;
initial begin
// myhdl integration
$from_myhdl(async_rst,
input_clk,
output_clk,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
input_status_overflow,
input_status_bad_frame,
input_status_good_frame,
output_status_overflow,
output_status_bad_frame,
output_status_good_frame);
$from_myhdl(
async_rst,
input_clk,
output_clk,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready
);
$to_myhdl(
input_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
input_status_overflow,
input_status_bad_frame,
input_status_good_frame,
output_status_overflow,
output_status_bad_frame,
output_status_good_frame
);
// dump file
$dumpfile("test_axis_async_frame_fifo_64.lxt");
@ -84,9 +97,10 @@ initial begin
end
axis_async_frame_fifo_64 #(
.ADDR_WIDTH(6),
.DATA_WIDTH(64),
.DROP_WHEN_FULL(0)
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.DROP_WHEN_FULL(DROP_WHEN_FULL)
)
UUT (
// Common reset

188
lib/axis/tb/test_axis_cobs_decode.py
View File

@ -26,15 +26,10 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_cobs_decode'
testbench = 'test_axis_cobs_decode'
testbench = 'test_%s' % module
srcs = []
@ -45,37 +40,6 @@ src = ' '.join(srcs)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def dut_axis_cobs_decode(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser)
def cobs_encode(block):
block = bytearray(block)
enc = bytearray()
@ -167,47 +131,59 @@ def bench():
output_axis_tuser = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_axis_tdata,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
source = axis_ep.AXIStreamSource()
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
source_logic = source.create_logic(
clk,
rst,
tdata=input_axis_tdata,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
pause=source_pause,
name='source'
)
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink'
)
# DUT
dut = dut_axis_cobs_decode(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser)
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser
)
@always(delay(4))
def clkgen():
@ -217,7 +193,7 @@ def bench():
i = 4
while i > 0:
i = max(0, i-1)
if input_axis_tvalid or output_axis_tvalid or not source_queue.empty():
if input_axis_tvalid or output_axis_tvalid or not source.empty():
i = 4
yield clk.posedge
@ -225,7 +201,7 @@ def bench():
i = 2
while i > 0:
i = max(0, i-1)
if input_axis_tvalid or output_axis_tvalid or not source_queue.empty():
if input_axis_tvalid or output_axis_tvalid or not source.empty():
i = 2
source_pause.next = True
yield clk.posedge
@ -238,7 +214,7 @@ def bench():
i = 2
while i > 0:
i = max(0, i-1)
if input_axis_tvalid or output_axis_tvalid or not source_queue.empty():
if input_axis_tvalid or output_axis_tvalid or not source.empty():
i = 2
sink_pause.next = True
yield clk.posedge
@ -266,7 +242,7 @@ def bench():
bytearray([k%255+1 for k in range(payload_len)]),
b'\x00'+bytearray([k%255+1 for k in range(payload_len)])+b'\x00',
bytearray([next(gen) for i in range(payload_len)])]:
yield clk.posedge
print("test 1: test packet, length %d" % payload_len)
current_test.next = 1
@ -276,7 +252,7 @@ def bench():
test_frame = axis_ep.AXIStreamFrame(enc)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield clk.posedge
@ -285,13 +261,13 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = sink_queue.get(False)
rx_frame = sink.recv()
assert cobs_decode(enc) == block
assert rx_frame.data == block
assert not rx_frame.user[-1]
assert sink_queue.empty()
assert sink.empty()
yield delay(100)
@ -304,7 +280,7 @@ def bench():
test_frame = axis_ep.AXIStreamFrame(enc+b'\x00')
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield clk.posedge
@ -313,13 +289,13 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = sink_queue.get(False)
rx_frame = sink.recv()
assert cobs_decode(enc) == block
assert rx_frame.data == block
assert not rx_frame.user[-1]
assert sink_queue.empty()
assert sink.empty()
yield delay(100)
@ -331,8 +307,8 @@ def bench():
test_frame1 = axis_ep.AXIStreamFrame(enc)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
yield clk.posedge
@ -341,19 +317,19 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = sink_queue.get(False)
rx_frame = sink.recv()
assert cobs_decode(enc) == block
assert rx_frame.data == block
assert not rx_frame.user[-1]
rx_frame = sink_queue.get(False)
rx_frame = sink.recv()
assert cobs_decode(enc) == block
assert rx_frame.data == block
assert not rx_frame.user[-1]
assert sink_queue.empty()
assert sink.empty()
yield delay(100)
@ -364,7 +340,7 @@ def bench():
test_frame = axis_ep.AXIStreamFrame(enc+b'\x00'+enc+b'\x00')
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield clk.posedge
@ -373,19 +349,19 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = sink_queue.get(False)
rx_frame = sink.recv()
assert cobs_decode(enc) == block
assert rx_frame.data == block
assert not rx_frame.user[-1]
rx_frame = sink_queue.get(False)
rx_frame = sink.recv()
assert cobs_decode(enc) == block
assert rx_frame.data == block
assert not rx_frame.user[-1]
assert sink_queue.empty()
assert sink.empty()
yield delay(100)
@ -400,9 +376,9 @@ def bench():
test_frame1.user = 1
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source_queue.put(test_frame3)
source.send(test_frame1)
source.send(test_frame2)
source.send(test_frame3)
yield clk.posedge
yield clk.posedge
@ -411,21 +387,21 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = sink_queue.get(False)
rx_frame = sink.recv()
assert rx_frame.user[-1]
rx_frame = sink_queue.get(False)
rx_frame = sink.recv()
assert rx_frame.user[-1]
rx_frame = sink_queue.get(False)
rx_frame = sink.recv()
assert cobs_decode(enc) == block
assert rx_frame.data == block
assert not rx_frame.user[-1]
assert sink_queue.empty()
assert sink.empty()
yield delay(100)
@ -440,9 +416,9 @@ def bench():
test_frame1.user = 1
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source_queue.put(test_frame3)
source.send(test_frame1)
source.send(test_frame2)
source.send(test_frame3)
yield clk.posedge
yield clk.posedge
@ -451,27 +427,27 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = sink_queue.get(False)
rx_frame = sink.recv()
assert rx_frame.user[-1]
rx_frame = sink_queue.get(False)
rx_frame = sink.recv()
assert rx_frame.user[-1]
rx_frame = sink_queue.get(False)
rx_frame = sink.recv()
assert cobs_decode(enc) == block
assert rx_frame.data == block
assert not rx_frame.user[-1]
assert sink_queue.empty()
assert sink.empty()
yield delay(100)
raise StopSimulation
return dut, source, sink, clkgen, check
return dut, source_logic, sink_logic, clkgen, check
def test_bench():
sim = Simulation(bench())

30
lib/axis/tb/test_axis_cobs_decode.v
View File

@ -53,19 +53,23 @@ wire output_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
$from_myhdl(
clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready
);
$to_myhdl(
input_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser
);
// dump file
$dumpfile("test_axis_cobs_decode.lxt");

154
lib/axis/tb/test_axis_cobs_encode.py
View File

@ -26,15 +26,10 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_cobs_encode'
testbench = 'test_axis_cobs_encode'
testbench = 'test_%s' % module
srcs = []
@ -46,37 +41,6 @@ src = ' '.join(srcs)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def dut_axis_cobs_encode(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser)
def cobs_encode(block):
block = bytearray(block)
enc = bytearray()
@ -168,47 +132,59 @@ def bench():
output_axis_tuser = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_axis_tdata,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
source = axis_ep.AXIStreamSource()
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
source_logic = source.create_logic(
clk,
rst,
tdata=input_axis_tdata,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
pause=source_pause,
name='source'
)
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink'
)
# DUT
dut = dut_axis_cobs_encode(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser)
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser
)
@always(delay(4))
def clkgen():
@ -218,7 +194,7 @@ def bench():
i = 4
while i > 0:
i = max(0, i-1)
if input_axis_tvalid or output_axis_tvalid or not source_queue.empty():
if input_axis_tvalid or output_axis_tvalid or not source.empty():
i = 4
yield clk.posedge
@ -226,7 +202,7 @@ def bench():
i = 2
while i > 0:
i = max(0, i-1)
if input_axis_tvalid or output_axis_tvalid or not source_queue.empty():
if input_axis_tvalid or output_axis_tvalid or not source.empty():
i = 2
source_pause.next = True
yield clk.posedge
@ -239,7 +215,7 @@ def bench():
i = 2
while i > 0:
i = max(0, i-1)
if input_axis_tvalid or output_axis_tvalid or not source_queue.empty():
if input_axis_tvalid or output_axis_tvalid or not source.empty():
i = 2
sink_pause.next = True
yield clk.posedge
@ -276,7 +252,7 @@ def bench():
test_frame = axis_ep.AXIStreamFrame(block)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield clk.posedge
@ -285,14 +261,14 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = sink_queue.get(False)
rx_frame = sink.recv()
assert cobs_decode(enc) == block
assert rx_frame.data == enc
assert cobs_decode(rx_frame.data) == block
assert not rx_frame.user[-1]
assert sink_queue.empty()
assert sink.empty()
yield delay(100)
@ -304,8 +280,8 @@ def bench():
test_frame2 = axis_ep.AXIStreamFrame(block)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
yield clk.posedge
@ -314,21 +290,21 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = sink_queue.get(False)
rx_frame = sink.recv()
assert cobs_decode(enc) == block
assert rx_frame.data == enc
assert cobs_decode(rx_frame.data) == block
assert not rx_frame.user[-1]
rx_frame = sink_queue.get(False)
rx_frame = sink.recv()
assert cobs_decode(enc) == block
assert rx_frame.data == enc
assert cobs_decode(rx_frame.data) == block
assert not rx_frame.user[-1]
assert sink_queue.empty()
assert sink.empty()
yield delay(100)
@ -342,8 +318,8 @@ def bench():
test_frame1.user = 1
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
yield clk.posedge
@ -352,25 +328,25 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = sink_queue.get(False)
rx_frame = sink.recv()
assert cobs_decode(rx_frame.data) == None
assert rx_frame.user[-1]
rx_frame = sink_queue.get(False)
rx_frame = sink.recv()
assert cobs_decode(enc) == block
assert rx_frame.data == enc
assert cobs_decode(rx_frame.data) == block
assert not rx_frame.user[-1]
assert sink_queue.empty()
assert sink.empty()
yield delay(100)
raise StopSimulation
return dut, source, sink, clkgen, check
return dut, source_logic, sink_logic, clkgen, check
def test_bench():
sim = Simulation(bench())

30
lib/axis/tb/test_axis_cobs_encode.v
View File

@ -54,19 +54,23 @@ wire output_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
$from_myhdl(
clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready
);
$to_myhdl(
input_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser
);
// dump file
$dumpfile("test_axis_cobs_encode.lxt");

154
lib/axis/tb/test_axis_cobs_encode_zero_frame.py
View File

@ -26,15 +26,10 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_cobs_encode'
testbench = 'test_axis_cobs_encode_zero_frame'
testbench = 'test_%s_zero_frame' % module
srcs = []
@ -46,37 +41,6 @@ src = ' '.join(srcs)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def dut_axis_cobs_encode(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser)
def cobs_encode(block):
block = bytearray(block)
enc = bytearray()
@ -168,47 +132,59 @@ def bench():
output_axis_tuser = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_axis_tdata,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
source = axis_ep.AXIStreamSource()
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
source_logic = source.create_logic(
clk,
rst,
tdata=input_axis_tdata,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
pause=source_pause,
name='source'
)
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink'
)
# DUT
dut = dut_axis_cobs_encode(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser)
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser
)
@always(delay(4))
def clkgen():
@ -218,7 +194,7 @@ def bench():
i = 4
while i > 0:
i = max(0, i-1)
if input_axis_tvalid or output_axis_tvalid or not source_queue.empty():
if input_axis_tvalid or output_axis_tvalid or not source.empty():
i = 4
yield clk.posedge
@ -226,7 +202,7 @@ def bench():
i = 2
while i > 0:
i = max(0, i-1)
if input_axis_tvalid or output_axis_tvalid or not source_queue.empty():
if input_axis_tvalid or output_axis_tvalid or not source.empty():
i = 2
source_pause.next = True
yield clk.posedge
@ -239,7 +215,7 @@ def bench():
i = 2
while i > 0:
i = max(0, i-1)
if input_axis_tvalid or output_axis_tvalid or not source_queue.empty():
if input_axis_tvalid or output_axis_tvalid or not source.empty():
i = 2
sink_pause.next = True
yield clk.posedge
@ -276,7 +252,7 @@ def bench():
test_frame = axis_ep.AXIStreamFrame(block)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield clk.posedge
@ -285,14 +261,14 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = sink_queue.get(False)
rx_frame = sink.recv()
assert cobs_decode(enc) == block
assert rx_frame.data == enc+b'\x00'
assert cobs_decode(rx_frame.data[:-1]) == block
assert not rx_frame.user[-1]
assert sink_queue.empty()
assert sink.empty()
yield delay(100)
@ -304,8 +280,8 @@ def bench():
test_frame2 = axis_ep.AXIStreamFrame(block)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
yield clk.posedge
@ -314,21 +290,21 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = sink_queue.get(False)
rx_frame = sink.recv()
assert cobs_decode(enc) == block
assert rx_frame.data == enc+b'\x00'
assert cobs_decode(rx_frame.data[:-1]) == block
assert not rx_frame.user[-1]
rx_frame = sink_queue.get(False)
rx_frame = sink.recv()
assert cobs_decode(enc) == block
assert rx_frame.data == enc+b'\x00'
assert cobs_decode(rx_frame.data[:-1]) == block
assert not rx_frame.user[-1]
assert sink_queue.empty()
assert sink.empty()
yield delay(100)
@ -342,8 +318,8 @@ def bench():
test_frame1.user = 1
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
yield clk.posedge
@ -352,25 +328,25 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = sink_queue.get(False)
rx_frame = sink.recv()
assert cobs_decode(rx_frame.data[:-1]) == None
assert rx_frame.user[-1]
rx_frame = sink_queue.get(False)
rx_frame = sink.recv()
assert cobs_decode(enc) == block
assert rx_frame.data == enc+b'\x00'
assert cobs_decode(rx_frame.data[:-1]) == block
assert not rx_frame.user[-1]
assert sink_queue.empty()
assert sink.empty()
yield delay(100)
raise StopSimulation
return dut, source, sink, clkgen, check
return dut, source_logic, sink_logic, clkgen, check
def test_bench():
sim = Simulation(bench())

30
lib/axis/tb/test_axis_cobs_encode_zero_frame.v
View File

@ -54,19 +54,23 @@ wire output_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
$from_myhdl(
clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready
);
$to_myhdl(
input_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser
);
// dump file
$dumpfile("test_axis_cobs_encode_zero_frame.lxt");

428
lib/axis/tb/test_axis_crosspoint_4x4.py
View File

@ -26,116 +26,46 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_crosspoint_4x4'
testbench = 'test_%s' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_axis_crosspoint_4x4(clk,
rst,
current_test,
input_0_axis_tdata,
input_0_axis_tvalid,
input_0_axis_tlast,
input_1_axis_tdata,
input_1_axis_tvalid,
input_1_axis_tlast,
input_2_axis_tdata,
input_2_axis_tvalid,
input_2_axis_tlast,
input_3_axis_tdata,
input_3_axis_tvalid,
input_3_axis_tlast,
output_0_axis_tdata,
output_0_axis_tvalid,
output_0_axis_tlast,
output_1_axis_tdata,
output_1_axis_tvalid,
output_1_axis_tlast,
output_2_axis_tdata,
output_2_axis_tvalid,
output_2_axis_tlast,
output_3_axis_tdata,
output_3_axis_tvalid,
output_3_axis_tlast,
output_0_select,
output_1_select,
output_2_select,
output_3_select):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_0_axis_tdata=input_0_axis_tdata,
input_0_axis_tvalid=input_0_axis_tvalid,
input_0_axis_tlast=input_0_axis_tlast,
input_1_axis_tdata=input_1_axis_tdata,
input_1_axis_tvalid=input_1_axis_tvalid,
input_1_axis_tlast=input_1_axis_tlast,
input_2_axis_tdata=input_2_axis_tdata,
input_2_axis_tvalid=input_2_axis_tvalid,
input_2_axis_tlast=input_2_axis_tlast,
input_3_axis_tdata=input_3_axis_tdata,
input_3_axis_tvalid=input_3_axis_tvalid,
input_3_axis_tlast=input_3_axis_tlast,
output_0_axis_tdata=output_0_axis_tdata,
output_0_axis_tvalid=output_0_axis_tvalid,
output_0_axis_tlast=output_0_axis_tlast,
output_1_axis_tdata=output_1_axis_tdata,
output_1_axis_tvalid=output_1_axis_tvalid,
output_1_axis_tlast=output_1_axis_tlast,
output_2_axis_tdata=output_2_axis_tdata,
output_2_axis_tvalid=output_2_axis_tvalid,
output_2_axis_tlast=output_2_axis_tlast,
output_3_axis_tdata=output_3_axis_tdata,
output_3_axis_tvalid=output_3_axis_tvalid,
output_3_axis_tlast=output_3_axis_tlast,
output_0_select=output_0_select,
output_1_select=output_1_select,
output_2_select=output_2_select,
output_3_select=output_3_select)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
DATA_WIDTH = 8
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_0_axis_tdata = Signal(intbv(0)[8:])
input_0_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_0_axis_tvalid = Signal(bool(0))
input_0_axis_tlast = Signal(bool(0))
input_1_axis_tdata = Signal(intbv(0)[8:])
input_0_axis_tuser = Signal(bool(0))
input_1_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_1_axis_tvalid = Signal(bool(0))
input_1_axis_tlast = Signal(bool(0))
input_2_axis_tdata = Signal(intbv(0)[8:])
input_1_axis_tuser = Signal(bool(0))
input_2_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_2_axis_tvalid = Signal(bool(0))
input_2_axis_tlast = Signal(bool(0))
input_3_axis_tdata = Signal(intbv(0)[8:])
input_2_axis_tuser = Signal(bool(0))
input_3_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_3_axis_tvalid = Signal(bool(0))
input_3_axis_tlast = Signal(bool(0))
input_3_axis_tuser = Signal(bool(0))
output_0_select = Signal(intbv(0)[2:])
output_1_select = Signal(intbv(0)[2:])
@ -143,138 +73,186 @@ def bench():
output_3_select = Signal(intbv(0)[2:])
# Outputs
output_0_axis_tdata = Signal(intbv(0)[8:])
output_0_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_0_axis_tvalid = Signal(bool(0))
output_0_axis_tlast = Signal(bool(0))
output_1_axis_tdata = Signal(intbv(0)[8:])
output_0_axis_tuser = Signal(bool(0))
output_1_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_1_axis_tvalid = Signal(bool(0))
output_1_axis_tlast = Signal(bool(0))
output_2_axis_tdata = Signal(intbv(0)[8:])
output_1_axis_tuser = Signal(bool(0))
output_2_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_2_axis_tvalid = Signal(bool(0))
output_2_axis_tlast = Signal(bool(0))
output_3_axis_tdata = Signal(intbv(0)[8:])
output_2_axis_tuser = Signal(bool(0))
output_3_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_3_axis_tvalid = Signal(bool(0))
output_3_axis_tlast = Signal(bool(0))
output_3_axis_tuser = Signal(bool(0))
# sources and sinks
source_0_queue = Queue()
source_0_pause = Signal(bool(0))
source_1_queue = Queue()
source_1_pause = Signal(bool(0))
source_2_queue = Queue()
source_2_pause = Signal(bool(0))
source_3_queue = Queue()
source_3_pause = Signal(bool(0))
sink_0_queue = Queue()
sink_0_pause = Signal(bool(0))
sink_1_queue = Queue()
sink_1_pause = Signal(bool(0))
sink_2_queue = Queue()
sink_2_pause = Signal(bool(0))
sink_3_queue = Queue()
sink_3_pause = Signal(bool(0))
source_0 = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_0_axis_tdata,
tvalid=input_0_axis_tvalid,
tlast=input_0_axis_tlast,
fifo=source_0_queue,
pause=source_0_pause,
name='source0')
source_1 = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_1_axis_tdata,
tvalid=input_1_axis_tvalid,
tlast=input_1_axis_tlast,
fifo=source_1_queue,
pause=source_1_pause,
name='source1')
source_2 = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_2_axis_tdata,
tvalid=input_2_axis_tvalid,
tlast=input_2_axis_tlast,
fifo=source_2_queue,
pause=source_2_pause,
name='source2')
source_3 = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_3_axis_tdata,
tvalid=input_3_axis_tvalid,
tlast=input_3_axis_tlast,
fifo=source_3_queue,
pause=source_3_pause,
name='source3')
source_0 = axis_ep.AXIStreamSource()
sink_0 = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_0_axis_tdata,
tvalid=output_0_axis_tvalid,
tlast=output_0_axis_tlast,
fifo=sink_0_queue,
pause=sink_0_pause,
name='sink0')
sink_1 = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_1_axis_tdata,
tvalid=output_1_axis_tvalid,
tlast=output_1_axis_tlast,
fifo=sink_1_queue,
pause=sink_1_pause,
name='sink1')
sink_2 = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_2_axis_tdata,
tvalid=output_2_axis_tvalid,
tlast=output_2_axis_tlast,
fifo=sink_2_queue,
pause=sink_2_pause,
name='sink2')
sink_3 = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_3_axis_tdata,
tvalid=output_3_axis_tvalid,
tlast=output_3_axis_tlast,
fifo=sink_3_queue,
pause=sink_3_pause,
name='sink3')
source_0_logic = source_0.create_logic(
clk,
rst,
tdata=input_0_axis_tdata,
tvalid=input_0_axis_tvalid,
tlast=input_0_axis_tlast,
tuser=input_0_axis_tuser,
pause=source_0_pause,
name='source_0'
)
source_1 = axis_ep.AXIStreamSource()
source_1_logic = source_1.create_logic(
clk,
rst,
tdata=input_1_axis_tdata,
tvalid=input_1_axis_tvalid,
tlast=input_1_axis_tlast,
tuser=input_1_axis_tuser,
pause=source_1_pause,
name='source_1'
)
source_2 = axis_ep.AXIStreamSource()
source_2_logic = source_2.create_logic(
clk,
rst,
tdata=input_2_axis_tdata,
tvalid=input_2_axis_tvalid,
tlast=input_2_axis_tlast,
tuser=input_2_axis_tuser,
pause=source_2_pause,
name='source_2'
)
source_3 = axis_ep.AXIStreamSource()
source_3_logic = source_3.create_logic(
clk,
rst,
tdata=input_3_axis_tdata,
tvalid=input_3_axis_tvalid,
tlast=input_3_axis_tlast,
tuser=input_3_axis_tuser,
pause=source_3_pause,
name='source_3'
)
sink_0 = axis_ep.AXIStreamSink()
sink_0_logic = sink_0.create_logic(
clk,
rst,
tdata=output_0_axis_tdata,
tvalid=output_0_axis_tvalid,
tlast=output_0_axis_tlast,
tuser=output_0_axis_tuser,
pause=sink_0_pause,
name='sink_0'
)
sink_1 = axis_ep.AXIStreamSink()
sink_1_logic = sink_1.create_logic(
clk,
rst,
tdata=output_1_axis_tdata,
tvalid=output_1_axis_tvalid,
tlast=output_1_axis_tlast,
tuser=output_1_axis_tuser,
pause=sink_1_pause,
name='sink_1'
)
sink_2 = axis_ep.AXIStreamSink()
sink_2_logic = sink_2.create_logic(
clk,
rst,
tdata=output_2_axis_tdata,
tvalid=output_2_axis_tvalid,
tlast=output_2_axis_tlast,
tuser=output_2_axis_tuser,
pause=sink_2_pause,
name='sink_2'
)
sink_3 = axis_ep.AXIStreamSink()
sink_3_logic = sink_3.create_logic(
clk,
rst,
tdata=output_3_axis_tdata,
tvalid=output_3_axis_tvalid,
tlast=output_3_axis_tlast,
tuser=output_3_axis_tuser,
pause=sink_3_pause,
name='sink_3'
)
# DUT
dut = dut_axis_crosspoint_4x4(clk,
rst,
current_test,
if os.system(build_cmd):
raise Exception("Error running build command")
input_0_axis_tdata,
input_0_axis_tvalid,
input_0_axis_tlast,
input_1_axis_tdata,
input_1_axis_tvalid,
input_1_axis_tlast,
input_2_axis_tdata,
input_2_axis_tvalid,
input_2_axis_tlast,
input_3_axis_tdata,
input_3_axis_tvalid,
input_3_axis_tlast,
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
output_0_axis_tdata,
output_0_axis_tvalid,
output_0_axis_tlast,
output_1_axis_tdata,
output_1_axis_tvalid,
output_1_axis_tlast,
output_2_axis_tdata,
output_2_axis_tvalid,
output_2_axis_tlast,
output_3_axis_tdata,
output_3_axis_tvalid,
output_3_axis_tlast,
input_0_axis_tdata=input_0_axis_tdata,
input_0_axis_tvalid=input_0_axis_tvalid,
input_0_axis_tlast=input_0_axis_tlast,
input_0_axis_tuser=input_0_axis_tuser,
input_1_axis_tdata=input_1_axis_tdata,
input_1_axis_tvalid=input_1_axis_tvalid,
input_1_axis_tlast=input_1_axis_tlast,
input_1_axis_tuser=input_1_axis_tuser,
input_2_axis_tdata=input_2_axis_tdata,
input_2_axis_tvalid=input_2_axis_tvalid,
input_2_axis_tlast=input_2_axis_tlast,
input_2_axis_tuser=input_2_axis_tuser,
input_3_axis_tdata=input_3_axis_tdata,
input_3_axis_tvalid=input_3_axis_tvalid,
input_3_axis_tlast=input_3_axis_tlast,
input_3_axis_tuser=input_3_axis_tuser,
output_0_select,
output_1_select,
output_2_select,
output_3_select)
output_0_axis_tdata=output_0_axis_tdata,
output_0_axis_tvalid=output_0_axis_tvalid,
output_0_axis_tlast=output_0_axis_tlast,
output_0_axis_tuser=output_0_axis_tuser,
output_1_axis_tdata=output_1_axis_tdata,
output_1_axis_tvalid=output_1_axis_tvalid,
output_1_axis_tlast=output_1_axis_tlast,
output_1_axis_tuser=output_1_axis_tuser,
output_2_axis_tdata=output_2_axis_tdata,
output_2_axis_tvalid=output_2_axis_tvalid,
output_2_axis_tlast=output_2_axis_tlast,
output_2_axis_tuser=output_2_axis_tuser,
output_3_axis_tdata=output_3_axis_tdata,
output_3_axis_tvalid=output_3_axis_tvalid,
output_3_axis_tlast=output_3_axis_tlast,
output_3_axis_tuser=output_3_axis_tuser,
output_0_select=output_0_select,
output_1_select=output_1_select,
output_2_select=output_2_select,
output_3_select=output_3_select
)
@always(delay(4))
def clkgen():
@ -306,10 +284,10 @@ def bench():
test_frame1 = axis_ep.AXIStreamFrame(b'\x01\x01\x01\xFF\x01\x02\x03\x04')
test_frame2 = axis_ep.AXIStreamFrame(b'\x01\x02\x02\xFF\x01\x02\x03\x04')
test_frame3 = axis_ep.AXIStreamFrame(b'\x01\x03\x03\xFF\x01\x02\x03\x04')
source_0_queue.put(test_frame0)
source_1_queue.put(test_frame1)
source_2_queue.put(test_frame2)
source_3_queue.put(test_frame3)
source_0.send(test_frame0)
source_1.send(test_frame1)
source_2.send(test_frame2)
source_3.send(test_frame3)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
@ -317,27 +295,19 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame0 = None
if not sink_0_queue.empty():
rx_frame0 = sink_0_queue.get()
rx_frame0 = sink_0.recv()
assert rx_frame0 == test_frame0
rx_frame1 = None
if not sink_1_queue.empty():
rx_frame1 = sink_1_queue.get()
rx_frame1 = sink_1.recv()
assert rx_frame1 == test_frame1
rx_frame2 = None
if not sink_2_queue.empty():
rx_frame2 = sink_2_queue.get()
rx_frame2 = sink_2.recv()
assert rx_frame2 == test_frame2
rx_frame3 = None
if not sink_3_queue.empty():
rx_frame3 = sink_3_queue.get()
rx_frame3 = sink_3.recv()
assert rx_frame3 == test_frame3
@ -356,10 +326,10 @@ def bench():
test_frame1 = axis_ep.AXIStreamFrame(b'\x02\x01\x02\xFF\x01\x02\x03\x04')
test_frame2 = axis_ep.AXIStreamFrame(b'\x02\x02\x01\xFF\x01\x02\x03\x04')
test_frame3 = axis_ep.AXIStreamFrame(b'\x02\x03\x00\xFF\x01\x02\x03\x04')
source_0_queue.put(test_frame0)
source_1_queue.put(test_frame1)
source_2_queue.put(test_frame2)
source_3_queue.put(test_frame3)
source_0.send(test_frame0)
source_1.send(test_frame1)
source_2.send(test_frame2)
source_3.send(test_frame3)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
@ -367,27 +337,19 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame0 = None
if not sink_0_queue.empty():
rx_frame0 = sink_0_queue.get()
rx_frame0 = sink_0.recv()
assert rx_frame0 == test_frame3
rx_frame1 = None
if not sink_1_queue.empty():
rx_frame1 = sink_1_queue.get()
rx_frame1 = sink_1.recv()
assert rx_frame1 == test_frame2
rx_frame2 = None
if not sink_2_queue.empty():
rx_frame2 = sink_2_queue.get()
rx_frame2 = sink_2.recv()
assert rx_frame2 == test_frame1
rx_frame3 = None
if not sink_3_queue.empty():
rx_frame3 = sink_3_queue.get()
rx_frame3 = sink_3.recv()
assert rx_frame3 == test_frame0
@ -403,7 +365,7 @@ def bench():
output_3_select.next = 0
test_frame0 = axis_ep.AXIStreamFrame(b'\x03\x00\xFF\xFF\x01\x02\x03\x04')
source_0_queue.put(test_frame0)
source_0.send(test_frame0)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
@ -411,27 +373,19 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame0 = None
if not sink_0_queue.empty():
rx_frame0 = sink_0_queue.get()
rx_frame0 = sink_0.recv()
assert rx_frame0 == test_frame0
rx_frame1 = None
if not sink_1_queue.empty():
rx_frame1 = sink_1_queue.get()
rx_frame1 = sink_1.recv()
assert rx_frame1 == test_frame0
rx_frame2 = None
if not sink_2_queue.empty():
rx_frame2 = sink_2_queue.get()
rx_frame2 = sink_2.recv()
assert rx_frame2 == test_frame0
rx_frame3 = None
if not sink_3_queue.empty():
rx_frame3 = sink_3_queue.get()
rx_frame3 = sink_3.recv()
assert rx_frame3 == test_frame0
@ -439,7 +393,7 @@ def bench():
raise StopSimulation
return dut, source_0, source_1, source_2, source_3, sink_0, sink_1, sink_2, sink_3, clkgen, check
return dut, source_0_logic, source_1_logic, source_2_logic, source_3_logic, sink_0_logic, sink_1_logic, sink_2_logic, sink_3_logic, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))

116
lib/axis/tb/test_axis_crosspoint_4x4.v
View File

@ -24,27 +24,37 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1 ns / 1 ps
`timescale 1ns / 1ps
/*
* Testbench for axis_crosspoint_4x4
*/
module test_axis_crosspoint_4x4;
// Parameters
parameter DATA_WIDTH = 8;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] input_0_axis_tdata = 0;
reg [DATA_WIDTH-1:0] input_0_axis_tdata = 0;
reg input_0_axis_tvalid = 0;
reg input_0_axis_tlast = 0;
reg [7:0] input_1_axis_tdata = 0;
reg input_0_axis_tuser = 0;
reg [DATA_WIDTH-1:0] input_1_axis_tdata = 0;
reg input_1_axis_tvalid = 0;
reg input_1_axis_tlast = 0;
reg [7:0] input_2_axis_tdata = 0;
reg input_1_axis_tuser = 0;
reg [DATA_WIDTH-1:0] input_2_axis_tdata = 0;
reg input_2_axis_tvalid = 0;
reg input_2_axis_tlast = 0;
reg [7:0] input_3_axis_tdata = 0;
reg input_2_axis_tuser = 0;
reg [DATA_WIDTH-1:0] input_3_axis_tdata = 0;
reg input_3_axis_tvalid = 0;
reg input_3_axis_tlast = 0;
reg input_3_axis_tuser = 0;
reg [1:0] output_0_select = 0;
reg [1:0] output_1_select = 0;
@ -52,52 +62,68 @@ reg [1:0] output_2_select = 0;
reg [1:0] output_3_select = 0;
// Outputs
wire [7:0] output_0_axis_tdata;
wire [DATA_WIDTH-1:0] output_0_axis_tdata;
wire output_0_axis_tvalid;
wire output_0_axis_tlast;
wire [7:0] output_1_axis_tdata;
wire output_0_axis_tuser;
wire [DATA_WIDTH-1:0] output_1_axis_tdata;
wire output_1_axis_tvalid;
wire output_1_axis_tlast;
wire [7:0] output_2_axis_tdata;
wire output_1_axis_tuser;
wire [DATA_WIDTH-1:0] output_2_axis_tdata;
wire output_2_axis_tvalid;
wire output_2_axis_tlast;
wire [7:0] output_3_axis_tdata;
wire output_2_axis_tuser;
wire [DATA_WIDTH-1:0] output_3_axis_tdata;
wire output_3_axis_tvalid;
wire output_3_axis_tlast;
wire output_3_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_0_axis_tdata,
input_0_axis_tvalid,
input_0_axis_tlast,
input_1_axis_tdata,
input_1_axis_tvalid,
input_1_axis_tlast,
input_2_axis_tdata,
input_2_axis_tvalid,
input_2_axis_tlast,
input_3_axis_tdata,
input_3_axis_tvalid,
input_3_axis_tlast,
output_0_select,
output_1_select,
output_2_select,
output_3_select);
$to_myhdl(output_0_axis_tdata,
output_0_axis_tvalid,
output_0_axis_tlast,
output_1_axis_tdata,
output_1_axis_tvalid,
output_1_axis_tlast,
output_2_axis_tdata,
output_2_axis_tvalid,
output_2_axis_tlast,
output_3_axis_tdata,
output_3_axis_tvalid,
output_3_axis_tlast);
$from_myhdl(
clk,
rst,
current_test,
input_0_axis_tdata,
input_0_axis_tvalid,
input_0_axis_tlast,
input_0_axis_tuser,
input_1_axis_tdata,
input_1_axis_tvalid,
input_1_axis_tlast,
input_1_axis_tuser,
input_2_axis_tdata,
input_2_axis_tvalid,
input_2_axis_tlast,
input_2_axis_tuser,
input_3_axis_tdata,
input_3_axis_tvalid,
input_3_axis_tlast,
input_3_axis_tuser,
output_0_select,
output_1_select,
output_2_select,
output_3_select
);
$to_myhdl(
output_0_axis_tdata,
output_0_axis_tvalid,
output_0_axis_tlast,
output_0_axis_tuser,
output_1_axis_tdata,
output_1_axis_tvalid,
output_1_axis_tlast,
output_1_axis_tuser,
output_2_axis_tdata,
output_2_axis_tvalid,
output_2_axis_tlast,
output_2_axis_tuser,
output_3_axis_tdata,
output_3_axis_tvalid,
output_3_axis_tlast,
output_3_axis_tuser
);
// dump file
$dumpfile("test_axis_crosspoint_4x4.lxt");
@ -105,7 +131,7 @@ initial begin
end
axis_crosspoint_4x4 #(
.DATA_WIDTH(8)
.DATA_WIDTH(DATA_WIDTH)
)
UUT (
.clk(clk),
@ -114,28 +140,36 @@ UUT (
.input_0_axis_tdata(input_0_axis_tdata),
.input_0_axis_tvalid(input_0_axis_tvalid),
.input_0_axis_tlast(input_0_axis_tlast),
.input_0_axis_tuser(input_0_axis_tuser),
.input_1_axis_tdata(input_1_axis_tdata),
.input_1_axis_tvalid(input_1_axis_tvalid),
.input_1_axis_tlast(input_1_axis_tlast),
.input_1_axis_tuser(input_1_axis_tuser),
.input_2_axis_tdata(input_2_axis_tdata),
.input_2_axis_tvalid(input_2_axis_tvalid),
.input_2_axis_tlast(input_2_axis_tlast),
.input_2_axis_tuser(input_2_axis_tuser),
.input_3_axis_tdata(input_3_axis_tdata),
.input_3_axis_tvalid(input_3_axis_tvalid),
.input_3_axis_tlast(input_3_axis_tlast),
.input_3_axis_tuser(input_3_axis_tuser),
// AXI outputs
.output_0_axis_tdata(output_0_axis_tdata),
.output_0_axis_tvalid(output_0_axis_tvalid),
.output_0_axis_tlast(output_0_axis_tlast),
.output_0_axis_tuser(output_0_axis_tuser),
.output_1_axis_tdata(output_1_axis_tdata),
.output_1_axis_tvalid(output_1_axis_tvalid),
.output_1_axis_tlast(output_1_axis_tlast),
.output_1_axis_tuser(output_1_axis_tuser),
.output_2_axis_tdata(output_2_axis_tdata),
.output_2_axis_tvalid(output_2_axis_tvalid),
.output_2_axis_tlast(output_2_axis_tlast),
.output_2_axis_tuser(output_2_axis_tuser),
.output_3_axis_tdata(output_3_axis_tdata),
.output_3_axis_tvalid(output_3_axis_tvalid),
.output_3_axis_tlast(output_3_axis_tlast),
.output_3_axis_tuser(output_3_axis_tuser),
// Control
.output_0_select(output_0_select),
.output_1_select(output_1_select),

493
lib/axis/tb/test_axis_crosspoint_64_4x4.py
View File

@ -26,136 +26,51 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_crosspoint_64_4x4'
testbench = 'test_%s' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_axis_crosspoint_64_4x4(clk,
rst,
current_test,
input_0_axis_tdata,
input_0_axis_tkeep,
input_0_axis_tvalid,
input_0_axis_tlast,
input_1_axis_tdata,
input_1_axis_tkeep,
input_1_axis_tvalid,
input_1_axis_tlast,
input_2_axis_tdata,
input_2_axis_tkeep,
input_2_axis_tvalid,
input_2_axis_tlast,
input_3_axis_tdata,
input_3_axis_tkeep,
input_3_axis_tvalid,
input_3_axis_tlast,
output_0_axis_tdata,
output_0_axis_tkeep,
output_0_axis_tvalid,
output_0_axis_tlast,
output_1_axis_tdata,
output_1_axis_tkeep,
output_1_axis_tvalid,
output_1_axis_tlast,
output_2_axis_tdata,
output_2_axis_tkeep,
output_2_axis_tvalid,
output_2_axis_tlast,
output_3_axis_tdata,
output_3_axis_tkeep,
output_3_axis_tvalid,
output_3_axis_tlast,
output_0_select,
output_1_select,
output_2_select,
output_3_select):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_0_axis_tdata=input_0_axis_tdata,
input_0_axis_tkeep=input_0_axis_tkeep,
input_0_axis_tvalid=input_0_axis_tvalid,
input_0_axis_tlast=input_0_axis_tlast,
input_1_axis_tdata=input_1_axis_tdata,
input_1_axis_tkeep=input_1_axis_tkeep,
input_1_axis_tvalid=input_1_axis_tvalid,
input_1_axis_tlast=input_1_axis_tlast,
input_2_axis_tdata=input_2_axis_tdata,
input_2_axis_tkeep=input_2_axis_tkeep,
input_2_axis_tvalid=input_2_axis_tvalid,
input_2_axis_tlast=input_2_axis_tlast,
input_3_axis_tdata=input_3_axis_tdata,
input_3_axis_tkeep=input_3_axis_tkeep,
input_3_axis_tvalid=input_3_axis_tvalid,
input_3_axis_tlast=input_3_axis_tlast,
output_0_axis_tdata=output_0_axis_tdata,
output_0_axis_tkeep=output_0_axis_tkeep,
output_0_axis_tvalid=output_0_axis_tvalid,
output_0_axis_tlast=output_0_axis_tlast,
output_1_axis_tdata=output_1_axis_tdata,
output_1_axis_tkeep=output_1_axis_tkeep,
output_1_axis_tvalid=output_1_axis_tvalid,
output_1_axis_tlast=output_1_axis_tlast,
output_2_axis_tdata=output_2_axis_tdata,
output_2_axis_tkeep=output_2_axis_tkeep,
output_2_axis_tvalid=output_2_axis_tvalid,
output_2_axis_tlast=output_2_axis_tlast,
output_3_axis_tdata=output_3_axis_tdata,
output_3_axis_tkeep=output_3_axis_tkeep,
output_3_axis_tvalid=output_3_axis_tvalid,
output_3_axis_tlast=output_3_axis_tlast,
output_0_select=output_0_select,
output_1_select=output_1_select,
output_2_select=output_2_select,
output_3_select=output_3_select)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
DATA_WIDTH = 64
KEEP_WIDTH = (DATA_WIDTH/8)
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_0_axis_tdata = Signal(intbv(0)[64:])
input_0_axis_tkeep = Signal(intbv(0)[8:])
input_0_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_0_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
input_0_axis_tvalid = Signal(bool(0))
input_0_axis_tlast = Signal(bool(0))
input_1_axis_tdata = Signal(intbv(0)[64:])
input_1_axis_tkeep = Signal(intbv(0)[8:])
input_0_axis_tuser = Signal(bool(0))
input_1_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_1_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
input_1_axis_tvalid = Signal(bool(0))
input_1_axis_tlast = Signal(bool(0))
input_2_axis_tdata = Signal(intbv(0)[64:])
input_2_axis_tkeep = Signal(intbv(0)[8:])
input_1_axis_tuser = Signal(bool(0))
input_2_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_2_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
input_2_axis_tvalid = Signal(bool(0))
input_2_axis_tlast = Signal(bool(0))
input_3_axis_tdata = Signal(intbv(0)[64:])
input_3_axis_tkeep = Signal(intbv(0)[8:])
input_2_axis_tuser = Signal(bool(0))
input_3_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_3_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
input_3_axis_tvalid = Signal(bool(0))
input_3_axis_tlast = Signal(bool(0))
input_3_axis_tuser = Signal(bool(0))
output_0_select = Signal(intbv(0)[2:])
output_1_select = Signal(intbv(0)[2:])
@ -163,158 +78,206 @@ def bench():
output_3_select = Signal(intbv(0)[2:])
# Outputs
output_0_axis_tdata = Signal(intbv(0)[64:])
output_0_axis_tkeep = Signal(intbv(0)[8:])
output_0_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_0_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
output_0_axis_tvalid = Signal(bool(0))
output_0_axis_tlast = Signal(bool(0))
output_1_axis_tdata = Signal(intbv(0)[64:])
output_1_axis_tkeep = Signal(intbv(0)[8:])
output_0_axis_tuser = Signal(bool(0))
output_1_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_1_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
output_1_axis_tvalid = Signal(bool(0))
output_1_axis_tlast = Signal(bool(0))
output_2_axis_tdata = Signal(intbv(0)[64:])
output_2_axis_tkeep = Signal(intbv(0)[8:])
output_1_axis_tuser = Signal(bool(0))
output_2_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_2_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
output_2_axis_tvalid = Signal(bool(0))
output_2_axis_tlast = Signal(bool(0))
output_3_axis_tdata = Signal(intbv(0)[64:])
output_3_axis_tkeep = Signal(intbv(0)[8:])
output_2_axis_tuser = Signal(bool(0))
output_3_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_3_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
output_3_axis_tvalid = Signal(bool(0))
output_3_axis_tlast = Signal(bool(0))
output_3_axis_tuser = Signal(bool(0))
# sources and sinks
source_0_queue = Queue()
source_0_pause = Signal(bool(0))
source_1_queue = Queue()
source_1_pause = Signal(bool(0))
source_2_queue = Queue()
source_2_pause = Signal(bool(0))
source_3_queue = Queue()
source_3_pause = Signal(bool(0))
sink_0_queue = Queue()
sink_0_pause = Signal(bool(0))
sink_1_queue = Queue()
sink_1_pause = Signal(bool(0))
sink_2_queue = Queue()
sink_2_pause = Signal(bool(0))
sink_3_queue = Queue()
sink_3_pause = Signal(bool(0))
source_0 = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_0_axis_tdata,
tkeep=input_0_axis_tkeep,
tvalid=input_0_axis_tvalid,
tlast=input_0_axis_tlast,
fifo=source_0_queue,
pause=source_0_pause,
name='source0')
source_1 = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_1_axis_tdata,
tkeep=input_1_axis_tkeep,
tvalid=input_1_axis_tvalid,
tlast=input_1_axis_tlast,
fifo=source_1_queue,
pause=source_1_pause,
name='source1')
source_2 = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_2_axis_tdata,
tkeep=input_2_axis_tkeep,
tvalid=input_2_axis_tvalid,
tlast=input_2_axis_tlast,
fifo=source_2_queue,
pause=source_2_pause,
name='source2')
source_3 = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_3_axis_tdata,
tkeep=input_3_axis_tkeep,
tvalid=input_3_axis_tvalid,
tlast=input_3_axis_tlast,
fifo=source_3_queue,
pause=source_3_pause,
name='source3')
source_0 = axis_ep.AXIStreamSource()
sink_0 = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_0_axis_tdata,
tkeep=output_0_axis_tkeep,
tvalid=output_0_axis_tvalid,
tlast=output_0_axis_tlast,
fifo=sink_0_queue,
pause=sink_0_pause,
name='sink0')
sink_1 = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_1_axis_tdata,
tkeep=output_1_axis_tkeep,
tvalid=output_1_axis_tvalid,
tlast=output_1_axis_tlast,
fifo=sink_1_queue,
pause=sink_1_pause,
name='sink1')
sink_2 = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_2_axis_tdata,
tkeep=output_2_axis_tkeep,
tvalid=output_2_axis_tvalid,
tlast=output_2_axis_tlast,
fifo=sink_2_queue,
pause=sink_2_pause,
name='sink2')
sink_3 = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_3_axis_tdata,
tkeep=output_3_axis_tkeep,
tvalid=output_3_axis_tvalid,
tlast=output_3_axis_tlast,
fifo=sink_3_queue,
pause=sink_3_pause,
name='sink3')
source_0_logic = source_0.create_logic(
clk,
rst,
tdata=input_0_axis_tdata,
tkeep=input_0_axis_tkeep,
tvalid=input_0_axis_tvalid,
tlast=input_0_axis_tlast,
tuser=input_0_axis_tuser,
pause=source_0_pause,
name='source_0'
)
source_1 = axis_ep.AXIStreamSource()
source_1_logic = source_1.create_logic(
clk,
rst,
tdata=input_1_axis_tdata,
tkeep=input_1_axis_tkeep,
tvalid=input_1_axis_tvalid,
tlast=input_1_axis_tlast,
tuser=input_1_axis_tuser,
pause=source_1_pause,
name='source_1'
)
source_2 = axis_ep.AXIStreamSource()
source_2_logic = source_2.create_logic(
clk,
rst,
tdata=input_2_axis_tdata,
tkeep=input_2_axis_tkeep,
tvalid=input_2_axis_tvalid,
tlast=input_2_axis_tlast,
tuser=input_2_axis_tuser,
pause=source_2_pause,
name='source_2'
)
source_3 = axis_ep.AXIStreamSource()
source_3_logic = source_3.create_logic(
clk,
rst,
tdata=input_3_axis_tdata,
tkeep=input_3_axis_tkeep,
tvalid=input_3_axis_tvalid,
tlast=input_3_axis_tlast,
tuser=input_3_axis_tuser,
pause=source_3_pause,
name='source_3'
)
sink_0 = axis_ep.AXIStreamSink()
sink_0_logic = sink_0.create_logic(
clk,
rst,
tdata=output_0_axis_tdata,
tkeep=output_0_axis_tkeep,
tvalid=output_0_axis_tvalid,
tlast=output_0_axis_tlast,
tuser=output_0_axis_tuser,
pause=sink_0_pause,
name='sink_0'
)
sink_1 = axis_ep.AXIStreamSink()
sink_1_logic = sink_1.create_logic(
clk,
rst,
tdata=output_1_axis_tdata,
tkeep=output_1_axis_tkeep,
tvalid=output_1_axis_tvalid,
tlast=output_1_axis_tlast,
tuser=output_1_axis_tuser,
pause=sink_1_pause,
name='sink_1'
)
sink_2 = axis_ep.AXIStreamSink()
sink_2_logic = sink_2.create_logic(
clk,
rst,
tdata=output_2_axis_tdata,
tkeep=output_2_axis_tkeep,
tvalid=output_2_axis_tvalid,
tlast=output_2_axis_tlast,
tuser=output_2_axis_tuser,
pause=sink_2_pause,
name='sink_2'
)
sink_3 = axis_ep.AXIStreamSink()
sink_3_logic = sink_3.create_logic(
clk,
rst,
tdata=output_3_axis_tdata,
tkeep=output_3_axis_tkeep,
tvalid=output_3_axis_tvalid,
tlast=output_3_axis_tlast,
tuser=output_3_axis_tuser,
pause=sink_3_pause,
name='sink_3'
)
# DUT
dut = dut_axis_crosspoint_64_4x4(clk,
rst,
current_test,
if os.system(build_cmd):
raise Exception("Error running build command")
input_0_axis_tdata,
input_0_axis_tkeep,
input_0_axis_tvalid,
input_0_axis_tlast,
input_1_axis_tdata,
input_1_axis_tkeep,
input_1_axis_tvalid,
input_1_axis_tlast,
input_2_axis_tdata,
input_2_axis_tkeep,
input_2_axis_tvalid,
input_2_axis_tlast,
input_3_axis_tdata,
input_3_axis_tkeep,
input_3_axis_tvalid,
input_3_axis_tlast,
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
output_0_axis_tdata,
output_0_axis_tkeep,
output_0_axis_tvalid,
output_0_axis_tlast,
output_1_axis_tdata,
output_1_axis_tkeep,
output_1_axis_tvalid,
output_1_axis_tlast,
output_2_axis_tdata,
output_2_axis_tkeep,
output_2_axis_tvalid,
output_2_axis_tlast,
output_3_axis_tdata,
output_3_axis_tkeep,
output_3_axis_tvalid,
output_3_axis_tlast,
input_0_axis_tdata=input_0_axis_tdata,
input_0_axis_tkeep=input_0_axis_tkeep,
input_0_axis_tvalid=input_0_axis_tvalid,
input_0_axis_tlast=input_0_axis_tlast,
input_0_axis_tuser=input_0_axis_tuser,
input_1_axis_tdata=input_1_axis_tdata,
input_1_axis_tkeep=input_1_axis_tkeep,
input_1_axis_tvalid=input_1_axis_tvalid,
input_1_axis_tlast=input_1_axis_tlast,
input_1_axis_tuser=input_1_axis_tuser,
input_2_axis_tdata=input_2_axis_tdata,
input_2_axis_tkeep=input_2_axis_tkeep,
input_2_axis_tvalid=input_2_axis_tvalid,
input_2_axis_tlast=input_2_axis_tlast,
input_2_axis_tuser=input_2_axis_tuser,
input_3_axis_tdata=input_3_axis_tdata,
input_3_axis_tkeep=input_3_axis_tkeep,
input_3_axis_tvalid=input_3_axis_tvalid,
input_3_axis_tlast=input_3_axis_tlast,
input_3_axis_tuser=input_3_axis_tuser,
output_0_select,
output_1_select,
output_2_select,
output_3_select)
output_0_axis_tdata=output_0_axis_tdata,
output_0_axis_tkeep=output_0_axis_tkeep,
output_0_axis_tvalid=output_0_axis_tvalid,
output_0_axis_tlast=output_0_axis_tlast,
output_0_axis_tuser=output_0_axis_tuser,
output_1_axis_tdata=output_1_axis_tdata,
output_1_axis_tkeep=output_1_axis_tkeep,
output_1_axis_tvalid=output_1_axis_tvalid,
output_1_axis_tlast=output_1_axis_tlast,
output_1_axis_tuser=output_1_axis_tuser,
output_2_axis_tdata=output_2_axis_tdata,
output_2_axis_tkeep=output_2_axis_tkeep,
output_2_axis_tvalid=output_2_axis_tvalid,
output_2_axis_tlast=output_2_axis_tlast,
output_2_axis_tuser=output_2_axis_tuser,
output_3_axis_tdata=output_3_axis_tdata,
output_3_axis_tkeep=output_3_axis_tkeep,
output_3_axis_tvalid=output_3_axis_tvalid,
output_3_axis_tlast=output_3_axis_tlast,
output_3_axis_tuser=output_3_axis_tuser,
output_0_select=output_0_select,
output_1_select=output_1_select,
output_2_select=output_2_select,
output_3_select=output_3_select
)
@always(delay(4))
def clkgen():
@ -346,10 +309,10 @@ def bench():
test_frame1 = axis_ep.AXIStreamFrame(b'\x01\x01\x01\xFF\x01\x02\x03\x04')
test_frame2 = axis_ep.AXIStreamFrame(b'\x01\x02\x02\xFF\x01\x02\x03\x04')
test_frame3 = axis_ep.AXIStreamFrame(b'\x01\x03\x03\xFF\x01\x02\x03\x04')
source_0_queue.put(test_frame0)
source_1_queue.put(test_frame1)
source_2_queue.put(test_frame2)
source_3_queue.put(test_frame3)
source_0.send(test_frame0)
source_1.send(test_frame1)
source_2.send(test_frame2)
source_3.send(test_frame3)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
@ -357,27 +320,19 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame0 = None
if not sink_0_queue.empty():
rx_frame0 = sink_0_queue.get()
rx_frame0 = sink_0.recv()
assert rx_frame0 == test_frame0
rx_frame1 = None
if not sink_1_queue.empty():
rx_frame1 = sink_1_queue.get()
rx_frame1 = sink_1.recv()
assert rx_frame1 == test_frame1
rx_frame2 = None
if not sink_2_queue.empty():
rx_frame2 = sink_2_queue.get()
rx_frame2 = sink_2.recv()
assert rx_frame2 == test_frame2
rx_frame3 = None
if not sink_3_queue.empty():
rx_frame3 = sink_3_queue.get()
rx_frame3 = sink_3.recv()
assert rx_frame3 == test_frame3
@ -396,10 +351,10 @@ def bench():
test_frame1 = axis_ep.AXIStreamFrame(b'\x02\x01\x02\xFF\x01\x02\x03\x04')
test_frame2 = axis_ep.AXIStreamFrame(b'\x02\x02\x01\xFF\x01\x02\x03\x04')
test_frame3 = axis_ep.AXIStreamFrame(b'\x02\x03\x00\xFF\x01\x02\x03\x04')
source_0_queue.put(test_frame0)
source_1_queue.put(test_frame1)
source_2_queue.put(test_frame2)
source_3_queue.put(test_frame3)
source_0.send(test_frame0)
source_1.send(test_frame1)
source_2.send(test_frame2)
source_3.send(test_frame3)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
@ -407,27 +362,19 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame0 = None
if not sink_0_queue.empty():
rx_frame0 = sink_0_queue.get()
rx_frame0 = sink_0.recv()
assert rx_frame0 == test_frame3
rx_frame1 = None
if not sink_1_queue.empty():
rx_frame1 = sink_1_queue.get()
rx_frame1 = sink_1.recv()
assert rx_frame1 == test_frame2
rx_frame2 = None
if not sink_2_queue.empty():
rx_frame2 = sink_2_queue.get()
rx_frame2 = sink_2.recv()
assert rx_frame2 == test_frame1
rx_frame3 = None
if not sink_3_queue.empty():
rx_frame3 = sink_3_queue.get()
rx_frame3 = sink_3.recv()
assert rx_frame3 == test_frame0
@ -443,7 +390,7 @@ def bench():
output_3_select.next = 0
test_frame0 = axis_ep.AXIStreamFrame(b'\x03\x00\xFF\xFF\x01\x02\x03\x04')
source_0_queue.put(test_frame0)
source_0.send(test_frame0)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
@ -451,27 +398,19 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame0 = None
if not sink_0_queue.empty():
rx_frame0 = sink_0_queue.get()
rx_frame0 = sink_0.recv()
assert rx_frame0 == test_frame0
rx_frame1 = None
if not sink_1_queue.empty():
rx_frame1 = sink_1_queue.get()
rx_frame1 = sink_1.recv()
assert rx_frame1 == test_frame0
rx_frame2 = None
if not sink_2_queue.empty():
rx_frame2 = sink_2_queue.get()
rx_frame2 = sink_2.recv()
assert rx_frame2 == test_frame0
rx_frame3 = None
if not sink_3_queue.empty():
rx_frame3 = sink_3_queue.get()
rx_frame3 = sink_3.recv()
assert rx_frame3 == test_frame0
@ -479,7 +418,7 @@ def bench():
raise StopSimulation
return dut, source_0, source_1, source_2, source_3, sink_0, sink_1, sink_2, sink_3, clkgen, check
return dut, source_0_logic, source_1_logic, source_2_logic, source_3_logic, sink_0_logic, sink_1_logic, sink_2_logic, sink_3_logic, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))

150
lib/axis/tb/test_axis_crosspoint_64_4x4.v
View File

@ -24,31 +24,42 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1 ns / 1 ps
`timescale 1ns / 1ps
/*
* Testbench for axis_crosspoint_64_4x4
*/
module test_axis_crosspoint_64_4x4;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_WIDTH = (DATA_WIDTH/8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [63:0] input_0_axis_tdata = 0;
reg [7:0] input_0_axis_tkeep = 0;
reg [DATA_WIDTH-1:0] input_0_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_0_axis_tkeep = 0;
reg input_0_axis_tvalid = 0;
reg input_0_axis_tlast = 0;
reg [63:0] input_1_axis_tdata = 0;
reg [7:0] input_1_axis_tkeep = 0;
reg input_0_axis_tuser = 0;
reg [DATA_WIDTH-1:0] input_1_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_1_axis_tkeep = 0;
reg input_1_axis_tvalid = 0;
reg input_1_axis_tlast = 0;
reg [63:0] input_2_axis_tdata = 0;
reg [7:0] input_2_axis_tkeep = 0;
reg input_1_axis_tuser = 0;
reg [DATA_WIDTH-1:0] input_2_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_2_axis_tkeep = 0;
reg input_2_axis_tvalid = 0;
reg input_2_axis_tlast = 0;
reg [63:0] input_3_axis_tdata = 0;
reg [7:0] input_3_axis_tkeep = 0;
reg input_2_axis_tuser = 0;
reg [DATA_WIDTH-1:0] input_3_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_3_axis_tkeep = 0;
reg input_3_axis_tvalid = 0;
reg input_3_axis_tlast = 0;
reg input_3_axis_tuser = 0;
reg [1:0] output_0_select = 0;
reg [1:0] output_1_select = 0;
@ -56,64 +67,80 @@ reg [1:0] output_2_select = 0;
reg [1:0] output_3_select = 0;
// Outputs
wire [63:0] output_0_axis_tdata;
wire [7:0] output_0_axis_tkeep;
wire [DATA_WIDTH-1:0] output_0_axis_tdata;
wire [KEEP_WIDTH-1:0] output_0_axis_tkeep;
wire output_0_axis_tvalid;
wire output_0_axis_tlast;
wire [63:0] output_1_axis_tdata;
wire [7:0] output_1_axis_tkeep;
wire output_0_axis_tuser;
wire [DATA_WIDTH-1:0] output_1_axis_tdata;
wire [KEEP_WIDTH-1:0] output_1_axis_tkeep;
wire output_1_axis_tvalid;
wire output_1_axis_tlast;
wire [63:0] output_2_axis_tdata;
wire [7:0] output_2_axis_tkeep;
wire output_1_axis_tuser;
wire [DATA_WIDTH-1:0] output_2_axis_tdata;
wire [KEEP_WIDTH-1:0] output_2_axis_tkeep;
wire output_2_axis_tvalid;
wire output_2_axis_tlast;
wire [63:0] output_3_axis_tdata;
wire [7:0] output_3_axis_tkeep;
wire output_2_axis_tuser;
wire [DATA_WIDTH-1:0] output_3_axis_tdata;
wire [KEEP_WIDTH-1:0] output_3_axis_tkeep;
wire output_3_axis_tvalid;
wire output_3_axis_tlast;
wire output_3_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_0_axis_tdata,
input_0_axis_tkeep,
input_0_axis_tvalid,
input_0_axis_tlast,
input_1_axis_tdata,
input_1_axis_tkeep,
input_1_axis_tvalid,
input_1_axis_tlast,
input_2_axis_tdata,
input_2_axis_tkeep,
input_2_axis_tvalid,
input_2_axis_tlast,
input_3_axis_tdata,
input_3_axis_tkeep,
input_3_axis_tvalid,
input_3_axis_tlast,
output_0_select,
output_1_select,
output_2_select,
output_3_select);
$to_myhdl(output_0_axis_tdata,
output_0_axis_tkeep,
output_0_axis_tvalid,
output_0_axis_tlast,
output_1_axis_tdata,
output_1_axis_tkeep,
output_1_axis_tvalid,
output_1_axis_tlast,
output_2_axis_tdata,
output_2_axis_tkeep,
output_2_axis_tvalid,
output_2_axis_tlast,
output_3_axis_tdata,
output_3_axis_tkeep,
output_3_axis_tvalid,
output_3_axis_tlast);
$from_myhdl(
clk,
rst,
current_test,
input_0_axis_tdata,
input_0_axis_tkeep,
input_0_axis_tvalid,
input_0_axis_tlast,
input_0_axis_tuser,
input_1_axis_tdata,
input_1_axis_tkeep,
input_1_axis_tvalid,
input_1_axis_tlast,
input_1_axis_tuser,
input_2_axis_tdata,
input_2_axis_tkeep,
input_2_axis_tvalid,
input_2_axis_tlast,
input_2_axis_tuser,
input_3_axis_tdata,
input_3_axis_tkeep,
input_3_axis_tvalid,
input_3_axis_tlast,
input_3_axis_tuser,
output_0_select,
output_1_select,
output_2_select,
output_3_select
);
$to_myhdl(
output_0_axis_tdata,
output_0_axis_tkeep,
output_0_axis_tvalid,
output_0_axis_tlast,
output_0_axis_tuser,
output_1_axis_tdata,
output_1_axis_tkeep,
output_1_axis_tvalid,
output_1_axis_tlast,
output_1_axis_tuser,
output_2_axis_tdata,
output_2_axis_tkeep,
output_2_axis_tvalid,
output_2_axis_tlast,
output_2_axis_tuser,
output_3_axis_tdata,
output_3_axis_tkeep,
output_3_axis_tvalid,
output_3_axis_tlast,
output_3_axis_tuser
);
// dump file
$dumpfile("test_axis_crosspoint_64_4x4.lxt");
@ -121,7 +148,8 @@ initial begin
end
axis_crosspoint_64_4x4 #(
.DATA_WIDTH(64)
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH)
)
UUT (
.clk(clk),
@ -131,35 +159,43 @@ UUT (
.input_0_axis_tkeep(input_0_axis_tkeep),
.input_0_axis_tvalid(input_0_axis_tvalid),
.input_0_axis_tlast(input_0_axis_tlast),
.input_0_axis_tuser(input_0_axis_tuser),
.input_1_axis_tdata(input_1_axis_tdata),
.input_1_axis_tkeep(input_1_axis_tkeep),
.input_1_axis_tvalid(input_1_axis_tvalid),
.input_1_axis_tlast(input_1_axis_tlast),
.input_1_axis_tuser(input_1_axis_tuser),
.input_2_axis_tdata(input_2_axis_tdata),
.input_2_axis_tkeep(input_2_axis_tkeep),
.input_2_axis_tvalid(input_2_axis_tvalid),
.input_2_axis_tlast(input_2_axis_tlast),
.input_2_axis_tuser(input_2_axis_tuser),
.input_3_axis_tdata(input_3_axis_tdata),
.input_3_axis_tkeep(input_3_axis_tkeep),
.input_3_axis_tvalid(input_3_axis_tvalid),
.input_3_axis_tlast(input_3_axis_tlast),
.input_3_axis_tuser(input_3_axis_tuser),
// AXI outputs
.output_0_axis_tdata(output_0_axis_tdata),
.output_0_axis_tkeep(output_0_axis_tkeep),
.output_0_axis_tvalid(output_0_axis_tvalid),
.output_0_axis_tlast(output_0_axis_tlast),
.output_0_axis_tuser(output_0_axis_tuser),
.output_1_axis_tdata(output_1_axis_tdata),
.output_1_axis_tkeep(output_1_axis_tkeep),
.output_1_axis_tvalid(output_1_axis_tvalid),
.output_1_axis_tlast(output_1_axis_tlast),
.output_1_axis_tuser(output_1_axis_tuser),
.output_2_axis_tdata(output_2_axis_tdata),
.output_2_axis_tkeep(output_2_axis_tkeep),
.output_2_axis_tvalid(output_2_axis_tvalid),
.output_2_axis_tlast(output_2_axis_tlast),
.output_2_axis_tuser(output_2_axis_tuser),
.output_3_axis_tdata(output_3_axis_tdata),
.output_3_axis_tkeep(output_3_axis_tkeep),
.output_3_axis_tvalid(output_3_axis_tvalid),
.output_3_axis_tlast(output_3_axis_tlast),
.output_3_axis_tuser(output_3_axis_tuser),
// Control
.output_0_select(output_0_select),
.output_1_select(output_1_select),

344
lib/axis/tb/test_axis_demux_4.py
View File

@ -26,107 +26,35 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_demux_4'
testbench = 'test_%s' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_axis_demux_4(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_0_axis_tdata,
output_0_axis_tvalid,
output_0_axis_tready,
output_0_axis_tlast,
output_0_axis_tuser,
output_1_axis_tdata,
output_1_axis_tvalid,
output_1_axis_tready,
output_1_axis_tlast,
output_1_axis_tuser,
output_2_axis_tdata,
output_2_axis_tvalid,
output_2_axis_tready,
output_2_axis_tlast,
output_2_axis_tuser,
output_3_axis_tdata,
output_3_axis_tvalid,
output_3_axis_tready,
output_3_axis_tlast,
output_3_axis_tuser,
enable,
select):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_0_axis_tdata=output_0_axis_tdata,
output_0_axis_tvalid=output_0_axis_tvalid,
output_0_axis_tready=output_0_axis_tready,
output_0_axis_tlast=output_0_axis_tlast,
output_0_axis_tuser=output_0_axis_tuser,
output_1_axis_tdata=output_1_axis_tdata,
output_1_axis_tvalid=output_1_axis_tvalid,
output_1_axis_tready=output_1_axis_tready,
output_1_axis_tlast=output_1_axis_tlast,
output_1_axis_tuser=output_1_axis_tuser,
output_2_axis_tdata=output_2_axis_tdata,
output_2_axis_tvalid=output_2_axis_tvalid,
output_2_axis_tready=output_2_axis_tready,
output_2_axis_tlast=output_2_axis_tlast,
output_2_axis_tuser=output_2_axis_tuser,
output_3_axis_tdata=output_3_axis_tdata,
output_3_axis_tvalid=output_3_axis_tvalid,
output_3_axis_tready=output_3_axis_tready,
output_3_axis_tlast=output_3_axis_tlast,
output_3_axis_tuser=output_3_axis_tuser,
enable=enable,
select=select)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
DATA_WIDTH = 8
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
output_0_axis_tready = Signal(bool(0))
output_1_axis_tready = Signal(bool(0))
output_2_axis_tready = Signal(bool(0))
@ -138,124 +66,140 @@ def bench():
# Outputs
input_axis_tready = Signal(bool(0))
output_0_axis_tdata = Signal(intbv(0)[8:])
output_0_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_0_axis_tvalid = Signal(bool(0))
output_0_axis_tlast = Signal(bool(0))
output_0_axis_tuser = Signal(bool(0))
output_1_axis_tdata = Signal(intbv(0)[8:])
output_1_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_1_axis_tvalid = Signal(bool(0))
output_1_axis_tlast = Signal(bool(0))
output_1_axis_tuser = Signal(bool(0))
output_2_axis_tdata = Signal(intbv(0)[8:])
output_2_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_2_axis_tvalid = Signal(bool(0))
output_2_axis_tlast = Signal(bool(0))
output_2_axis_tuser = Signal(bool(0))
output_3_axis_tdata = Signal(intbv(0)[8:])
output_3_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_3_axis_tvalid = Signal(bool(0))
output_3_axis_tlast = Signal(bool(0))
output_3_axis_tuser = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_0_queue = Queue()
sink_0_pause = Signal(bool(0))
sink_1_queue = Queue()
sink_1_pause = Signal(bool(0))
sink_2_queue = Queue()
sink_2_pause = Signal(bool(0))
sink_3_queue = Queue()
sink_3_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_axis_tdata,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
source = axis_ep.AXIStreamSource()
sink_0 = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_0_axis_tdata,
tvalid=output_0_axis_tvalid,
tready=output_0_axis_tready,
tlast=output_0_axis_tlast,
tuser=output_0_axis_tuser,
fifo=sink_0_queue,
pause=sink_0_pause,
name='sink0')
source_logic = source.create_logic(
clk,
rst,
tdata=input_axis_tdata,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
pause=source_pause,
name='source'
)
sink_1 = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_1_axis_tdata,
tvalid=output_1_axis_tvalid,
tready=output_1_axis_tready,
tlast=output_1_axis_tlast,
tuser=output_1_axis_tuser,
fifo=sink_1_queue,
pause=sink_1_pause,
name='sink1')
sink_0 = axis_ep.AXIStreamSink()
sink_2 = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_2_axis_tdata,
tvalid=output_2_axis_tvalid,
tready=output_2_axis_tready,
tlast=output_2_axis_tlast,
tuser=output_2_axis_tuser,
fifo=sink_2_queue,
pause=sink_2_pause,
name='sink2')
sink_0_logic = sink_0.create_logic(
clk,
rst,
tdata=output_0_axis_tdata,
tvalid=output_0_axis_tvalid,
tready=output_0_axis_tready,
tlast=output_0_axis_tlast,
tuser=output_0_axis_tuser,
pause=sink_0_pause,
name='sink_0'
)
sink_3 = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_3_axis_tdata,
tvalid=output_3_axis_tvalid,
tready=output_3_axis_tready,
tlast=output_3_axis_tlast,
tuser=output_3_axis_tuser,
fifo=sink_3_queue,
pause=sink_3_pause,
name='sink3')
sink_1 = axis_ep.AXIStreamSink()
sink_1_logic = sink_1.create_logic(
clk,
rst,
tdata=output_1_axis_tdata,
tvalid=output_1_axis_tvalid,
tready=output_1_axis_tready,
tlast=output_1_axis_tlast,
tuser=output_1_axis_tuser,
pause=sink_1_pause,
name='sink_1'
)
sink_2 = axis_ep.AXIStreamSink()
sink_2_logic = sink_2.create_logic(
clk,
rst,
tdata=output_2_axis_tdata,
tvalid=output_2_axis_tvalid,
tready=output_2_axis_tready,
tlast=output_2_axis_tlast,
tuser=output_2_axis_tuser,
pause=sink_2_pause,
name='sink_2'
)
sink_3 = axis_ep.AXIStreamSink()
sink_3_logic = sink_3.create_logic(
clk,
rst,
tdata=output_3_axis_tdata,
tvalid=output_3_axis_tvalid,
tready=output_3_axis_tready,
tlast=output_3_axis_tlast,
tuser=output_3_axis_tuser,
pause=sink_3_pause,
name='sink_3'
)
# DUT
dut = dut_axis_demux_4(clk,
rst,
current_test,
if os.system(build_cmd):
raise Exception("Error running build command")
input_axis_tdata,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
output_0_axis_tdata,
output_0_axis_tvalid,
output_0_axis_tready,
output_0_axis_tlast,
output_0_axis_tuser,
output_1_axis_tdata,
output_1_axis_tvalid,
output_1_axis_tready,
output_1_axis_tlast,
output_1_axis_tuser,
output_2_axis_tdata,
output_2_axis_tvalid,
output_2_axis_tready,
output_2_axis_tlast,
output_2_axis_tuser,
output_3_axis_tdata,
output_3_axis_tvalid,
output_3_axis_tready,
output_3_axis_tlast,
output_3_axis_tuser,
input_axis_tdata=input_axis_tdata,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
enable,
select)
output_0_axis_tdata=output_0_axis_tdata,
output_0_axis_tvalid=output_0_axis_tvalid,
output_0_axis_tready=output_0_axis_tready,
output_0_axis_tlast=output_0_axis_tlast,
output_0_axis_tuser=output_0_axis_tuser,
output_1_axis_tdata=output_1_axis_tdata,
output_1_axis_tvalid=output_1_axis_tvalid,
output_1_axis_tready=output_1_axis_tready,
output_1_axis_tlast=output_1_axis_tlast,
output_1_axis_tuser=output_1_axis_tuser,
output_2_axis_tdata=output_2_axis_tdata,
output_2_axis_tvalid=output_2_axis_tvalid,
output_2_axis_tready=output_2_axis_tready,
output_2_axis_tlast=output_2_axis_tlast,
output_2_axis_tuser=output_2_axis_tuser,
output_3_axis_tdata=output_3_axis_tdata,
output_3_axis_tvalid=output_3_axis_tvalid,
output_3_axis_tready=output_3_axis_tready,
output_3_axis_tlast=output_3_axis_tlast,
output_3_axis_tuser=output_3_axis_tuser,
enable=enable,
select=select
)
@always(delay(4))
def clkgen():
@ -285,7 +229,7 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
while input_axis_tvalid:
@ -293,9 +237,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_0_queue.empty():
rx_frame = sink_0_queue.get()
rx_frame = sink_0.recv()
assert rx_frame == test_frame
@ -311,7 +253,7 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
while input_axis_tvalid:
@ -319,9 +261,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_1_queue.empty():
rx_frame = sink_1_queue.get()
rx_frame = sink_1.recv()
assert rx_frame == test_frame
@ -341,8 +281,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid:
@ -350,15 +290,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_0_queue.empty():
rx_frame = sink_0_queue.get()
rx_frame = sink_0.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_0_queue.empty():
rx_frame = sink_0_queue.get()
rx_frame = sink_0.recv()
assert rx_frame == test_frame2
@ -378,8 +314,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid:
@ -388,15 +324,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_2_queue.empty():
rx_frame = sink_1_queue.get()
rx_frame = sink_1.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_2_queue.empty():
rx_frame = sink_2_queue.get()
rx_frame = sink_2.recv()
assert rx_frame == test_frame2
@ -416,8 +348,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid:
@ -431,15 +363,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_1_queue.empty():
rx_frame = sink_1_queue.get()
rx_frame = sink_1.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_2_queue.empty():
rx_frame = sink_2_queue.get()
rx_frame = sink_2.recv()
assert rx_frame == test_frame2
@ -459,8 +387,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid:
@ -480,15 +408,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_1_queue.empty():
rx_frame = sink_1_queue.get()
rx_frame = sink_1.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_2_queue.empty():
rx_frame = sink_2_queue.get()
rx_frame = sink_2.recv()
assert rx_frame == test_frame2
@ -496,7 +420,7 @@ def bench():
raise StopSimulation
return dut, source, sink_0, sink_1, sink_2, sink_3, clkgen, check
return dut, source_logic, sink_0_logic, sink_1_logic, sink_2_logic, sink_3_logic, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))

84
lib/axis/tb/test_axis_demux_4.v
View File

@ -24,16 +24,22 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1 ns / 1 ps
`timescale 1ns / 1ps
/*
* Testbench for axis_demux_4
*/
module test_axis_demux_4;
// Parameters
parameter DATA_WIDTH = 8;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] input_axis_tdata = 0;
reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
@ -49,55 +55,59 @@ reg [1:0] select = 0;
// Outputs
wire input_axis_tready;
wire [7:0] output_0_axis_tdata;
wire [DATA_WIDTH-1:0] output_0_axis_tdata;
wire output_0_axis_tvalid;
wire output_0_axis_tlast;
wire output_0_axis_tuser;
wire [7:0] output_1_axis_tdata;
wire [DATA_WIDTH-1:0] output_1_axis_tdata;
wire output_1_axis_tvalid;
wire output_1_axis_tlast;
wire output_1_axis_tuser;
wire [7:0] output_2_axis_tdata;
wire [DATA_WIDTH-1:0] output_2_axis_tdata;
wire output_2_axis_tvalid;
wire output_2_axis_tlast;
wire output_2_axis_tuser;
wire [7:0] output_3_axis_tdata;
wire [DATA_WIDTH-1:0] output_3_axis_tdata;
wire output_3_axis_tvalid;
wire output_3_axis_tlast;
wire output_3_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_0_axis_tready,
output_1_axis_tready,
output_2_axis_tready,
output_3_axis_tready,
enable,
select);
$to_myhdl(input_axis_tready,
output_0_axis_tdata,
output_0_axis_tvalid,
output_0_axis_tlast,
output_0_axis_tuser,
output_1_axis_tdata,
output_1_axis_tvalid,
output_1_axis_tlast,
output_1_axis_tuser,
output_2_axis_tdata,
output_2_axis_tvalid,
output_2_axis_tlast,
output_2_axis_tuser,
output_3_axis_tdata,
output_3_axis_tvalid,
output_3_axis_tlast,
output_3_axis_tuser);
$from_myhdl(
clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_0_axis_tready,
output_1_axis_tready,
output_2_axis_tready,
output_3_axis_tready,
enable,
select
);
$to_myhdl(
input_axis_tready,
output_0_axis_tdata,
output_0_axis_tvalid,
output_0_axis_tlast,
output_0_axis_tuser,
output_1_axis_tdata,
output_1_axis_tvalid,
output_1_axis_tlast,
output_1_axis_tuser,
output_2_axis_tdata,
output_2_axis_tvalid,
output_2_axis_tlast,
output_2_axis_tuser,
output_3_axis_tdata,
output_3_axis_tvalid,
output_3_axis_tlast,
output_3_axis_tuser
);
// dump file
$dumpfile("test_axis_demux_4.lxt");
@ -105,7 +115,7 @@ initial begin
end
axis_demux_4 #(
.DATA_WIDTH(8)
.DATA_WIDTH(DATA_WIDTH)
)
UUT (
.clk(clk),

385
lib/axis/tb/test_axis_demux_64_4.py
View File

@ -26,118 +26,37 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_demux_64_4'
testbench = 'test_%s' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_axis_demux_64_4(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_0_axis_tdata,
output_0_axis_tkeep,
output_0_axis_tvalid,
output_0_axis_tready,
output_0_axis_tlast,
output_0_axis_tuser,
output_1_axis_tdata,
output_1_axis_tkeep,
output_1_axis_tvalid,
output_1_axis_tready,
output_1_axis_tlast,
output_1_axis_tuser,
output_2_axis_tdata,
output_2_axis_tkeep,
output_2_axis_tvalid,
output_2_axis_tready,
output_2_axis_tlast,
output_2_axis_tuser,
output_3_axis_tdata,
output_3_axis_tkeep,
output_3_axis_tvalid,
output_3_axis_tready,
output_3_axis_tlast,
output_3_axis_tuser,
enable,
select):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_0_axis_tdata=output_0_axis_tdata,
output_0_axis_tkeep=output_0_axis_tkeep,
output_0_axis_tvalid=output_0_axis_tvalid,
output_0_axis_tready=output_0_axis_tready,
output_0_axis_tlast=output_0_axis_tlast,
output_0_axis_tuser=output_0_axis_tuser,
output_1_axis_tdata=output_1_axis_tdata,
output_1_axis_tkeep=output_1_axis_tkeep,
output_1_axis_tvalid=output_1_axis_tvalid,
output_1_axis_tready=output_1_axis_tready,
output_1_axis_tlast=output_1_axis_tlast,
output_1_axis_tuser=output_1_axis_tuser,
output_2_axis_tdata=output_2_axis_tdata,
output_2_axis_tkeep=output_2_axis_tkeep,
output_2_axis_tvalid=output_2_axis_tvalid,
output_2_axis_tready=output_2_axis_tready,
output_2_axis_tlast=output_2_axis_tlast,
output_2_axis_tuser=output_2_axis_tuser,
output_3_axis_tdata=output_3_axis_tdata,
output_3_axis_tkeep=output_3_axis_tkeep,
output_3_axis_tvalid=output_3_axis_tvalid,
output_3_axis_tready=output_3_axis_tready,
output_3_axis_tlast=output_3_axis_tlast,
output_3_axis_tuser=output_3_axis_tuser,
enable=enable,
select=select)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
DATA_WIDTH = 64
KEEP_WIDTH = (DATA_WIDTH/8)
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[64:])
input_axis_tkeep = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
output_0_axis_tready = Signal(bool(0))
output_1_axis_tready = Signal(bool(0))
output_2_axis_tready = Signal(bool(0))
@ -149,138 +68,154 @@ def bench():
# Outputs
input_axis_tready = Signal(bool(0))
output_0_axis_tdata = Signal(intbv(0)[64:])
output_0_axis_tkeep = Signal(intbv(0)[8:])
output_0_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_0_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
output_0_axis_tvalid = Signal(bool(0))
output_0_axis_tlast = Signal(bool(0))
output_0_axis_tuser = Signal(bool(0))
output_1_axis_tdata = Signal(intbv(0)[64:])
output_1_axis_tkeep = Signal(intbv(0)[8:])
output_1_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_1_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
output_1_axis_tvalid = Signal(bool(0))
output_1_axis_tlast = Signal(bool(0))
output_1_axis_tuser = Signal(bool(0))
output_2_axis_tdata = Signal(intbv(0)[64:])
output_2_axis_tkeep = Signal(intbv(0)[8:])
output_2_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_2_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
output_2_axis_tvalid = Signal(bool(0))
output_2_axis_tlast = Signal(bool(0))
output_2_axis_tuser = Signal(bool(0))
output_3_axis_tdata = Signal(intbv(0)[64:])
output_3_axis_tkeep = Signal(intbv(0)[8:])
output_3_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_3_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
output_3_axis_tvalid = Signal(bool(0))
output_3_axis_tlast = Signal(bool(0))
output_3_axis_tuser = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_0_queue = Queue()
sink_0_pause = Signal(bool(0))
sink_1_queue = Queue()
sink_1_pause = Signal(bool(0))
sink_2_queue = Queue()
sink_2_pause = Signal(bool(0))
sink_3_queue = Queue()
sink_3_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
source = axis_ep.AXIStreamSource()
sink_0 = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_0_axis_tdata,
tkeep=output_0_axis_tkeep,
tvalid=output_0_axis_tvalid,
tready=output_0_axis_tready,
tlast=output_0_axis_tlast,
tuser=output_0_axis_tuser,
fifo=sink_0_queue,
pause=sink_0_pause,
name='sink0')
source_logic = source.create_logic(
clk,
rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
pause=source_pause,
name='source'
)
sink_1 = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_1_axis_tdata,
tkeep=output_1_axis_tkeep,
tvalid=output_1_axis_tvalid,
tready=output_1_axis_tready,
tlast=output_1_axis_tlast,
tuser=output_1_axis_tuser,
fifo=sink_1_queue,
pause=sink_1_pause,
name='sink1')
sink_0 = axis_ep.AXIStreamSink()
sink_2 = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_2_axis_tdata,
tkeep=output_2_axis_tkeep,
tvalid=output_2_axis_tvalid,
tready=output_2_axis_tready,
tlast=output_2_axis_tlast,
tuser=output_2_axis_tuser,
fifo=sink_2_queue,
pause=sink_2_pause,
name='sink2')
sink_0_logic = sink_0.create_logic(
clk,
rst,
tdata=output_0_axis_tdata,
tkeep=output_0_axis_tkeep,
tvalid=output_0_axis_tvalid,
tready=output_0_axis_tready,
tlast=output_0_axis_tlast,
tuser=output_0_axis_tuser,
pause=sink_0_pause,
name='sink_0'
)
sink_3 = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_3_axis_tdata,
tkeep=output_3_axis_tkeep,
tvalid=output_3_axis_tvalid,
tready=output_3_axis_tready,
tlast=output_3_axis_tlast,
tuser=output_3_axis_tuser,
fifo=sink_3_queue,
pause=sink_3_pause,
name='sink3')
sink_1 = axis_ep.AXIStreamSink()
sink_1_logic = sink_1.create_logic(
clk,
rst,
tdata=output_1_axis_tdata,
tkeep=output_1_axis_tkeep,
tvalid=output_1_axis_tvalid,
tready=output_1_axis_tready,
tlast=output_1_axis_tlast,
tuser=output_1_axis_tuser,
pause=sink_1_pause,
name='sink_1'
)
sink_2 = axis_ep.AXIStreamSink()
sink_2_logic = sink_2.create_logic(
clk,
rst,
tdata=output_2_axis_tdata,
tkeep=output_2_axis_tkeep,
tvalid=output_2_axis_tvalid,
tready=output_2_axis_tready,
tlast=output_2_axis_tlast,
tuser=output_2_axis_tuser,
pause=sink_2_pause,
name='sink_2'
)
sink_3 = axis_ep.AXIStreamSink()
sink_3_logic = sink_3.create_logic(
clk,
rst,
tdata=output_3_axis_tdata,
tkeep=output_3_axis_tkeep,
tvalid=output_3_axis_tvalid,
tready=output_3_axis_tready,
tlast=output_3_axis_tlast,
tuser=output_3_axis_tuser,
pause=sink_3_pause,
name='sink_3'
)
# DUT
dut = dut_axis_demux_64_4(clk,
rst,
current_test,
if os.system(build_cmd):
raise Exception("Error running build command")
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
output_0_axis_tdata,
output_0_axis_tkeep,
output_0_axis_tvalid,
output_0_axis_tready,
output_0_axis_tlast,
output_0_axis_tuser,
output_1_axis_tdata,
output_1_axis_tkeep,
output_1_axis_tvalid,
output_1_axis_tready,
output_1_axis_tlast,
output_1_axis_tuser,
output_2_axis_tdata,
output_2_axis_tkeep,
output_2_axis_tvalid,
output_2_axis_tready,
output_2_axis_tlast,
output_2_axis_tuser,
output_3_axis_tdata,
output_3_axis_tkeep,
output_3_axis_tvalid,
output_3_axis_tready,
output_3_axis_tlast,
output_3_axis_tuser,
input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
enable,
select)
output_0_axis_tdata=output_0_axis_tdata,
output_0_axis_tkeep=output_0_axis_tkeep,
output_0_axis_tvalid=output_0_axis_tvalid,
output_0_axis_tready=output_0_axis_tready,
output_0_axis_tlast=output_0_axis_tlast,
output_0_axis_tuser=output_0_axis_tuser,
output_1_axis_tdata=output_1_axis_tdata,
output_1_axis_tkeep=output_1_axis_tkeep,
output_1_axis_tvalid=output_1_axis_tvalid,
output_1_axis_tready=output_1_axis_tready,
output_1_axis_tlast=output_1_axis_tlast,
output_1_axis_tuser=output_1_axis_tuser,
output_2_axis_tdata=output_2_axis_tdata,
output_2_axis_tkeep=output_2_axis_tkeep,
output_2_axis_tvalid=output_2_axis_tvalid,
output_2_axis_tready=output_2_axis_tready,
output_2_axis_tlast=output_2_axis_tlast,
output_2_axis_tuser=output_2_axis_tuser,
output_3_axis_tdata=output_3_axis_tdata,
output_3_axis_tkeep=output_3_axis_tkeep,
output_3_axis_tvalid=output_3_axis_tvalid,
output_3_axis_tready=output_3_axis_tready,
output_3_axis_tlast=output_3_axis_tlast,
output_3_axis_tuser=output_3_axis_tuser,
enable=enable,
select=select
)
@always(delay(4))
def clkgen():
@ -310,7 +245,7 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
while input_axis_tvalid:
@ -318,9 +253,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_0_queue.empty():
rx_frame = sink_0_queue.get()
rx_frame = sink_0.recv()
assert rx_frame == test_frame
@ -336,7 +269,7 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
while input_axis_tvalid:
@ -344,9 +277,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_1_queue.empty():
rx_frame = sink_1_queue.get()
rx_frame = sink_1.recv()
assert rx_frame == test_frame
@ -366,8 +297,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid:
@ -375,15 +306,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_0_queue.empty():
rx_frame = sink_0_queue.get()
rx_frame = sink_0.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_0_queue.empty():
rx_frame = sink_0_queue.get()
rx_frame = sink_0.recv()
assert rx_frame == test_frame2
@ -403,8 +330,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid:
@ -413,15 +340,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_2_queue.empty():
rx_frame = sink_1_queue.get()
rx_frame = sink_1.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_2_queue.empty():
rx_frame = sink_2_queue.get()
rx_frame = sink_2.recv()
assert rx_frame == test_frame2
@ -441,8 +364,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid:
@ -456,15 +379,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_1_queue.empty():
rx_frame = sink_1_queue.get()
rx_frame = sink_1.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_2_queue.empty():
rx_frame = sink_2_queue.get()
rx_frame = sink_2.recv()
assert rx_frame == test_frame2
@ -484,8 +403,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid:
@ -505,15 +424,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_1_queue.empty():
rx_frame = sink_1_queue.get()
rx_frame = sink_1.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_2_queue.empty():
rx_frame = sink_2_queue.get()
rx_frame = sink_2.recv()
assert rx_frame == test_frame2
@ -521,7 +436,7 @@ def bench():
raise StopSimulation
return dut, source, sink_0, sink_1, sink_2, sink_3, clkgen, check
return dut, source_logic, sink_0_logic, sink_1_logic, sink_2_logic, sink_3_logic, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))

106
lib/axis/tb/test_axis_demux_64_4.v
View File

@ -24,17 +24,24 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1 ns / 1 ps
`timescale 1ns / 1ps
/*
* Testbench for axis_demux_64_4
*/
module test_axis_demux_64_4;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_WIDTH = (DATA_WIDTH/8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [63:0] input_axis_tdata = 0;
reg [7:0] input_axis_tkeep = 0;
reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
@ -50,64 +57,68 @@ reg [1:0] select = 0;
// Outputs
wire input_axis_tready;
wire [63:0] output_0_axis_tdata;
wire [7:0] output_0_axis_tkeep;
wire [DATA_WIDTH-1:0] output_0_axis_tdata;
wire [KEEP_WIDTH-1:0] output_0_axis_tkeep;
wire output_0_axis_tvalid;
wire output_0_axis_tlast;
wire output_0_axis_tuser;
wire [63:0] output_1_axis_tdata;
wire [7:0] output_1_axis_tkeep;
wire [DATA_WIDTH-1:0] output_1_axis_tdata;
wire [KEEP_WIDTH-1:0] output_1_axis_tkeep;
wire output_1_axis_tvalid;
wire output_1_axis_tlast;
wire output_1_axis_tuser;
wire [63:0] output_2_axis_tdata;
wire [7:0] output_2_axis_tkeep;
wire [DATA_WIDTH-1:0] output_2_axis_tdata;
wire [KEEP_WIDTH-1:0] output_2_axis_tkeep;
wire output_2_axis_tvalid;
wire output_2_axis_tlast;
wire output_2_axis_tuser;
wire [63:0] output_3_axis_tdata;
wire [7:0] output_3_axis_tkeep;
wire [DATA_WIDTH-1:0] output_3_axis_tdata;
wire [KEEP_WIDTH-1:0] output_3_axis_tkeep;
wire output_3_axis_tvalid;
wire output_3_axis_tlast;
wire output_3_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_0_axis_tready,
output_1_axis_tready,
output_2_axis_tready,
output_3_axis_tready,
enable,
select);
$to_myhdl(input_axis_tready,
output_0_axis_tdata,
output_0_axis_tkeep,
output_0_axis_tvalid,
output_0_axis_tlast,
output_0_axis_tuser,
output_1_axis_tdata,
output_1_axis_tkeep,
output_1_axis_tvalid,
output_1_axis_tlast,
output_1_axis_tuser,
output_2_axis_tdata,
output_2_axis_tkeep,
output_2_axis_tvalid,
output_2_axis_tlast,
output_2_axis_tuser,
output_3_axis_tdata,
output_3_axis_tkeep,
output_3_axis_tvalid,
output_3_axis_tlast,
output_3_axis_tuser);
$from_myhdl(
clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_0_axis_tready,
output_1_axis_tready,
output_2_axis_tready,
output_3_axis_tready,
enable,
select
);
$to_myhdl(
input_axis_tready,
output_0_axis_tdata,
output_0_axis_tkeep,
output_0_axis_tvalid,
output_0_axis_tlast,
output_0_axis_tuser,
output_1_axis_tdata,
output_1_axis_tkeep,
output_1_axis_tvalid,
output_1_axis_tlast,
output_1_axis_tuser,
output_2_axis_tdata,
output_2_axis_tkeep,
output_2_axis_tvalid,
output_2_axis_tlast,
output_2_axis_tuser,
output_3_axis_tdata,
output_3_axis_tkeep,
output_3_axis_tvalid,
output_3_axis_tlast,
output_3_axis_tuser
);
// dump file
$dumpfile("test_axis_demux_64_4.lxt");
@ -115,7 +126,8 @@ initial begin
end
axis_demux_64_4 #(
.DATA_WIDTH(64)
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH)
)
UUT (
.clk(clk),

205
lib/axis/tb/test_axis_fifo.py
View File

@ -26,67 +26,32 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_fifo'
testbench = 'test_%s' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_axis_fifo(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
ADDR_WIDTH = 2
DATA_WIDTH = 8
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
@ -94,55 +59,65 @@ def bench():
# Outputs
input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[8:])
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_axis_tdata,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
source = axis_ep.AXIStreamSource()
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
source_logic = source.create_logic(
clk,
rst,
tdata=input_axis_tdata,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
pause=source_pause,
name='source'
)
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink'
)
# DUT
dut = dut_axis_fifo(clk,
rst,
current_test,
if os.system(build_cmd):
raise Exception("Error running build command")
input_axis_tdata,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser)
input_axis_tdata=input_axis_tdata,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser
)
@always(delay(4))
def clkgen():
@ -169,16 +144,14 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -192,16 +165,14 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -213,7 +184,7 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield delay(64)
@ -234,9 +205,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -254,8 +223,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
yield output_axis_tlast.posedge
@ -264,15 +233,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -290,8 +255,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -305,15 +270,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -331,8 +292,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -346,15 +307,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -369,16 +326,14 @@ def bench():
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame.user = 1
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
assert rx_frame.user[-1]
@ -392,7 +347,7 @@ def bench():
test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
sink_pause.next = 1
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield clk.posedge
yield clk.posedge
@ -403,9 +358,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -418,7 +371,7 @@ def bench():
test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
sink_pause.next = 1
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield clk.posedge
yield clk.posedge
@ -436,13 +389,13 @@ def bench():
yield clk.posedge
yield clk.posedge
assert sink_queue.empty()
assert sink.empty()
yield delay(100)
raise StopSimulation
return dut, source, sink, clkgen, check
return dut, source_logic, sink_logic, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))

47
lib/axis/tb/test_axis_fifo.v
View File

@ -24,16 +24,23 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1 ns / 1 ps
`timescale 1ns / 1ps
/*
* Testbench for axis_fifo
*/
module test_axis_fifo;
// Parameters
parameter ADDR_WIDTH = 2;
parameter DATA_WIDTH = 8;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] input_axis_tdata = 0;
reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
@ -41,26 +48,30 @@ reg output_axis_tready = 0;
// Outputs
wire input_axis_tready;
wire [7:0] output_axis_tdata;
wire [DATA_WIDTH-1:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
$from_myhdl(
clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready
);
$to_myhdl(
input_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser
);
// dump file
$dumpfile("test_axis_fifo.lxt");
@ -68,8 +79,8 @@ initial begin
end
axis_fifo #(
.ADDR_WIDTH(2),
.DATA_WIDTH(8)
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH)
)
UUT (
.clk(clk),

222
lib/axis/tb/test_axis_fifo_64.py
View File

@ -26,72 +26,34 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_fifo_64'
testbench = 'test_%s' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_axis_fifo_64(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
ADDR_WIDTH = 2
DATA_WIDTH = 64
KEEP_WIDTH = (DATA_WIDTH/8)
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[64:])
input_axis_tkeep = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
@ -99,60 +61,70 @@ def bench():
# Outputs
input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[64:])
output_axis_tkeep = Signal(intbv(0)[8:])
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
source = axis_ep.AXIStreamSource()
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
source_logic = source.create_logic(
clk,
rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
pause=source_pause,
name='source'
)
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink'
)
# DUT
dut = dut_axis_fifo_64(clk,
rst,
current_test,
if os.system(build_cmd):
raise Exception("Error running build command")
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser)
input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser
)
@always(delay(4))
def clkgen():
@ -179,16 +151,14 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -202,16 +172,14 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -223,7 +191,7 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield delay(64)
@ -244,9 +212,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -264,8 +230,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
yield output_axis_tlast.posedge
@ -274,15 +240,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -300,8 +262,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -315,15 +277,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -341,8 +299,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -356,15 +314,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -379,16 +333,14 @@ def bench():
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame.user = 1
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
assert rx_frame.user[-1]
@ -402,7 +354,7 @@ def bench():
test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
sink_pause.next = 1
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield clk.posedge
yield clk.posedge
@ -413,9 +365,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -428,7 +378,7 @@ def bench():
test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
sink_pause.next = 1
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield clk.posedge
yield clk.posedge
@ -446,13 +396,13 @@ def bench():
yield clk.posedge
yield clk.posedge
assert sink_queue.empty()
assert sink.empty()
yield delay(100)
raise StopSimulation
return dut, source, sink, clkgen, check
return dut, source_logic, sink_logic, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))

56
lib/axis/tb/test_axis_fifo_64.v
View File

@ -24,17 +24,25 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1 ns / 1 ps
`timescale 1ns / 1ps
/*
* Testbench for axis_fifo_64
*/
module test_axis_fifo_64;
// Parameters
parameter ADDR_WIDTH = 2;
parameter DATA_WIDTH = 64;
parameter KEEP_WIDTH = (DATA_WIDTH/8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [63:0] input_axis_tdata = 0;
reg [7:0] input_axis_tkeep = 0;
reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
@ -42,29 +50,33 @@ reg output_axis_tready = 0;
// Outputs
wire input_axis_tready;
wire [63:0] output_axis_tdata;
wire [7:0] output_axis_tkeep;
wire [DATA_WIDTH-1:0] output_axis_tdata;
wire [KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
$from_myhdl(
clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready
);
$to_myhdl(
input_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser
);
// dump file
$dumpfile("test_axis_fifo_64.lxt");
@ -72,8 +84,8 @@ initial begin
end
axis_fifo_64 #(
.ADDR_WIDTH(2),
.DATA_WIDTH(64)
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH)
)
UUT (
.clk(clk),

216
lib/axis/tb/test_axis_frame_fifo.py
View File

@ -26,73 +26,33 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_frame_fifo'
testbench = 'test_%s' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_axis_frame_fifo(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
overflow,
bad_frame,
good_frame):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
overflow=overflow,
bad_frame=bad_frame,
good_frame=good_frame)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
ADDR_WIDTH = 9
DATA_WIDTH = 8
DROP_WHEN_FULL = 0
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
@ -100,7 +60,7 @@ def bench():
# Outputs
input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[8:])
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
overflow = Signal(bool(0))
@ -108,51 +68,61 @@ def bench():
good_frame = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_axis_tdata,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
source = axis_ep.AXIStreamSource()
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
fifo=sink_queue,
pause=sink_pause,
name='sink')
source_logic = source.create_logic(
clk,
rst,
tdata=input_axis_tdata,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
pause=source_pause,
name='source'
)
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
pause=sink_pause,
name='sink'
)
# DUT
dut = dut_axis_frame_fifo(clk,
rst,
current_test,
if os.system(build_cmd):
raise Exception("Error running build command")
input_axis_tdata,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
input_axis_tdata=input_axis_tdata,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
overflow,
bad_frame,
good_frame)
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
overflow=overflow,
bad_frame=bad_frame,
good_frame=good_frame
)
@always(delay(4))
def clkgen():
@ -197,16 +167,14 @@ def bench():
bad_frame_asserted.next = 0
good_frame_asserted.next = 0
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -229,16 +197,14 @@ def bench():
bad_frame_asserted.next = 0
good_frame_asserted.next = 0
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -259,7 +225,7 @@ def bench():
bad_frame_asserted.next = 0
good_frame_asserted.next = 0
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield delay(64)
@ -280,9 +246,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -309,8 +273,8 @@ def bench():
bad_frame_asserted.next = 0
good_frame_asserted.next = 0
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
yield output_axis_tlast.posedge
@ -319,15 +283,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -354,8 +314,8 @@ def bench():
bad_frame_asserted.next = 0
good_frame_asserted.next = 0
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -369,15 +329,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -404,8 +360,8 @@ def bench():
bad_frame_asserted.next = 0
good_frame_asserted.next = 0
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -419,15 +375,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -451,12 +403,12 @@ def bench():
bad_frame_asserted.next = 0
good_frame_asserted.next = 0
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield delay(1000)
assert sink_queue.empty()
assert sink.empty()
assert not overflow_asserted
assert bad_frame_asserted
@ -477,12 +429,12 @@ def bench():
bad_frame_asserted.next = 0
good_frame_asserted.next = 0
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield delay(10000)
assert sink_queue.empty()
assert sink.empty()
assert overflow_asserted
assert not bad_frame_asserted
@ -497,7 +449,7 @@ def bench():
test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
sink_pause.next = 1
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield clk.posedge
yield clk.posedge
@ -508,9 +460,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -523,7 +473,7 @@ def bench():
test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
sink_pause.next = 1
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield clk.posedge
yield clk.posedge
@ -541,13 +491,13 @@ def bench():
yield clk.posedge
yield clk.posedge
assert sink_queue.empty()
assert sink.empty()
yield delay(100)
raise StopSimulation
return dut, monitor, source, sink, clkgen, check
return dut, monitor, source_logic, sink_logic, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))

54
lib/axis/tb/test_axis_frame_fifo.v
View File

@ -24,16 +24,24 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1 ns / 1 ps
`timescale 1ns / 1ps
/*
* Testbench for axis_frame_fifo
*/
module test_axis_frame_fifo;
// Parameters
parameter ADDR_WIDTH = 9;
parameter DATA_WIDTH = 8;
parameter DROP_WHEN_FULL = 0;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] input_axis_tdata = 0;
reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
@ -41,7 +49,7 @@ reg output_axis_tready = 0;
// Outputs
wire input_axis_tready;
wire [7:0] output_axis_tdata;
wire [DATA_WIDTH-1:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
wire overflow;
@ -50,21 +58,25 @@ wire good_frame;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
overflow,
bad_frame,
good_frame);
$from_myhdl(
clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready
);
$to_myhdl(
input_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
overflow,
bad_frame,
good_frame
);
// dump file
$dumpfile("test_axis_frame_fifo.lxt");
@ -72,9 +84,9 @@ initial begin
end
axis_frame_fifo #(
.ADDR_WIDTH(9),
.DATA_WIDTH(8),
.DROP_WHEN_FULL(0)
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.DROP_WHEN_FULL(DROP_WHEN_FULL)
)
UUT (
.clk(clk),

238
lib/axis/tb/test_axis_frame_fifo_64.py
View File

@ -26,80 +26,35 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_frame_fifo_64'
testbench = 'test_%s' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_axis_frame_fifo_64(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
overflow,
bad_frame,
good_frame):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser,
overflow=overflow,
bad_frame=bad_frame,
good_frame=good_frame)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
ADDR_WIDTH = 6
DATA_WIDTH = 64
KEEP_WIDTH = (DATA_WIDTH/8)
DROP_WHEN_FULL = 0
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[64:])
input_axis_tkeep = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
@ -107,67 +62,74 @@ def bench():
# Outputs
input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[64:])
output_axis_tkeep = Signal(intbv(0)[8:])
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
overflow = Signal(bool(0))
bad_frame = Signal(bool(0))
good_frame = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
source = axis_ep.AXIStreamSource()
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
source_logic = source.create_logic(
clk,
rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
pause=source_pause,
name='source'
)
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
pause=sink_pause,
name='sink'
)
# DUT
dut = dut_axis_frame_fifo_64(clk,
rst,
current_test,
if os.system(build_cmd):
raise Exception("Error running build command")
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
overflow,
bad_frame,
good_frame)
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
overflow=overflow,
bad_frame=bad_frame,
good_frame=good_frame
)
@always(delay(4))
def clkgen():
@ -212,16 +174,14 @@ def bench():
bad_frame_asserted.next = 0
good_frame_asserted.next = 0
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -244,16 +204,14 @@ def bench():
bad_frame_asserted.next = 0
good_frame_asserted.next = 0
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -274,7 +232,7 @@ def bench():
bad_frame_asserted.next = 0
good_frame_asserted.next = 0
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield delay(64)
@ -295,9 +253,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -324,8 +280,8 @@ def bench():
bad_frame_asserted.next = 0
good_frame_asserted.next = 0
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
yield output_axis_tlast.posedge
@ -334,15 +290,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -369,8 +321,8 @@ def bench():
bad_frame_asserted.next = 0
good_frame_asserted.next = 0
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -384,15 +336,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -419,8 +367,8 @@ def bench():
bad_frame_asserted.next = 0
good_frame_asserted.next = 0
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -434,15 +382,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -466,12 +410,12 @@ def bench():
bad_frame_asserted.next = 0
good_frame_asserted.next = 0
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield delay(1000)
assert sink_queue.empty()
assert sink.empty()
assert not overflow_asserted
assert bad_frame_asserted
@ -492,12 +436,12 @@ def bench():
bad_frame_asserted.next = 0
good_frame_asserted.next = 0
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield delay(10000)
assert sink_queue.empty()
assert sink.empty()
assert overflow_asserted
assert not bad_frame_asserted
@ -512,7 +456,7 @@ def bench():
test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
sink_pause.next = 1
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield clk.posedge
yield clk.posedge
@ -523,9 +467,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -538,7 +480,7 @@ def bench():
test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
sink_pause.next = 1
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield clk.posedge
yield clk.posedge
@ -556,13 +498,13 @@ def bench():
yield clk.posedge
yield clk.posedge
assert sink_queue.empty()
assert sink.empty()
yield delay(100)
raise StopSimulation
return dut, monitor, source, sink, clkgen, check
return dut, monitor, source_logic, sink_logic, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))

64
lib/axis/tb/test_axis_frame_fifo_64.v
View File

@ -24,17 +24,26 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1 ns / 1 ps
`timescale 1ns / 1ps
/*
* Testbench for axis_frame_fifo_64
*/
module test_axis_frame_fifo_64;
// Parameters
parameter ADDR_WIDTH = 6;
parameter DATA_WIDTH = 64;
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter DROP_WHEN_FULL = 0;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [63:0] input_axis_tdata = 0;
reg [7:0] input_axis_tkeep = 0;
reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
@ -42,8 +51,8 @@ reg output_axis_tready = 0;
// Outputs
wire input_axis_tready;
wire [63:0] output_axis_tdata;
wire [7:0] output_axis_tkeep;
wire [DATA_WIDTH-1:0] output_axis_tdata;
wire [KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid;
wire output_axis_tlast;
wire overflow;
@ -52,23 +61,27 @@ wire good_frame;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
overflow,
bad_frame,
good_frame);
$from_myhdl(
clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready
);
$to_myhdl(
input_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
overflow,
bad_frame,
good_frame
);
// dump file
$dumpfile("test_axis_frame_fifo_64.lxt");
@ -76,9 +89,10 @@ initial begin
end
axis_frame_fifo_64 #(
.ADDR_WIDTH(6),
.DATA_WIDTH(64),
.DROP_WHEN_FULL(0)
.ADDR_WIDTH(ADDR_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.DROP_WHEN_FULL(DROP_WHEN_FULL)
)
UUT (
.clk(clk),

401
lib/axis/tb/test_axis_frame_join_4.py
View File

@ -27,103 +27,26 @@ from myhdl import *
import os
import struct
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_frame_join_4'
testbench = 'test_%s' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_axis_frame_join_4(clk,
rst,
current_test,
input_0_axis_tdata,
input_0_axis_tvalid,
input_0_axis_tready,
input_0_axis_tlast,
input_0_axis_tuser,
input_1_axis_tdata,
input_1_axis_tvalid,
input_1_axis_tready,
input_1_axis_tlast,
input_1_axis_tuser,
input_2_axis_tdata,
input_2_axis_tvalid,
input_2_axis_tready,
input_2_axis_tlast,
input_2_axis_tuser,
input_3_axis_tdata,
input_3_axis_tvalid,
input_3_axis_tready,
input_3_axis_tlast,
input_3_axis_tuser,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
tag,
busy):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_0_axis_tdata=input_0_axis_tdata,
input_0_axis_tvalid=input_0_axis_tvalid,
input_0_axis_tready=input_0_axis_tready,
input_0_axis_tlast=input_0_axis_tlast,
input_0_axis_tuser=input_0_axis_tuser,
input_1_axis_tdata=input_1_axis_tdata,
input_1_axis_tvalid=input_1_axis_tvalid,
input_1_axis_tready=input_1_axis_tready,
input_1_axis_tlast=input_1_axis_tlast,
input_1_axis_tuser=input_1_axis_tuser,
input_2_axis_tdata=input_2_axis_tdata,
input_2_axis_tvalid=input_2_axis_tvalid,
input_2_axis_tready=input_2_axis_tready,
input_2_axis_tlast=input_2_axis_tlast,
input_2_axis_tuser=input_2_axis_tuser,
input_3_axis_tdata=input_3_axis_tdata,
input_3_axis_tvalid=input_3_axis_tvalid,
input_3_axis_tready=input_3_axis_tready,
input_3_axis_tlast=input_3_axis_tlast,
input_3_axis_tuser=input_3_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser,
tag=tag,
busy=busy)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
TAG_ENABLE = 1
TAG_WIDTH = 16
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
@ -146,7 +69,7 @@ def bench():
input_3_axis_tlast = Signal(bool(0))
input_3_axis_tuser = Signal(bool(0))
output_axis_tready = Signal(bool(0))
tag = Signal(intbv(0)[15:])
tag = Signal(intbv(0)[TAG_WIDTH:])
# Outputs
input_0_axis_tready = Signal(bool(0))
@ -160,109 +83,125 @@ def bench():
busy = Signal(bool(0))
# sources and sinks
source_0_queue = Queue()
source_0_pause = Signal(bool(0))
source_1_queue = Queue()
source_1_pause = Signal(bool(0))
source_2_queue = Queue()
source_2_pause = Signal(bool(0))
source_3_queue = Queue()
source_3_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source_0 = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_0_axis_tdata,
tvalid=input_0_axis_tvalid,
tready=input_0_axis_tready,
tlast=input_0_axis_tlast,
tuser=input_0_axis_tuser,
fifo=source_0_queue,
pause=source_0_pause,
name='source_0')
source_0 = axis_ep.AXIStreamSource()
source_1 = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_1_axis_tdata,
tvalid=input_1_axis_tvalid,
tready=input_1_axis_tready,
tlast=input_1_axis_tlast,
tuser=input_1_axis_tuser,
fifo=source_1_queue,
pause=source_1_pause,
name='source_1')
source_0_logic = source_0.create_logic(
clk,
rst,
tdata=input_0_axis_tdata,
tvalid=input_0_axis_tvalid,
tready=input_0_axis_tready,
tlast=input_0_axis_tlast,
tuser=input_0_axis_tuser,
pause=source_0_pause,
name='source_0'
)
source_2 = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_2_axis_tdata,
tvalid=input_2_axis_tvalid,
tready=input_2_axis_tready,
tlast=input_2_axis_tlast,
tuser=input_2_axis_tuser,
fifo=source_2_queue,
pause=source_2_pause,
name='source_2')
source_1 = axis_ep.AXIStreamSource()
source_3 = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_3_axis_tdata,
tvalid=input_3_axis_tvalid,
tready=input_3_axis_tready,
tlast=input_3_axis_tlast,
tuser=input_3_axis_tuser,
fifo=source_3_queue,
pause=source_3_pause,
name='source_3')
source_1_logic = source_1.create_logic(
clk,
rst,
tdata=input_1_axis_tdata,
tvalid=input_1_axis_tvalid,
tready=input_1_axis_tready,
tlast=input_1_axis_tlast,
tuser=input_1_axis_tuser,
pause=source_1_pause,
name='source_1'
)
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
source_2 = axis_ep.AXIStreamSource()
source_2_logic = source_2.create_logic(
clk,
rst,
tdata=input_2_axis_tdata,
tvalid=input_2_axis_tvalid,
tready=input_2_axis_tready,
tlast=input_2_axis_tlast,
tuser=input_2_axis_tuser,
pause=source_2_pause,
name='source_2'
)
source_3 = axis_ep.AXIStreamSource()
source_3_logic = source_3.create_logic(
clk,
rst,
tdata=input_3_axis_tdata,
tvalid=input_3_axis_tvalid,
tready=input_3_axis_tready,
tlast=input_3_axis_tlast,
tuser=input_3_axis_tuser,
pause=source_3_pause,
name='source_3'
)
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink'
)
# DUT
dut = dut_axis_frame_join_4(clk,
rst,
current_test,
if os.system(build_cmd):
raise Exception("Error running build command")
input_0_axis_tdata,
input_0_axis_tvalid,
input_0_axis_tready,
input_0_axis_tlast,
input_0_axis_tuser,
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
input_1_axis_tdata,
input_1_axis_tvalid,
input_1_axis_tready,
input_1_axis_tlast,
input_1_axis_tuser,
input_0_axis_tdata=input_0_axis_tdata,
input_0_axis_tvalid=input_0_axis_tvalid,
input_0_axis_tready=input_0_axis_tready,
input_0_axis_tlast=input_0_axis_tlast,
input_0_axis_tuser=input_0_axis_tuser,
input_2_axis_tdata,
input_2_axis_tvalid,
input_2_axis_tready,
input_2_axis_tlast,
input_2_axis_tuser,
input_1_axis_tdata=input_1_axis_tdata,
input_1_axis_tvalid=input_1_axis_tvalid,
input_1_axis_tready=input_1_axis_tready,
input_1_axis_tlast=input_1_axis_tlast,
input_1_axis_tuser=input_1_axis_tuser,
input_3_axis_tdata,
input_3_axis_tvalid,
input_3_axis_tready,
input_3_axis_tlast,
input_3_axis_tuser,
input_2_axis_tdata=input_2_axis_tdata,
input_2_axis_tvalid=input_2_axis_tvalid,
input_2_axis_tready=input_2_axis_tready,
input_2_axis_tlast=input_2_axis_tlast,
input_2_axis_tuser=input_2_axis_tuser,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
input_3_axis_tdata=input_3_axis_tdata,
input_3_axis_tvalid=input_3_axis_tvalid,
input_3_axis_tready=input_3_axis_tready,
input_3_axis_tlast=input_3_axis_tlast,
input_3_axis_tuser=input_3_axis_tuser,
tag,
busy)
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser,
tag=tag,
busy=busy
)
@always(delay(4))
def clkgen():
@ -290,19 +229,17 @@ def bench():
test_frame_1 = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
test_frame_2 = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_3 = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
source_0_queue.put(test_frame_0)
source_1_queue.put(test_frame_1)
source_2_queue.put(test_frame_2)
source_3_queue.put(test_frame_3)
source_0.send(test_frame_0)
source_1.send(test_frame_1)
source_2.send(test_frame_2)
source_3.send(test_frame_3)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack('>H', tag) + test_frame_0.data + test_frame_1.data + test_frame_2.data + test_frame_3.data
@ -316,19 +253,17 @@ def bench():
test_frame_1 = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
test_frame_2 = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_3 = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
source_0_queue.put(test_frame_0)
source_1_queue.put(test_frame_1)
source_2_queue.put(test_frame_2)
source_3_queue.put(test_frame_3)
source_0.send(test_frame_0)
source_1.send(test_frame_1)
source_2.send(test_frame_2)
source_3.send(test_frame_3)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack('>H', tag) + test_frame_0.data + test_frame_1.data + test_frame_2.data + test_frame_3.data
@ -342,10 +277,10 @@ def bench():
test_frame_1 = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
test_frame_2 = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_3 = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
source_0_queue.put(test_frame_0)
source_1_queue.put(test_frame_1)
source_2_queue.put(test_frame_2)
source_3_queue.put(test_frame_3)
source_0.send(test_frame_0)
source_1.send(test_frame_1)
source_2.send(test_frame_2)
source_3.send(test_frame_3)
yield clk.posedge
yield delay(64)
@ -366,9 +301,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack('>H', tag) + test_frame_0.data + test_frame_1.data + test_frame_2.data + test_frame_3.data
@ -386,14 +319,14 @@ def bench():
test_frame_2b = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_3a = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
test_frame_3b = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
source_0_queue.put(test_frame_0a)
source_0_queue.put(test_frame_0b)
source_1_queue.put(test_frame_1a)
source_1_queue.put(test_frame_1b)
source_2_queue.put(test_frame_2a)
source_2_queue.put(test_frame_2b)
source_3_queue.put(test_frame_3a)
source_3_queue.put(test_frame_3b)
source_0.send(test_frame_0a)
source_0.send(test_frame_0b)
source_1.send(test_frame_1a)
source_1.send(test_frame_1b)
source_2.send(test_frame_2a)
source_2.send(test_frame_2b)
source_3.send(test_frame_3a)
source_3.send(test_frame_3b)
yield clk.posedge
yield output_axis_tlast.posedge
@ -402,15 +335,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack('>H', tag) + test_frame_0a.data + test_frame_1a.data + test_frame_2a.data + test_frame_3a.data
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack('>H', tag) + test_frame_0b.data + test_frame_1b.data + test_frame_2b.data + test_frame_3b.data
@ -428,14 +357,14 @@ def bench():
test_frame_2b = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_3a = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
test_frame_3b = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
source_0_queue.put(test_frame_0a)
source_0_queue.put(test_frame_0b)
source_1_queue.put(test_frame_1a)
source_1_queue.put(test_frame_1b)
source_2_queue.put(test_frame_2a)
source_2_queue.put(test_frame_2b)
source_3_queue.put(test_frame_3a)
source_3_queue.put(test_frame_3b)
source_0.send(test_frame_0a)
source_0.send(test_frame_0b)
source_1.send(test_frame_1a)
source_1.send(test_frame_1b)
source_2.send(test_frame_2a)
source_2.send(test_frame_2b)
source_3.send(test_frame_3a)
source_3.send(test_frame_3b)
yield clk.posedge
while input_3_axis_tvalid or output_axis_tvalid:
@ -455,15 +384,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack('>H', tag) + test_frame_0a.data + test_frame_1a.data + test_frame_2a.data + test_frame_3a.data
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack('>H', tag) + test_frame_0b.data + test_frame_1b.data + test_frame_2b.data + test_frame_3b.data
@ -481,14 +406,14 @@ def bench():
test_frame_2b = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_3a = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
test_frame_3b = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
source_0_queue.put(test_frame_0a)
source_0_queue.put(test_frame_0b)
source_1_queue.put(test_frame_1a)
source_1_queue.put(test_frame_1b)
source_2_queue.put(test_frame_2a)
source_2_queue.put(test_frame_2b)
source_3_queue.put(test_frame_3a)
source_3_queue.put(test_frame_3b)
source_0.send(test_frame_0a)
source_0.send(test_frame_0b)
source_1.send(test_frame_1a)
source_1.send(test_frame_1b)
source_2.send(test_frame_2a)
source_2.send(test_frame_2b)
source_3.send(test_frame_3a)
source_3.send(test_frame_3b)
yield clk.posedge
while input_3_axis_tvalid or output_axis_tvalid:
@ -502,15 +427,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack('>H', tag) + test_frame_0a.data + test_frame_1a.data + test_frame_2a.data + test_frame_3a.data
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack('>H', tag) + test_frame_0b.data + test_frame_1b.data + test_frame_2b.data + test_frame_3b.data
@ -525,19 +446,17 @@ def bench():
test_frame_2 = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_3 = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
test_frame_0.user = 1
source_0_queue.put(test_frame_0)
source_1_queue.put(test_frame_1)
source_2_queue.put(test_frame_2)
source_3_queue.put(test_frame_3)
source_0.send(test_frame_0)
source_1.send(test_frame_1)
source_2.send(test_frame_2)
source_3.send(test_frame_3)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack('>H', tag) + test_frame_0.data + test_frame_1.data + test_frame_2.data + test_frame_3.data
assert rx_frame.user[-1]
@ -546,7 +465,7 @@ def bench():
raise StopSimulation
return dut, source_0, source_1, source_2, source_3, sink, clkgen, check
return dut, source_0_logic, source_1_logic, source_2_logic, source_3_logic, sink_logic, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))

112
lib/axis/tb/test_axis_frame_join_4.v
View File

@ -24,33 +24,40 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1 ns / 1 ps
`timescale 1ns / 1ps
/*
* Testbench for axis_frame_join_4
*/
module test_axis_frame_join_4;
// Parameters
parameter TAG_ENABLE = 1;
parameter TAG_WIDTH = 16;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] input_0_axis_tdata = 8'd0;
reg input_0_axis_tvalid = 1'b0;
reg input_0_axis_tlast = 1'b0;
reg input_0_axis_tuser = 1'b0;
reg [7:0] input_1_axis_tdata = 8'd0;
reg input_1_axis_tvalid = 1'b0;
reg input_1_axis_tlast = 1'b0;
reg input_1_axis_tuser = 1'b0;
reg [7:0] input_2_axis_tdata = 8'd0;
reg input_2_axis_tvalid = 1'b0;
reg input_2_axis_tlast = 1'b0;
reg input_2_axis_tuser = 1'b0;
reg [7:0] input_3_axis_tdata = 8'd0;
reg input_3_axis_tvalid = 1'b0;
reg input_3_axis_tlast = 1'b0;
reg input_3_axis_tuser = 1'b0;
reg output_axis_tready = 1'b0;
reg [15:0] tag = 0;
reg [7:0] input_0_axis_tdata = 0;
reg input_0_axis_tvalid = 0;
reg input_0_axis_tlast = 0;
reg input_0_axis_tuser = 0;
reg [7:0] input_1_axis_tdata = 0;
reg input_1_axis_tvalid = 0;
reg input_1_axis_tlast = 0;
reg input_1_axis_tuser = 0;
reg [7:0] input_2_axis_tdata = 0;
reg input_2_axis_tvalid = 0;
reg input_2_axis_tlast = 0;
reg input_2_axis_tuser = 0;
reg [7:0] input_3_axis_tdata = 0;
reg input_3_axis_tvalid = 0;
reg input_3_axis_tlast = 0;
reg input_3_axis_tuser = 0;
reg output_axis_tready = 0;
reg [TAG_WIDTH-1:0] tag = 0;
// Outputs
wire input_0_axis_tready;
@ -65,36 +72,40 @@ wire busy;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_0_axis_tdata,
input_0_axis_tvalid,
input_0_axis_tlast,
input_0_axis_tuser,
input_1_axis_tdata,
input_1_axis_tvalid,
input_1_axis_tlast,
input_1_axis_tuser,
input_2_axis_tdata,
input_2_axis_tvalid,
input_2_axis_tlast,
input_2_axis_tuser,
input_3_axis_tdata,
input_3_axis_tvalid,
input_3_axis_tlast,
input_3_axis_tuser,
output_axis_tready,
tag);
$to_myhdl(input_0_axis_tready,
input_1_axis_tready,
input_2_axis_tready,
input_3_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser,
busy);
$from_myhdl(
clk,
rst,
current_test,
input_0_axis_tdata,
input_0_axis_tvalid,
input_0_axis_tlast,
input_0_axis_tuser,
input_1_axis_tdata,
input_1_axis_tvalid,
input_1_axis_tlast,
input_1_axis_tuser,
input_2_axis_tdata,
input_2_axis_tvalid,
input_2_axis_tlast,
input_2_axis_tuser,
input_3_axis_tdata,
input_3_axis_tvalid,
input_3_axis_tlast,
input_3_axis_tuser,
output_axis_tready,
tag
);
$to_myhdl(
input_0_axis_tready,
input_1_axis_tready,
input_2_axis_tready,
input_3_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser,
busy
);
// dump file
$dumpfile("test_axis_frame_join_4.lxt");
@ -102,7 +113,8 @@ initial begin
end
axis_frame_join_4 #(
.TAG_ENABLE(1)
.TAG_ENABLE(TAG_ENABLE),
.TAG_WIDTH(TAG_WIDTH)
)
UUT (
.clk(clk),

249
lib/axis/tb/test_axis_frame_length_adjust_64.py
View File

@ -26,92 +26,33 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_frame_length_adjust'
testbench = 'test_%s_64' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s_64.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s_64.vvp %s" % (module, src)
def dut_axis_frame_length_adjust_64(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
status_valid,
status_ready,
status_frame_pad,
status_frame_truncate,
status_frame_length,
status_frame_original_length,
length_min,
length_max):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s_64.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser,
status_valid=status_valid,
status_ready=status_ready,
status_frame_pad=status_frame_pad,
status_frame_truncate=status_frame_truncate,
status_frame_length=status_frame_length,
status_frame_original_length=status_frame_original_length,
length_min=length_min,
length_max=length_max)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
DATA_WIDTH = 64
KEEP_WIDTH = (DATA_WIDTH/8)
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[64:])
input_axis_tkeep = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
@ -122,8 +63,8 @@ def bench():
# Outputs
input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[64:])
output_axis_tkeep = Signal(intbv(0)[8:])
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
@ -134,74 +75,86 @@ def bench():
status_frame_original_length = Signal(intbv(0)[16:])
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
status_sink_queue = Queue()
status_sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
source = axis_ep.AXIStreamSource()
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
source_logic = source.create_logic(
clk,
rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
pause=source_pause,
name='source'
)
status_sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=(status_frame_pad, status_frame_truncate, status_frame_length, status_frame_original_length),
tvalid=status_valid,
tready=status_ready,
fifo=status_sink_queue,
pause=status_sink_pause,
name='status_sink')
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink'
)
status_sink = axis_ep.AXIStreamSink()
status_sink_logic = status_sink.create_logic(
clk,
rst,
tdata=(status_frame_pad, status_frame_truncate, status_frame_length, status_frame_original_length),
tvalid=status_valid,
tready=status_ready,
pause=status_sink_pause,
name='status_sink'
)
# DUT
dut = dut_axis_frame_length_adjust_64(clk,
rst,
current_test,
if os.system(build_cmd):
raise Exception("Error running build command")
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
status_valid,
status_ready,
status_frame_pad,
status_frame_truncate,
status_frame_length,
status_frame_original_length,
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser,
length_min,
length_max)
status_valid=status_valid,
status_ready=status_ready,
status_frame_pad=status_frame_pad,
status_frame_truncate=status_frame_truncate,
status_frame_length=status_frame_length,
status_frame_original_length=status_frame_original_length,
length_min=length_min,
length_max=length_max
)
@always(delay(4))
def clkgen():
@ -256,7 +209,7 @@ def bench():
test_frame = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield clk.posedge
@ -266,7 +219,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = sink_queue.get(False)
rx_frame = sink.recv()
lrx = len(rx_frame.data)
lt = len(test_frame.data)
@ -275,14 +228,14 @@ def bench():
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame.data[:lm]
status = status_sink_queue.get(False)
status = status_sink.recv()
assert status.data[0][0] == (lt < lmin)
assert status.data[0][1] == (lt > lmax)
assert status.data[0][2] == lrx
assert status.data[0][3] == lt
assert sink_queue.empty()
assert status_sink_queue.empty()
assert sink.empty()
assert status_sink.empty()
yield delay(100)
@ -294,8 +247,8 @@ def bench():
test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
yield clk.posedge
@ -305,7 +258,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = sink_queue.get(False)
rx_frame = sink.recv()
lrx = len(rx_frame.data)
lt = len(test_frame1.data)
@ -314,13 +267,13 @@ def bench():
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame1.data[:lm]
status = status_sink_queue.get(False)
status = status_sink.recv()
assert status.data[0][0] == (lt < lmin)
assert status.data[0][1] == (lt > lmax)
assert status.data[0][2] == lrx
assert status.data[0][3] == lt
rx_frame = sink_queue.get(False)
rx_frame = sink.recv()
lrx = len(rx_frame.data)
lt = len(test_frame2.data)
@ -329,14 +282,14 @@ def bench():
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame2.data[:lm]
status = status_sink_queue.get(False)
status = status_sink.recv()
assert status.data[0][0] == (lt < lmin)
assert status.data[0][1] == (lt > lmax)
assert status.data[0][2] == lrx
assert status.data[0][3] == lt
assert sink_queue.empty()
assert status_sink_queue.empty()
assert sink.empty()
assert status_sink.empty()
yield delay(100)
@ -350,8 +303,8 @@ def bench():
test_frame1.user = 1
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
yield clk.posedge
@ -361,7 +314,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = sink_queue.get(False)
rx_frame = sink.recv()
lrx = len(rx_frame.data)
lt = len(test_frame1.data)
@ -372,13 +325,13 @@ def bench():
assert rx_frame.user[-1]
status = status_sink_queue.get(False)
status = status_sink.recv()
assert status.data[0][0] == (lt < lmin)
assert status.data[0][1] == (lt > lmax)
assert status.data[0][2] == lrx
assert status.data[0][3] == lt
rx_frame = sink_queue.get(False)
rx_frame = sink.recv()
lrx = len(rx_frame.data)
lt = len(test_frame2.data)
@ -387,20 +340,20 @@ def bench():
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame2.data[:lm]
status = status_sink_queue.get(False)
status = status_sink.recv()
assert status.data[0][0] == (lt < lmin)
assert status.data[0][1] == (lt > lmax)
assert status.data[0][2] == lrx
assert status.data[0][3] == lt
assert sink_queue.empty()
assert status_sink_queue.empty()
assert sink.empty()
assert status_sink.empty()
yield delay(100)
raise StopSimulation
return dut, source, sink, status_sink, clkgen, check
return dut, source_logic, sink_logic, status_sink_logic, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))

57
lib/axis/tb/test_axis_frame_length_adjust_64.v
View File

@ -24,11 +24,14 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1 ns / 1 ps
`timescale 1ns / 1ps
/*
* Testbench for axis_frame_length_adjust
*/
module test_axis_frame_length_adjust_64;
// parameters
// Parameters
localparam DATA_WIDTH = 64;
localparam KEEP_WIDTH = (DATA_WIDTH/8);
@ -62,29 +65,33 @@ wire [15:0] status_frame_original_length;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready,
status_ready,
length_min,
length_max);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser,
status_valid,
status_frame_pad,
status_frame_truncate,
status_frame_length,
status_frame_original_length);
$from_myhdl(
clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready,
status_ready,
length_min,
length_max
);
$to_myhdl(
input_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser,
status_valid,
status_frame_pad,
status_frame_truncate,
status_frame_length,
status_frame_original_length
);
// dump file
$dumpfile("test_axis_frame_length_adjust_64.lxt");

249
lib/axis/tb/test_axis_frame_length_adjust_8.py
View File

@ -26,92 +26,33 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_frame_length_adjust'
testbench = 'test_%s_8' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s_8.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s_8.vvp %s" % (module, src)
def dut_axis_frame_length_adjust_8(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
status_valid,
status_ready,
status_frame_pad,
status_frame_truncate,
status_frame_length,
status_frame_original_length,
length_min,
length_max):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s_8.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser,
status_valid=status_valid,
status_ready=status_ready,
status_frame_pad=status_frame_pad,
status_frame_truncate=status_frame_truncate,
status_frame_length=status_frame_length,
status_frame_original_length=status_frame_original_length,
length_min=length_min,
length_max=length_max)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
DATA_WIDTH = 8
KEEP_WIDTH = (DATA_WIDTH/8)
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[8:])
input_axis_tkeep = Signal(intbv(0)[1:])
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
@ -122,8 +63,8 @@ def bench():
# Outputs
input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[8:])
output_axis_tkeep = Signal(intbv(0)[1:])
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
@ -134,74 +75,86 @@ def bench():
status_frame_original_length = Signal(intbv(0)[16:])
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
status_sink_queue = Queue()
status_sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
source = axis_ep.AXIStreamSource()
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
source_logic = source.create_logic(
clk,
rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
pause=source_pause,
name='source'
)
status_sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=(status_frame_pad, status_frame_truncate, status_frame_length, status_frame_original_length),
tvalid=status_valid,
tready=status_ready,
fifo=status_sink_queue,
pause=status_sink_pause,
name='status_sink')
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink'
)
status_sink = axis_ep.AXIStreamSink()
status_sink_logic = status_sink.create_logic(
clk,
rst,
tdata=(status_frame_pad, status_frame_truncate, status_frame_length, status_frame_original_length),
tvalid=status_valid,
tready=status_ready,
pause=status_sink_pause,
name='status_sink'
)
# DUT
dut = dut_axis_frame_length_adjust_8(clk,
rst,
current_test,
if os.system(build_cmd):
raise Exception("Error running build command")
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
status_valid,
status_ready,
status_frame_pad,
status_frame_truncate,
status_frame_length,
status_frame_original_length,
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser,
length_min,
length_max)
status_valid=status_valid,
status_ready=status_ready,
status_frame_pad=status_frame_pad,
status_frame_truncate=status_frame_truncate,
status_frame_length=status_frame_length,
status_frame_original_length=status_frame_original_length,
length_min=length_min,
length_max=length_max
)
@always(delay(4))
def clkgen():
@ -256,7 +209,7 @@ def bench():
test_frame = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield clk.posedge
@ -266,7 +219,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = sink_queue.get(False)
rx_frame = sink.recv()
lrx = len(rx_frame.data)
lt = len(test_frame.data)
@ -275,14 +228,14 @@ def bench():
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame.data[:lm]
status = status_sink_queue.get(False)
status = status_sink.recv()
assert status.data[0][0] == (lt < lmin)
assert status.data[0][1] == (lt > lmax)
assert status.data[0][2] == lrx
assert status.data[0][3] == lt
assert sink_queue.empty()
assert status_sink_queue.empty()
assert sink.empty()
assert status_sink.empty()
yield delay(100)
@ -294,8 +247,8 @@ def bench():
test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
yield clk.posedge
@ -305,7 +258,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = sink_queue.get(False)
rx_frame = sink.recv()
lrx = len(rx_frame.data)
lt = len(test_frame1.data)
@ -314,13 +267,13 @@ def bench():
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame1.data[:lm]
status = status_sink_queue.get(False)
status = status_sink.recv()
assert status.data[0][0] == (lt < lmin)
assert status.data[0][1] == (lt > lmax)
assert status.data[0][2] == lrx
assert status.data[0][3] == lt
rx_frame = sink_queue.get(False)
rx_frame = sink.recv()
lrx = len(rx_frame.data)
lt = len(test_frame2.data)
@ -329,14 +282,14 @@ def bench():
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame2.data[:lm]
status = status_sink_queue.get(False)
status = status_sink.recv()
assert status.data[0][0] == (lt < lmin)
assert status.data[0][1] == (lt > lmax)
assert status.data[0][2] == lrx
assert status.data[0][3] == lt
assert sink_queue.empty()
assert status_sink_queue.empty()
assert sink.empty()
assert status_sink.empty()
yield delay(100)
@ -350,8 +303,8 @@ def bench():
test_frame1.user = 1
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
yield clk.posedge
@ -361,7 +314,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = sink_queue.get(False)
rx_frame = sink.recv()
lrx = len(rx_frame.data)
lt = len(test_frame1.data)
@ -372,13 +325,13 @@ def bench():
assert rx_frame.user[-1]
status = status_sink_queue.get(False)
status = status_sink.recv()
assert status.data[0][0] == (lt < lmin)
assert status.data[0][1] == (lt > lmax)
assert status.data[0][2] == lrx
assert status.data[0][3] == lt
rx_frame = sink_queue.get(False)
rx_frame = sink.recv()
lrx = len(rx_frame.data)
lt = len(test_frame2.data)
@ -387,20 +340,20 @@ def bench():
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame2.data[:lm]
status = status_sink_queue.get(False)
status = status_sink.recv()
assert status.data[0][0] == (lt < lmin)
assert status.data[0][1] == (lt > lmax)
assert status.data[0][2] == lrx
assert status.data[0][3] == lt
assert sink_queue.empty()
assert status_sink_queue.empty()
assert sink.empty()
assert status_sink.empty()
yield delay(100)
raise StopSimulation
return dut, source, sink, status_sink, clkgen, check
return dut, source_logic, sink_logic, status_sink_logic, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))

57
lib/axis/tb/test_axis_frame_length_adjust_8.v
View File

@ -24,11 +24,14 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1 ns / 1 ps
`timescale 1ns / 1ps
/*
* Testbench for axis_frame_length_adjust
*/
module test_axis_frame_length_adjust_8;
// parameters
// Parameters
localparam DATA_WIDTH = 8;
localparam KEEP_WIDTH = (DATA_WIDTH/8);
@ -62,29 +65,33 @@ wire [15:0] status_frame_original_length;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready,
status_ready,
length_min,
length_max);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser,
status_valid,
status_frame_pad,
status_frame_truncate,
status_frame_length,
status_frame_original_length);
$from_myhdl(
clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready,
status_ready,
length_min,
length_max
);
$to_myhdl(
input_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser,
status_valid,
status_frame_pad,
status_frame_truncate,
status_frame_length,
status_frame_original_length
);
// dump file
$dumpfile("test_axis_frame_length_adjust_8.lxt");

242
lib/axis/tb/test_axis_frame_length_adjust_fifo.py
View File

@ -26,87 +26,35 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_frame_length_adjust_fifo'
testbench = 'test_%s' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/axis_frame_length_adjust.v")
srcs.append("../rtl/axis_fifo.v")
srcs.append("test_%s.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_axis_frame_length_adjust_fifo(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_axis_hdr_valid,
output_axis_hdr_ready,
output_axis_hdr_pad,
output_axis_hdr_truncate,
output_axis_hdr_length,
output_axis_hdr_original_length,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
length_min,
length_max):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_hdr_valid=output_axis_hdr_valid,
output_axis_hdr_ready=output_axis_hdr_ready,
output_axis_hdr_pad=output_axis_hdr_pad,
output_axis_hdr_truncate=output_axis_hdr_truncate,
output_axis_hdr_length=output_axis_hdr_length,
output_axis_hdr_original_length=output_axis_hdr_original_length,
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser,
length_min=length_min,
length_max=length_max)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
DATA_WIDTH = 8
FRAME_FIFO_ADDR_WIDTH = 12
HEADER_FIFO_ADDR_WIDTH = 3
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
@ -122,75 +70,87 @@ def bench():
output_axis_hdr_truncate = Signal(bool(0))
output_axis_hdr_length = Signal(intbv(0)[16:])
output_axis_hdr_original_length = Signal(intbv(0)[16:])
output_axis_tdata = Signal(intbv(0)[8:])
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
hdr_sink_queue = Queue()
hdr_sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_axis_tdata,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
source = axis_ep.AXIStreamSource()
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
source_logic = source.create_logic(
clk,
rst,
tdata=input_axis_tdata,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
pause=source_pause,
name='source'
)
hdr_sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=(output_axis_hdr_pad, output_axis_hdr_truncate, output_axis_hdr_length, output_axis_hdr_original_length),
tvalid=output_axis_hdr_valid,
tready=output_axis_hdr_ready,
fifo=hdr_sink_queue,
pause=hdr_sink_pause,
name='hdr_sink')
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink'
)
hdr_sink = axis_ep.AXIStreamSink()
hdr_sink_logic = hdr_sink.create_logic(
clk,
rst,
tdata=(output_axis_hdr_pad, output_axis_hdr_truncate, output_axis_hdr_length, output_axis_hdr_original_length),
tvalid=output_axis_hdr_valid,
tready=output_axis_hdr_ready,
pause=hdr_sink_pause,
name='hdr_sink'
)
# DUT
dut = dut_axis_frame_length_adjust_fifo(clk,
rst,
current_test,
if os.system(build_cmd):
raise Exception("Error running build command")
input_axis_tdata,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
output_axis_hdr_valid,
output_axis_hdr_ready,
output_axis_hdr_pad,
output_axis_hdr_truncate,
output_axis_hdr_length,
output_axis_hdr_original_length,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
input_axis_tdata=input_axis_tdata,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
length_min,
length_max)
output_axis_hdr_valid=output_axis_hdr_valid,
output_axis_hdr_ready=output_axis_hdr_ready,
output_axis_hdr_pad=output_axis_hdr_pad,
output_axis_hdr_truncate=output_axis_hdr_truncate,
output_axis_hdr_length=output_axis_hdr_length,
output_axis_hdr_original_length=output_axis_hdr_original_length,
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser,
length_min=length_min,
length_max=length_max
)
@always(delay(4))
def clkgen():
@ -227,7 +187,7 @@ def bench():
test_frame = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
for wait in wait_normal,:
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield clk.posedge
yield clk.posedge
@ -241,9 +201,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
lrx = len(rx_frame.data)
lt = len(test_frame.data)
@ -252,14 +210,14 @@ def bench():
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame.data[:lm]
hdr = hdr_sink_queue.get(False)
hdr = hdr_sink.recv()
assert hdr.data[0][0] == (lt < lmin)
assert hdr.data[0][1] == (lt > lmax)
assert hdr.data[0][2] == lrx
assert hdr.data[0][3] == lt
assert sink_queue.empty()
assert hdr_sink_queue.empty()
assert sink.empty()
assert hdr_sink.empty()
yield delay(100)
@ -271,8 +229,8 @@ def bench():
test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
for wait in wait_normal,:
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
yield clk.posedge
@ -284,9 +242,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
lrx = len(rx_frame.data)
lt = len(test_frame1.data)
@ -295,15 +251,13 @@ def bench():
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame1.data[:lm]
hdr = hdr_sink_queue.get(False)
hdr = hdr_sink.recv()
assert hdr.data[0][0] == (lt < lmin)
assert hdr.data[0][1] == (lt > lmax)
assert hdr.data[0][2] == lrx
assert hdr.data[0][3] == lt
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
lrx = len(rx_frame.data)
lt = len(test_frame2.data)
@ -312,14 +266,14 @@ def bench():
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame2.data[:lm]
hdr = hdr_sink_queue.get(False)
hdr = hdr_sink.recv()
assert hdr.data[0][0] == (lt < lmin)
assert hdr.data[0][1] == (lt > lmax)
assert hdr.data[0][2] == lrx
assert hdr.data[0][3] == lt
assert sink_queue.empty()
assert hdr_sink_queue.empty()
assert sink.empty()
assert hdr_sink.empty()
yield delay(100)
@ -333,8 +287,8 @@ def bench():
test_frame1.user = 1
for wait in wait_normal,:
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
yield clk.posedge
@ -346,9 +300,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
lrx = len(rx_frame.data)
lt = len(test_frame1.data)
@ -357,16 +309,14 @@ def bench():
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame1.data[:lm]
hdr = hdr_sink_queue.get(False)
hdr = hdr_sink.recv()
assert hdr.data[0][0] == (lt < lmin)
assert hdr.data[0][1] == (lt > lmax)
assert hdr.data[0][2] == lrx
assert hdr.data[0][3] == lt
assert rx_frame.user[-1]
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
lrx = len(rx_frame.data)
lt = len(test_frame2.data)
@ -375,20 +325,20 @@ def bench():
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame2.data[:lm]
hdr = hdr_sink_queue.get(False)
hdr = hdr_sink.recv()
assert hdr.data[0][0] == (lt < lmin)
assert hdr.data[0][1] == (lt > lmax)
assert hdr.data[0][2] == lrx
assert hdr.data[0][3] == lt
assert sink_queue.empty()
assert hdr_sink_queue.empty()
assert sink.empty()
assert hdr_sink.empty()
yield delay(100)
raise StopSimulation
return dut, source, sink, hdr_sink, clkgen, check
return dut, source_logic, sink_logic, hdr_sink_logic, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))

53
lib/axis/tb/test_axis_frame_length_adjust_fifo.v
View File

@ -24,11 +24,14 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1 ns / 1 ps
`timescale 1ns / 1ps
/*
* Testbench for axis_frame_length_adjust_fifo
*/
module test_axis_frame_length_adjust_fifo;
// parameters
// Parameters
localparam DATA_WIDTH = 8;
localparam FRAME_FIFO_ADDR_WIDTH = 12;
localparam HEADER_FIFO_ADDR_WIDTH = 3;
@ -61,27 +64,31 @@ wire [15:0] output_axis_hdr_original_length;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_hdr_ready,
output_axis_tready,
length_min,
length_max);
$to_myhdl(input_axis_tready,
output_axis_hdr_valid,
output_axis_hdr_pad,
output_axis_hdr_truncate,
output_axis_hdr_length,
output_axis_hdr_original_length,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
$from_myhdl(
clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_hdr_ready,
output_axis_tready,
length_min,
length_max
);
$to_myhdl(
input_axis_tready,
output_axis_hdr_valid,
output_axis_hdr_pad,
output_axis_hdr_truncate,
output_axis_hdr_length,
output_axis_hdr_original_length,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser
);
// dump file
$dumpfile("test_axis_frame_length_adjust_fifo.lxt");

259
lib/axis/tb/test_axis_frame_length_adjust_fifo_64.py
View File

@ -26,14 +26,10 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_frame_length_adjust_fifo_64'
testbench = 'test_%s' % module
srcs = []
@ -41,78 +37,27 @@ srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/axis_frame_length_adjust.v")
srcs.append("../rtl/axis_fifo.v")
srcs.append("../rtl/axis_fifo_64.v")
srcs.append("test_%s.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_axis_frame_length_adjust_fifo_64(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_axis_hdr_valid,
output_axis_hdr_ready,
output_axis_hdr_pad,
output_axis_hdr_truncate,
output_axis_hdr_length,
output_axis_hdr_original_length,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
length_min,
length_max):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_hdr_valid=output_axis_hdr_valid,
output_axis_hdr_ready=output_axis_hdr_ready,
output_axis_hdr_pad=output_axis_hdr_pad,
output_axis_hdr_truncate=output_axis_hdr_truncate,
output_axis_hdr_length=output_axis_hdr_length,
output_axis_hdr_original_length=output_axis_hdr_original_length,
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser,
length_min=length_min,
length_max=length_max)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
DATA_WIDTH = 64
KEEP_WIDTH = (DATA_WIDTH/8)
FRAME_FIFO_ADDR_WIDTH = 9
HEADER_FIFO_ADDR_WIDTH = 3
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[64:])
input_axis_tkeep = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
@ -128,80 +73,92 @@ def bench():
output_axis_hdr_truncate = Signal(bool(0))
output_axis_hdr_length = Signal(intbv(0)[16:])
output_axis_hdr_original_length = Signal(intbv(0)[16:])
output_axis_tdata = Signal(intbv(0)[64:])
output_axis_tkeep = Signal(intbv(0)[8:])
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
hdr_sink_queue = Queue()
hdr_sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
source = axis_ep.AXIStreamSource()
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
source_logic = source.create_logic(
clk,
rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
pause=source_pause,
name='source'
)
hdr_sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=(output_axis_hdr_pad, output_axis_hdr_truncate, output_axis_hdr_length, output_axis_hdr_original_length),
tvalid=output_axis_hdr_valid,
tready=output_axis_hdr_ready,
fifo=hdr_sink_queue,
pause=hdr_sink_pause,
name='hdr_sink')
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink'
)
hdr_sink = axis_ep.AXIStreamSink()
hdr_sink_logic = hdr_sink.create_logic(
clk,
rst,
tdata=(output_axis_hdr_pad, output_axis_hdr_truncate, output_axis_hdr_length, output_axis_hdr_original_length),
tvalid=output_axis_hdr_valid,
tready=output_axis_hdr_ready,
pause=hdr_sink_pause,
name='hdr_sink'
)
# DUT
dut = dut_axis_frame_length_adjust_fifo_64(clk,
rst,
current_test,
if os.system(build_cmd):
raise Exception("Error running build command")
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
output_axis_hdr_valid,
output_axis_hdr_ready,
output_axis_hdr_pad,
output_axis_hdr_truncate,
output_axis_hdr_length,
output_axis_hdr_original_length,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
length_min,
length_max)
output_axis_hdr_valid=output_axis_hdr_valid,
output_axis_hdr_ready=output_axis_hdr_ready,
output_axis_hdr_pad=output_axis_hdr_pad,
output_axis_hdr_truncate=output_axis_hdr_truncate,
output_axis_hdr_length=output_axis_hdr_length,
output_axis_hdr_original_length=output_axis_hdr_original_length,
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser,
length_min=length_min,
length_max=length_max
)
@always(delay(4))
def clkgen():
@ -238,7 +195,7 @@ def bench():
test_frame = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
for wait in wait_normal,:
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield clk.posedge
yield clk.posedge
@ -252,9 +209,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
lrx = len(rx_frame.data)
lt = len(test_frame.data)
@ -263,14 +218,14 @@ def bench():
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame.data[:lm]
hdr = hdr_sink_queue.get(False)
hdr = hdr_sink.recv()
assert hdr.data[0][0] == (lt < lmin)
assert hdr.data[0][1] == (lt > lmax)
assert hdr.data[0][2] == lrx
assert hdr.data[0][3] == lt
assert sink_queue.empty()
assert hdr_sink_queue.empty()
assert sink.empty()
assert hdr_sink.empty()
yield delay(100)
@ -282,8 +237,8 @@ def bench():
test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
for wait in wait_normal,:
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
yield clk.posedge
@ -295,9 +250,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
lrx = len(rx_frame.data)
lt = len(test_frame1.data)
@ -306,15 +259,13 @@ def bench():
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame1.data[:lm]
hdr = hdr_sink_queue.get(False)
hdr = hdr_sink.recv()
assert hdr.data[0][0] == (lt < lmin)
assert hdr.data[0][1] == (lt > lmax)
assert hdr.data[0][2] == lrx
assert hdr.data[0][3] == lt
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
lrx = len(rx_frame.data)
lt = len(test_frame2.data)
@ -323,14 +274,14 @@ def bench():
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame2.data[:lm]
hdr = hdr_sink_queue.get(False)
hdr = hdr_sink.recv()
assert hdr.data[0][0] == (lt < lmin)
assert hdr.data[0][1] == (lt > lmax)
assert hdr.data[0][2] == lrx
assert hdr.data[0][3] == lt
assert sink_queue.empty()
assert hdr_sink_queue.empty()
assert sink.empty()
assert hdr_sink.empty()
yield delay(100)
@ -344,8 +295,8 @@ def bench():
test_frame1.user = 1
for wait in wait_normal,:
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
yield clk.posedge
@ -357,9 +308,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
lrx = len(rx_frame.data)
lt = len(test_frame1.data)
@ -368,16 +317,14 @@ def bench():
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame1.data[:lm]
hdr = hdr_sink_queue.get(False)
hdr = hdr_sink.recv()
assert hdr.data[0][0] == (lt < lmin)
assert hdr.data[0][1] == (lt > lmax)
assert hdr.data[0][2] == lrx
assert hdr.data[0][3] == lt
assert rx_frame.user[-1]
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
lrx = len(rx_frame.data)
lt = len(test_frame2.data)
@ -386,20 +333,20 @@ def bench():
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame2.data[:lm]
hdr = hdr_sink_queue.get(False)
hdr = hdr_sink.recv()
assert hdr.data[0][0] == (lt < lmin)
assert hdr.data[0][1] == (lt > lmax)
assert hdr.data[0][2] == lrx
assert hdr.data[0][3] == lt
assert sink_queue.empty()
assert hdr_sink_queue.empty()
assert sink.empty()
assert hdr_sink.empty()
yield delay(100)
raise StopSimulation
return dut, source, sink, hdr_sink, clkgen, check
return dut, source_logic, sink_logic, hdr_sink_logic, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))

57
lib/axis/tb/test_axis_frame_length_adjust_fifo_64.v
View File

@ -24,11 +24,14 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1 ns / 1 ps
`timescale 1ns / 1ps
/*
* Testbench for axis_frame_length_adjust_fifo_64
*/
module test_axis_frame_length_adjust_fifo_64;
// parameters
// Parameters
localparam DATA_WIDTH = 64;
localparam KEEP_WIDTH = (DATA_WIDTH/8);
localparam FRAME_FIFO_ADDR_WIDTH = 9;
@ -64,29 +67,33 @@ wire [15:0] output_axis_hdr_original_length;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_hdr_ready,
output_axis_tready,
length_min,
length_max);
$to_myhdl(input_axis_tready,
output_axis_hdr_valid,
output_axis_hdr_pad,
output_axis_hdr_truncate,
output_axis_hdr_length,
output_axis_hdr_original_length,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
$from_myhdl(
clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_hdr_ready,
output_axis_tready,
length_min,
length_max
);
$to_myhdl(
input_axis_tready,
output_axis_hdr_valid,
output_axis_hdr_pad,
output_axis_hdr_truncate,
output_axis_hdr_length,
output_axis_hdr_original_length,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser
);
// dump file
$dumpfile("test_axis_frame_length_adjust_fifo_64.lxt");

166
lib/axis/tb/test_axis_ll_bridge.py
View File

@ -26,119 +26,95 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
import ll_ep
module = 'axis_ll_bridge'
testbench = 'test_%s' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_axis_ll_bridge(clk,
rst,
current_test,
axis_tdata,
axis_tvalid,
axis_tready,
axis_tlast,
ll_data_out,
ll_sof_out_n,
ll_eof_out_n,
ll_src_rdy_out_n,
ll_dst_rdy_in_n):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
axis_tdata=axis_tdata,
axis_tvalid=axis_tvalid,
axis_tready=axis_tready,
axis_tlast=axis_tlast,
ll_data_out=ll_data_out,
ll_sof_out_n=ll_sof_out_n,
ll_eof_out_n=ll_eof_out_n,
ll_src_rdy_out_n=ll_src_rdy_out_n,
ll_dst_rdy_in_n=ll_dst_rdy_in_n)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
DATA_WIDTH = 8
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
axis_tdata = Signal(intbv(0)[8:])
axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
axis_tvalid = Signal(bool(0))
axis_tlast = Signal(bool(0))
ll_dst_rdy_in_n = Signal(bool(1))
# Outputs
ll_data_out = Signal(intbv(0)[8:])
ll_data_out = Signal(intbv(0)[DATA_WIDTH:])
ll_sof_out_n = Signal(bool(1))
ll_eof_out_n = Signal(bool(1))
ll_src_rdy_out_n = Signal(bool(1))
axis_tready = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=axis_tdata,
tvalid=axis_tvalid,
tready=axis_tready,
tlast=axis_tlast,
fifo=source_queue,
pause=source_pause,
name='source')
source = axis_ep.AXIStreamSource()
sink = ll_ep.LocalLinkSink(clk,
rst,
data_in=ll_data_out,
sof_in_n=ll_sof_out_n,
eof_in_n=ll_eof_out_n,
src_rdy_in_n=ll_src_rdy_out_n,
dst_rdy_out_n=ll_dst_rdy_in_n,
fifo=sink_queue,
pause=sink_pause,
name='sink')
source_logic = source.create_logic(
clk,
rst,
tdata=axis_tdata,
tvalid=axis_tvalid,
tready=axis_tready,
tlast=axis_tlast,
pause=source_pause,
name='source'
)
sink = ll_ep.LocalLinkSink()
sink_logic = sink.create_logic(
clk,
rst,
data_in=ll_data_out,
sof_in_n=ll_sof_out_n,
eof_in_n=ll_eof_out_n,
src_rdy_in_n=ll_src_rdy_out_n,
dst_rdy_out_n=ll_dst_rdy_in_n,
pause=sink_pause,
name='sink'
)
# DUT
dut = dut_axis_ll_bridge(clk,
rst,
current_test,
if os.system(build_cmd):
raise Exception("Error running build command")
axis_tdata,
axis_tvalid,
axis_tready,
axis_tlast,
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
ll_data_out,
ll_sof_out_n,
ll_eof_out_n,
ll_src_rdy_out_n,
ll_dst_rdy_in_n)
axis_tdata=axis_tdata,
axis_tvalid=axis_tvalid,
axis_tready=axis_tready,
axis_tlast=axis_tlast,
ll_data_out=ll_data_out,
ll_sof_out_n=ll_sof_out_n,
ll_eof_out_n=ll_eof_out_n,
ll_src_rdy_out_n=ll_src_rdy_out_n,
ll_dst_rdy_in_n=ll_dst_rdy_in_n
)
@always(delay(4))
def clkgen():
@ -161,24 +137,21 @@ def bench():
print("test 1: test packet")
current_test.next = 1
source_queue.put(bytearray(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'))
test_frame = bytearray(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source.send(test_frame)
yield clk.posedge
yield ll_eof_out_n.negedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert bytearray(rx_frame) == (b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
assert bytearray(rx_frame) == test_frame
yield delay(100)
@ -186,10 +159,12 @@ def bench():
print("test 2: test packet with pauses")
current_test.next = 2
source_queue.put(bytearray(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'))
test_frame = bytearray(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source.send(test_frame)
yield clk.posedge
yield delay(64)
@ -210,20 +185,15 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert bytearray(rx_frame) == (b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
assert bytearray(rx_frame) == test_frame
yield delay(100)
raise StopSimulation
return dut, source, sink, clkgen, check
return dut, source_logic, sink_logic, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))

50
lib/axis/tb/test_axis_ll_bridge.v
View File

@ -24,22 +24,28 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1 ns / 1 ps
`timescale 1ns / 1ps
/*
* Testbench for axis_ll_bridge
*/
module test_axis_ll_bridge;
// Parameters
parameter DATA_WIDTH = 8;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] axis_tdata = 8'd0;
reg axis_tvalid = 1'b0;
reg axis_tlast = 1'b0;
reg ll_dst_rdy_in_n = 1'b1;
reg [DATA_WIDTH-1:0] axis_tdata = 0;
reg axis_tvalid = 0;
reg axis_tlast = 0;
reg ll_dst_rdy_in_n = 1;
// Outputs
wire [7:0] ll_data_out;
wire [DATA_WIDTH-1:0] ll_data_out;
wire ll_sof_out_n;
wire ll_eof_out_n;
wire ll_src_rdy_out_n;
@ -47,25 +53,31 @@ wire axis_tready;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
axis_tdata,
axis_tvalid,
axis_tlast,
ll_dst_rdy_in_n);
$to_myhdl(ll_data_out,
ll_sof_out_n,
ll_eof_out_n,
ll_src_rdy_out_n,
axis_tready);
$from_myhdl(
clk,
rst,
current_test,
axis_tdata,
axis_tvalid,
axis_tlast,
ll_dst_rdy_in_n
);
$to_myhdl(
ll_data_out,
ll_sof_out_n,
ll_eof_out_n,
ll_src_rdy_out_n,
axis_tready
);
// dump file
$dumpfile("test_axis_ll_bridge.lxt");
$dumpvars(0, test_axis_ll_bridge);
end
axis_ll_bridge
axis_ll_bridge #(
.DATA_WIDTH(DATA_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),

345
lib/axis/tb/test_axis_mux_4.py
View File

@ -26,115 +26,43 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_mux_4'
testbench = 'test_%s' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_axis_mux_4(clk,
rst,
current_test,
input_0_axis_tdata,
input_0_axis_tvalid,
input_0_axis_tready,
input_0_axis_tlast,
input_0_axis_tuser,
input_1_axis_tdata,
input_1_axis_tvalid,
input_1_axis_tready,
input_1_axis_tlast,
input_1_axis_tuser,
input_2_axis_tdata,
input_2_axis_tvalid,
input_2_axis_tready,
input_2_axis_tlast,
input_2_axis_tuser,
input_3_axis_tdata,
input_3_axis_tvalid,
input_3_axis_tready,
input_3_axis_tlast,
input_3_axis_tuser,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
enable,
select):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_0_axis_tdata=input_0_axis_tdata,
input_0_axis_tvalid=input_0_axis_tvalid,
input_0_axis_tready=input_0_axis_tready,
input_0_axis_tlast=input_0_axis_tlast,
input_0_axis_tuser=input_0_axis_tuser,
input_1_axis_tdata=input_1_axis_tdata,
input_1_axis_tvalid=input_1_axis_tvalid,
input_1_axis_tready=input_1_axis_tready,
input_1_axis_tlast=input_1_axis_tlast,
input_1_axis_tuser=input_1_axis_tuser,
input_2_axis_tdata=input_2_axis_tdata,
input_2_axis_tvalid=input_2_axis_tvalid,
input_2_axis_tready=input_2_axis_tready,
input_2_axis_tlast=input_2_axis_tlast,
input_2_axis_tuser=input_2_axis_tuser,
input_3_axis_tdata=input_3_axis_tdata,
input_3_axis_tvalid=input_3_axis_tvalid,
input_3_axis_tready=input_3_axis_tready,
input_3_axis_tlast=input_3_axis_tlast,
input_3_axis_tuser=input_3_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser,
enable=enable,
select=select)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
DATA_WIDTH = 8
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_0_axis_tdata = Signal(intbv(0)[8:])
input_0_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_0_axis_tvalid = Signal(bool(0))
input_0_axis_tlast = Signal(bool(0))
input_0_axis_tuser = Signal(bool(0))
input_1_axis_tdata = Signal(intbv(0)[8:])
input_1_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_1_axis_tvalid = Signal(bool(0))
input_1_axis_tlast = Signal(bool(0))
input_1_axis_tuser = Signal(bool(0))
input_2_axis_tdata = Signal(intbv(0)[8:])
input_2_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_2_axis_tvalid = Signal(bool(0))
input_2_axis_tlast = Signal(bool(0))
input_2_axis_tuser = Signal(bool(0))
input_3_axis_tdata = Signal(intbv(0)[8:])
input_3_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_3_axis_tvalid = Signal(bool(0))
input_3_axis_tlast = Signal(bool(0))
input_3_axis_tuser = Signal(bool(0))
@ -150,109 +78,128 @@ def bench():
input_2_axis_tready = Signal(bool(0))
input_3_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[8:])
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
# sources and sinks
source_0_queue = Queue()
source_0_pause = Signal(bool(0))
source_1_queue = Queue()
source_1_pause = Signal(bool(0))
source_2_queue = Queue()
source_2_pause = Signal(bool(0))
source_3_queue = Queue()
source_3_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source_0 = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_0_axis_tdata,
tvalid=input_0_axis_tvalid,
tready=input_0_axis_tready,
tlast=input_0_axis_tlast,
tuser=input_0_axis_tuser,
fifo=source_0_queue,
pause=source_0_pause,
name='source0')
source_1 = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_1_axis_tdata,
tvalid=input_1_axis_tvalid,
tready=input_1_axis_tready,
tlast=input_1_axis_tlast,
tuser=input_1_axis_tuser,
fifo=source_1_queue,
pause=source_1_pause,
name='source1')
source_2 = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_2_axis_tdata,
tvalid=input_2_axis_tvalid,
tready=input_2_axis_tready,
tlast=input_2_axis_tlast,
tuser=input_2_axis_tuser,
fifo=source_2_queue,
pause=source_2_pause,
name='source2')
source_3 = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_3_axis_tdata,
tvalid=input_3_axis_tvalid,
tready=input_3_axis_tready,
tlast=input_3_axis_tlast,
tuser=input_3_axis_tuser,
fifo=source_3_queue,
pause=source_3_pause,
name='source3')
source_0 = axis_ep.AXIStreamSource()
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
source_0_logic = source_0.create_logic(
clk,
rst,
tdata=input_0_axis_tdata,
tvalid=input_0_axis_tvalid,
tready=input_0_axis_tready,
tlast=input_0_axis_tlast,
tuser=input_0_axis_tuser,
pause=source_0_pause,
name='source_0'
)
source_1 = axis_ep.AXIStreamSource()
source_1_logic = source_1.create_logic(
clk,
rst,
tdata=input_1_axis_tdata,
tvalid=input_1_axis_tvalid,
tready=input_1_axis_tready,
tlast=input_1_axis_tlast,
tuser=input_1_axis_tuser,
pause=source_1_pause,
name='source_1'
)
source_2 = axis_ep.AXIStreamSource()
source_2_logic = source_2.create_logic(
clk,
rst,
tdata=input_2_axis_tdata,
tvalid=input_2_axis_tvalid,
tready=input_2_axis_tready,
tlast=input_2_axis_tlast,
tuser=input_2_axis_tuser,
pause=source_2_pause,
name='source_2'
)
source_3 = axis_ep.AXIStreamSource()
source_3_logic = source_3.create_logic(
clk,
rst,
tdata=input_3_axis_tdata,
tvalid=input_3_axis_tvalid,
tready=input_3_axis_tready,
tlast=input_3_axis_tlast,
tuser=input_3_axis_tuser,
pause=source_3_pause,
name='source_3'
)
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink'
)
# DUT
dut = dut_axis_mux_4(clk,
rst,
current_test,
if os.system(build_cmd):
raise Exception("Error running build command")
input_0_axis_tdata,
input_0_axis_tvalid,
input_0_axis_tready,
input_0_axis_tlast,
input_0_axis_tuser,
input_1_axis_tdata,
input_1_axis_tvalid,
input_1_axis_tready,
input_1_axis_tlast,
input_1_axis_tuser,
input_2_axis_tdata,
input_2_axis_tvalid,
input_2_axis_tready,
input_2_axis_tlast,
input_2_axis_tuser,
input_3_axis_tdata,
input_3_axis_tvalid,
input_3_axis_tready,
input_3_axis_tlast,
input_3_axis_tuser,
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
input_0_axis_tdata=input_0_axis_tdata,
input_0_axis_tvalid=input_0_axis_tvalid,
input_0_axis_tready=input_0_axis_tready,
input_0_axis_tlast=input_0_axis_tlast,
input_0_axis_tuser=input_0_axis_tuser,
input_1_axis_tdata=input_1_axis_tdata,
input_1_axis_tvalid=input_1_axis_tvalid,
input_1_axis_tready=input_1_axis_tready,
input_1_axis_tlast=input_1_axis_tlast,
input_1_axis_tuser=input_1_axis_tuser,
input_2_axis_tdata=input_2_axis_tdata,
input_2_axis_tvalid=input_2_axis_tvalid,
input_2_axis_tready=input_2_axis_tready,
input_2_axis_tlast=input_2_axis_tlast,
input_2_axis_tuser=input_2_axis_tuser,
input_3_axis_tdata=input_3_axis_tdata,
input_3_axis_tvalid=input_3_axis_tvalid,
input_3_axis_tready=input_3_axis_tready,
input_3_axis_tlast=input_3_axis_tlast,
input_3_axis_tuser=input_3_axis_tuser,
enable,
select)
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser,
enable=enable,
select=select
)
@always(delay(4))
def clkgen():
@ -282,7 +229,7 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_0_queue.put(test_frame)
source_0.send(test_frame)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
@ -290,9 +237,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -308,7 +253,7 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_1_queue.put(test_frame)
source_1.send(test_frame)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
@ -316,9 +261,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -338,8 +281,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_0_queue.put(test_frame1)
source_0_queue.put(test_frame2)
source_0.send(test_frame1)
source_0.send(test_frame2)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
@ -347,15 +290,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -375,8 +314,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_1_queue.put(test_frame1)
source_2_queue.put(test_frame2)
source_1.send(test_frame1)
source_2.send(test_frame2)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
@ -385,15 +324,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -413,8 +348,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_1_queue.put(test_frame1)
source_2_queue.put(test_frame2)
source_1.send(test_frame1)
source_2.send(test_frame2)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
@ -434,15 +369,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -462,8 +393,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_1_queue.put(test_frame1)
source_2_queue.put(test_frame2)
source_1.send(test_frame1)
source_2.send(test_frame2)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
@ -477,15 +408,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -493,7 +420,7 @@ def bench():
raise StopSimulation
return dut, source_0, source_1, source_2, source_3, sink, clkgen, check
return dut, source_0_logic, source_1_logic, source_2_logic, source_3_logic, sink_logic, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))

84
lib/axis/tb/test_axis_mux_4.v
View File

@ -24,28 +24,34 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1 ns / 1 ps
`timescale 1ns / 1ps
/*
* Testbench for axis_mux_4
*/
module test_axis_mux_4;
// Parameters
parameter DATA_WIDTH = 8;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] input_0_axis_tdata = 0;
reg [DATA_WIDTH-1:0] input_0_axis_tdata = 0;
reg input_0_axis_tvalid = 0;
reg input_0_axis_tlast = 0;
reg input_0_axis_tuser = 0;
reg [7:0] input_1_axis_tdata = 0;
reg [DATA_WIDTH-1:0] input_1_axis_tdata = 0;
reg input_1_axis_tvalid = 0;
reg input_1_axis_tlast = 0;
reg input_1_axis_tuser = 0;
reg [7:0] input_2_axis_tdata = 0;
reg [DATA_WIDTH-1:0] input_2_axis_tdata = 0;
reg input_2_axis_tvalid = 0;
reg input_2_axis_tlast = 0;
reg input_2_axis_tuser = 0;
reg [7:0] input_3_axis_tdata = 0;
reg [DATA_WIDTH-1:0] input_3_axis_tdata = 0;
reg input_3_axis_tvalid = 0;
reg input_3_axis_tlast = 0;
reg input_3_axis_tuser = 0;
@ -61,43 +67,47 @@ wire input_1_axis_tready;
wire input_2_axis_tready;
wire input_3_axis_tready;
wire [7:0] output_axis_tdata;
wire [DATA_WIDTH-1:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_0_axis_tdata,
input_0_axis_tvalid,
input_0_axis_tlast,
input_0_axis_tuser,
input_1_axis_tdata,
input_1_axis_tvalid,
input_1_axis_tlast,
input_1_axis_tuser,
input_2_axis_tdata,
input_2_axis_tvalid,
input_2_axis_tlast,
input_2_axis_tuser,
input_3_axis_tdata,
input_3_axis_tvalid,
input_3_axis_tlast,
input_3_axis_tuser,
output_axis_tready,
enable,
select);
$to_myhdl(input_0_axis_tready,
input_1_axis_tready,
input_2_axis_tready,
input_3_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
$from_myhdl(
clk,
rst,
current_test,
input_0_axis_tdata,
input_0_axis_tvalid,
input_0_axis_tlast,
input_0_axis_tuser,
input_1_axis_tdata,
input_1_axis_tvalid,
input_1_axis_tlast,
input_1_axis_tuser,
input_2_axis_tdata,
input_2_axis_tvalid,
input_2_axis_tlast,
input_2_axis_tuser,
input_3_axis_tdata,
input_3_axis_tvalid,
input_3_axis_tlast,
input_3_axis_tuser,
output_axis_tready,
enable,
select
);
$to_myhdl(
input_0_axis_tready,
input_1_axis_tready,
input_2_axis_tready,
input_3_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser
);
// dump file
$dumpfile("test_axis_mux_4.lxt");
@ -105,7 +115,7 @@ initial begin
end
axis_mux_4 #(
.DATA_WIDTH(8)
.DATA_WIDTH(DATA_WIDTH)
)
UUT (
.clk(clk),

386
lib/axis/tb/test_axis_mux_64_4.py
View File

@ -26,129 +26,48 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_mux_64_4'
testbench = 'test_%s' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_axis_mux_64_4(clk,
rst,
current_test,
input_0_axis_tdata,
input_0_axis_tkeep,
input_0_axis_tvalid,
input_0_axis_tready,
input_0_axis_tlast,
input_0_axis_tuser,
input_1_axis_tdata,
input_1_axis_tkeep,
input_1_axis_tvalid,
input_1_axis_tready,
input_1_axis_tlast,
input_1_axis_tuser,
input_2_axis_tdata,
input_2_axis_tkeep,
input_2_axis_tvalid,
input_2_axis_tready,
input_2_axis_tlast,
input_2_axis_tuser,
input_3_axis_tdata,
input_3_axis_tkeep,
input_3_axis_tvalid,
input_3_axis_tready,
input_3_axis_tlast,
input_3_axis_tuser,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
enable,
select):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_0_axis_tdata=input_0_axis_tdata,
input_0_axis_tkeep=input_0_axis_tkeep,
input_0_axis_tvalid=input_0_axis_tvalid,
input_0_axis_tready=input_0_axis_tready,
input_0_axis_tlast=input_0_axis_tlast,
input_0_axis_tuser=input_0_axis_tuser,
input_1_axis_tdata=input_1_axis_tdata,
input_1_axis_tkeep=input_1_axis_tkeep,
input_1_axis_tvalid=input_1_axis_tvalid,
input_1_axis_tready=input_1_axis_tready,
input_1_axis_tlast=input_1_axis_tlast,
input_1_axis_tuser=input_1_axis_tuser,
input_2_axis_tdata=input_2_axis_tdata,
input_2_axis_tkeep=input_2_axis_tkeep,
input_2_axis_tvalid=input_2_axis_tvalid,
input_2_axis_tready=input_2_axis_tready,
input_2_axis_tlast=input_2_axis_tlast,
input_2_axis_tuser=input_2_axis_tuser,
input_3_axis_tdata=input_3_axis_tdata,
input_3_axis_tkeep=input_3_axis_tkeep,
input_3_axis_tvalid=input_3_axis_tvalid,
input_3_axis_tready=input_3_axis_tready,
input_3_axis_tlast=input_3_axis_tlast,
input_3_axis_tuser=input_3_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser,
enable=enable,
select=select)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
DATA_WIDTH = 64
KEEP_WIDTH = (DATA_WIDTH/8)
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_0_axis_tdata = Signal(intbv(0)[64:])
input_0_axis_tkeep = Signal(intbv(0)[8:])
input_0_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_0_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
input_0_axis_tvalid = Signal(bool(0))
input_0_axis_tlast = Signal(bool(0))
input_0_axis_tuser = Signal(bool(0))
input_1_axis_tdata = Signal(intbv(0)[64:])
input_1_axis_tkeep = Signal(intbv(0)[8:])
input_1_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_1_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
input_1_axis_tvalid = Signal(bool(0))
input_1_axis_tlast = Signal(bool(0))
input_1_axis_tuser = Signal(bool(0))
input_2_axis_tdata = Signal(intbv(0)[64:])
input_2_axis_tkeep = Signal(intbv(0)[8:])
input_2_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_2_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
input_2_axis_tvalid = Signal(bool(0))
input_2_axis_tlast = Signal(bool(0))
input_2_axis_tuser = Signal(bool(0))
input_3_axis_tdata = Signal(intbv(0)[64:])
input_3_axis_tkeep = Signal(intbv(0)[8:])
input_3_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_3_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
input_3_axis_tvalid = Signal(bool(0))
input_3_axis_tlast = Signal(bool(0))
input_3_axis_tuser = Signal(bool(0))
@ -164,120 +83,139 @@ def bench():
input_2_axis_tready = Signal(bool(0))
input_3_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[64:])
output_axis_tkeep = Signal(intbv(0)[8:])
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
# sources and sinks
source_0_queue = Queue()
source_0_pause = Signal(bool(0))
source_1_queue = Queue()
source_1_pause = Signal(bool(0))
source_2_queue = Queue()
source_2_pause = Signal(bool(0))
source_3_queue = Queue()
source_3_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source_0 = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_0_axis_tdata,
tkeep=input_0_axis_tkeep,
tvalid=input_0_axis_tvalid,
tready=input_0_axis_tready,
tlast=input_0_axis_tlast,
tuser=input_0_axis_tuser,
fifo=source_0_queue,
pause=source_0_pause,
name='source0')
source_1 = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_1_axis_tdata,
tkeep=input_1_axis_tkeep,
tvalid=input_1_axis_tvalid,
tready=input_1_axis_tready,
tlast=input_1_axis_tlast,
tuser=input_1_axis_tuser,
fifo=source_1_queue,
pause=source_1_pause,
name='source1')
source_2 = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_2_axis_tdata,
tkeep=input_2_axis_tkeep,
tvalid=input_2_axis_tvalid,
tready=input_2_axis_tready,
tlast=input_2_axis_tlast,
tuser=input_2_axis_tuser,
fifo=source_2_queue,
pause=source_2_pause,
name='source2')
source_3 = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_3_axis_tdata,
tkeep=input_3_axis_tkeep,
tvalid=input_3_axis_tvalid,
tready=input_3_axis_tready,
tlast=input_3_axis_tlast,
tuser=input_3_axis_tuser,
fifo=source_3_queue,
pause=source_3_pause,
name='source3')
source_0 = axis_ep.AXIStreamSource()
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
source_0_logic = source_0.create_logic(
clk,
rst,
tdata=input_0_axis_tdata,
tkeep=input_0_axis_tkeep,
tvalid=input_0_axis_tvalid,
tready=input_0_axis_tready,
tlast=input_0_axis_tlast,
tuser=input_0_axis_tuser,
pause=source_0_pause,
name='source_0'
)
source_1 = axis_ep.AXIStreamSource()
source_1_logic = source_1.create_logic(
clk,
rst,
tdata=input_1_axis_tdata,
tkeep=input_1_axis_tkeep,
tvalid=input_1_axis_tvalid,
tready=input_1_axis_tready,
tlast=input_1_axis_tlast,
tuser=input_1_axis_tuser,
pause=source_1_pause,
name='source_1'
)
source_2 = axis_ep.AXIStreamSource()
source_2_logic = source_2.create_logic(
clk,
rst,
tdata=input_2_axis_tdata,
tkeep=input_2_axis_tkeep,
tvalid=input_2_axis_tvalid,
tready=input_2_axis_tready,
tlast=input_2_axis_tlast,
tuser=input_2_axis_tuser,
pause=source_2_pause,
name='source_2'
)
source_3 = axis_ep.AXIStreamSource()
source_3_logic = source_3.create_logic(
clk,
rst,
tdata=input_3_axis_tdata,
tkeep=input_3_axis_tkeep,
tvalid=input_3_axis_tvalid,
tready=input_3_axis_tready,
tlast=input_3_axis_tlast,
tuser=input_3_axis_tuser,
pause=source_3_pause,
name='source_3'
)
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink'
)
# DUT
dut = dut_axis_mux_64_4(clk,
rst,
current_test,
if os.system(build_cmd):
raise Exception("Error running build command")
input_0_axis_tdata,
input_0_axis_tkeep,
input_0_axis_tvalid,
input_0_axis_tready,
input_0_axis_tlast,
input_0_axis_tuser,
input_1_axis_tdata,
input_1_axis_tkeep,
input_1_axis_tvalid,
input_1_axis_tready,
input_1_axis_tlast,
input_1_axis_tuser,
input_2_axis_tdata,
input_2_axis_tkeep,
input_2_axis_tvalid,
input_2_axis_tready,
input_2_axis_tlast,
input_2_axis_tuser,
input_3_axis_tdata,
input_3_axis_tkeep,
input_3_axis_tvalid,
input_3_axis_tready,
input_3_axis_tlast,
input_3_axis_tuser,
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
input_0_axis_tdata=input_0_axis_tdata,
input_0_axis_tkeep=input_0_axis_tkeep,
input_0_axis_tvalid=input_0_axis_tvalid,
input_0_axis_tready=input_0_axis_tready,
input_0_axis_tlast=input_0_axis_tlast,
input_0_axis_tuser=input_0_axis_tuser,
input_1_axis_tdata=input_1_axis_tdata,
input_1_axis_tkeep=input_1_axis_tkeep,
input_1_axis_tvalid=input_1_axis_tvalid,
input_1_axis_tready=input_1_axis_tready,
input_1_axis_tlast=input_1_axis_tlast,
input_1_axis_tuser=input_1_axis_tuser,
input_2_axis_tdata=input_2_axis_tdata,
input_2_axis_tkeep=input_2_axis_tkeep,
input_2_axis_tvalid=input_2_axis_tvalid,
input_2_axis_tready=input_2_axis_tready,
input_2_axis_tlast=input_2_axis_tlast,
input_2_axis_tuser=input_2_axis_tuser,
input_3_axis_tdata=input_3_axis_tdata,
input_3_axis_tkeep=input_3_axis_tkeep,
input_3_axis_tvalid=input_3_axis_tvalid,
input_3_axis_tready=input_3_axis_tready,
input_3_axis_tlast=input_3_axis_tlast,
input_3_axis_tuser=input_3_axis_tuser,
enable,
select)
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser,
enable=enable,
select=select
)
@always(delay(4))
def clkgen():
@ -307,7 +245,7 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_0_queue.put(test_frame)
source_0.send(test_frame)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
@ -315,9 +253,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -333,7 +269,7 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_1_queue.put(test_frame)
source_1.send(test_frame)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
@ -341,9 +277,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -363,8 +297,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_0_queue.put(test_frame1)
source_0_queue.put(test_frame2)
source_0.send(test_frame1)
source_0.send(test_frame2)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
@ -372,15 +306,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -400,8 +330,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_1_queue.put(test_frame1)
source_2_queue.put(test_frame2)
source_1.send(test_frame1)
source_2.send(test_frame2)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
@ -410,15 +340,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -438,8 +364,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_1_queue.put(test_frame1)
source_2_queue.put(test_frame2)
source_1.send(test_frame1)
source_2.send(test_frame2)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
@ -459,15 +385,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -487,8 +409,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_1_queue.put(test_frame1)
source_2_queue.put(test_frame2)
source_1.send(test_frame1)
source_2.send(test_frame2)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
@ -502,15 +424,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -518,7 +436,7 @@ def bench():
raise StopSimulation
return dut, source_0, source_1, source_2, source_3, sink, clkgen, check
return dut, source_0_logic, source_1_logic, source_2_logic, source_3_logic, sink_logic, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))

106
lib/axis/tb/test_axis_mux_64_4.v
View File

@ -24,32 +24,39 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1 ns / 1 ps
`timescale 1ns / 1ps
/*
* Testbench for axis_mux_64_4
*/
module test_axis_mux_64_4;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_WIDTH = (DATA_WIDTH/8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [63:0] input_0_axis_tdata = 0;
reg [7:0] input_0_axis_tkeep = 0;
reg [DATA_WIDTH-1:0] input_0_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_0_axis_tkeep = 0;
reg input_0_axis_tvalid = 0;
reg input_0_axis_tlast = 0;
reg input_0_axis_tuser = 0;
reg [63:0] input_1_axis_tdata = 0;
reg [7:0] input_1_axis_tkeep = 0;
reg [DATA_WIDTH-1:0] input_1_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_1_axis_tkeep = 0;
reg input_1_axis_tvalid = 0;
reg input_1_axis_tlast = 0;
reg input_1_axis_tuser = 0;
reg [63:0] input_2_axis_tdata = 0;
reg [7:0] input_2_axis_tkeep = 0;
reg [DATA_WIDTH-1:0] input_2_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_2_axis_tkeep = 0;
reg input_2_axis_tvalid = 0;
reg input_2_axis_tlast = 0;
reg input_2_axis_tuser = 0;
reg [63:0] input_3_axis_tdata = 0;
reg [7:0] input_3_axis_tkeep = 0;
reg [DATA_WIDTH-1:0] input_3_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_3_axis_tkeep = 0;
reg input_3_axis_tvalid = 0;
reg input_3_axis_tlast = 0;
reg input_3_axis_tuser = 0;
@ -65,49 +72,53 @@ wire input_1_axis_tready;
wire input_2_axis_tready;
wire input_3_axis_tready;
wire [63:0] output_axis_tdata;
wire [7:0] output_axis_tkeep;
wire [DATA_WIDTH-1:0] output_axis_tdata;
wire [KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_0_axis_tdata,
input_0_axis_tkeep,
input_0_axis_tvalid,
input_0_axis_tlast,
input_0_axis_tuser,
input_1_axis_tdata,
input_1_axis_tkeep,
input_1_axis_tvalid,
input_1_axis_tlast,
input_1_axis_tuser,
input_2_axis_tdata,
input_2_axis_tkeep,
input_2_axis_tvalid,
input_2_axis_tlast,
input_2_axis_tuser,
input_3_axis_tdata,
input_3_axis_tkeep,
input_3_axis_tvalid,
input_3_axis_tlast,
input_3_axis_tuser,
output_axis_tready,
enable,
select);
$to_myhdl(input_0_axis_tready,
input_1_axis_tready,
input_2_axis_tready,
input_3_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
$from_myhdl(
clk,
rst,
current_test,
input_0_axis_tdata,
input_0_axis_tkeep,
input_0_axis_tvalid,
input_0_axis_tlast,
input_0_axis_tuser,
input_1_axis_tdata,
input_1_axis_tkeep,
input_1_axis_tvalid,
input_1_axis_tlast,
input_1_axis_tuser,
input_2_axis_tdata,
input_2_axis_tkeep,
input_2_axis_tvalid,
input_2_axis_tlast,
input_2_axis_tuser,
input_3_axis_tdata,
input_3_axis_tkeep,
input_3_axis_tvalid,
input_3_axis_tlast,
input_3_axis_tuser,
output_axis_tready,
enable,
select
);
$to_myhdl(
input_0_axis_tready,
input_1_axis_tready,
input_2_axis_tready,
input_3_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser
);
// dump file
$dumpfile("test_axis_mux_64_4.lxt");
@ -115,7 +126,8 @@ initial begin
end
axis_mux_64_4 #(
.DATA_WIDTH(64)
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH)
)
UUT (
.clk(clk),

214
lib/axis/tb/test_axis_rate_limit.py
View File

@ -26,75 +26,31 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_rate_limit'
testbench = 'test_%s' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_axis_rate_limit(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
rate_num,
rate_denom,
rate_by_frame):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser,
rate_num=rate_num,
rate_denom=rate_denom,
rate_by_frame=rate_by_frame)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
DATA_WIDTH = 8
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
@ -106,59 +62,69 @@ def bench():
# Outputs
input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[8:])
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_axis_tdata,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
source = axis_ep.AXIStreamSource()
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
source_logic = source.create_logic(
clk,
rst,
tdata=input_axis_tdata,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
pause=source_pause,
name='source'
)
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink'
)
# DUT
dut = dut_axis_rate_limit(clk,
rst,
current_test,
if os.system(build_cmd):
raise Exception("Error running build command")
input_axis_tdata,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
input_axis_tdata=input_axis_tdata,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
rate_num,
rate_denom,
rate_by_frame)
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser,
rate_num=rate_num,
rate_denom=rate_denom,
rate_by_frame=rate_by_frame
)
@always(delay(4))
def clkgen():
@ -223,7 +189,7 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -232,9 +198,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -248,7 +212,7 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -257,9 +221,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -271,7 +233,7 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield delay(64)
@ -294,9 +256,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -314,8 +274,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -324,15 +284,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -350,8 +306,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -368,15 +324,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -394,8 +346,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -412,15 +364,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -435,7 +383,7 @@ def bench():
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame.user = 1
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -444,9 +392,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
assert rx_frame.user[-1]
@ -476,7 +422,7 @@ def bench():
bytearray(range(lens[i]))))
for f in test_frame:
source_queue.put(f)
source.send(f)
yield clk.posedge
yield clk.posedge
@ -490,8 +436,8 @@ def bench():
rx_frame = []
for i in range(len(lens)):
if not sink_queue.empty():
rx_frame.append(sink_queue.get())
if not sink.empty():
rx_frame.append(sink.recv())
assert len(rx_frame) == len(test_frame)
@ -523,7 +469,7 @@ def bench():
raise StopSimulation
return dut, source, sink, clkgen, monitor, check
return dut, source_logic, sink_logic, clkgen, monitor, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))

58
lib/axis/tb/test_axis_rate_limit.v
View File

@ -24,49 +24,59 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1 ns / 1 ps
`timescale 1ns / 1ps
/*
* Testbench for axis_rate_limit
*/
module test_axis_rate_limit;
// Parameters
parameter DATA_WIDTH = 8;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] input_axis_tdata = 8'd0;
reg input_axis_tvalid = 1'b0;
reg input_axis_tlast = 1'b0;
reg input_axis_tuser = 1'b0;
reg output_axis_tready = 1'b0;
reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_axis_tready = 0;
reg [7:0] rate_num = 0;
reg [7:0] rate_denom = 0;
reg rate_by_frame = 0;
// Outputs
wire input_axis_tready;
wire [7:0] output_axis_tdata;
wire [DATA_WIDTH-1:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready,
rate_num,
rate_denom,
rate_by_frame);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
$from_myhdl(
clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready,
rate_num,
rate_denom,
rate_by_frame
);
$to_myhdl(
input_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser
);
// dump file
$dumpfile("test_axis_rate_limit.lxt");
@ -74,7 +84,7 @@ initial begin
end
axis_rate_limit #(
.DATA_WIDTH(8)
.DATA_WIDTH(DATA_WIDTH)
)
UUT (
.clk(clk),

231
lib/axis/tb/test_axis_rate_limit_64.py
View File

@ -26,80 +26,33 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_rate_limit_64'
testbench = 'test_%s' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_axis_rate_limit_64(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
rate_num,
rate_denom,
rate_by_frame):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser,
rate_num=rate_num,
rate_denom=rate_denom,
rate_by_frame=rate_by_frame)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
DATA_WIDTH = 64
KEEP_WIDTH = (DATA_WIDTH/8)
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[64:])
input_axis_tkeep = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
@ -111,64 +64,74 @@ def bench():
# Outputs
input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[64:])
output_axis_tkeep = Signal(intbv(0)[8:])
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
source = axis_ep.AXIStreamSource()
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
source_logic = source.create_logic(
clk,
rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
pause=source_pause,
name='source'
)
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink'
)
# DUT
dut = dut_axis_rate_limit_64(clk,
rst,
current_test,
if os.system(build_cmd):
raise Exception("Error running build command")
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
rate_num,
rate_denom,
rate_by_frame)
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser,
rate_num=rate_num,
rate_denom=rate_denom,
rate_by_frame=rate_by_frame
)
@always(delay(4))
def clkgen():
@ -233,7 +196,7 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -242,9 +205,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -258,7 +219,7 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -267,9 +228,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -281,7 +240,7 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield delay(64)
@ -304,9 +263,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -324,8 +281,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -334,15 +291,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -360,8 +313,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -378,15 +331,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -404,8 +353,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -422,15 +371,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -445,7 +390,7 @@ def bench():
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame.user = 1
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -454,9 +399,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
assert rx_frame.user[-1]
@ -486,7 +429,7 @@ def bench():
bytearray(range(lens[i]))))
for f in test_frame:
source_queue.put(f)
source.send(f)
yield clk.posedge
yield clk.posedge
@ -500,8 +443,8 @@ def bench():
rx_frame = []
for i in range(len(lens)):
if not sink_queue.empty():
rx_frame.append(sink_queue.get())
if not sink.empty():
rx_frame.append(sink.recv())
assert len(rx_frame) == len(test_frame)
@ -533,7 +476,7 @@ def bench():
raise StopSimulation
return dut, source, sink, clkgen, monitor, check
return dut, source_logic, sink_logic, clkgen, monitor, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))

68
lib/axis/tb/test_axis_rate_limit_64.v
View File

@ -24,53 +24,64 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1 ns / 1 ps
`timescale 1ns / 1ps
/*
* Testbench for axis_rate_limit_64
*/
module test_axis_rate_limit_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_WIDTH = (DATA_WIDTH/8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [63:0] input_axis_tdata = 8'd0;
reg [7:0] input_axis_tkeep = 8'd0;
reg input_axis_tvalid = 1'b0;
reg input_axis_tlast = 1'b0;
reg input_axis_tuser = 1'b0;
reg output_axis_tready = 1'b0;
reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_axis_tready = 0;
reg [7:0] rate_num = 0;
reg [7:0] rate_denom = 0;
reg rate_by_frame = 0;
// Outputs
wire input_axis_tready;
wire [63:0] output_axis_tdata;
wire [7:0] output_axis_tkeep;
wire [DATA_WIDTH-1:0] output_axis_tdata;
wire [KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready,
rate_num,
rate_denom,
rate_by_frame);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
$from_myhdl(
clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready,
rate_num,
rate_denom,
rate_by_frame
);
$to_myhdl(
input_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser
);
// dump file
$dumpfile("test_axis_rate_limit_64.lxt");
@ -78,7 +89,8 @@ initial begin
end
axis_rate_limit_64 #(
.DATA_WIDTH(64)
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH)
)
UUT (
.clk(clk),

190
lib/axis/tb/test_axis_register.py
View File

@ -26,61 +26,25 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_register'
testbench = 'test_%s' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_axis_register(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
DATA_WIDTH = 8
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
@ -100,49 +64,59 @@ def bench():
output_axis_tuser = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_axis_tdata,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
source = axis_ep.AXIStreamSource()
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
source_logic = source.create_logic(
clk,
rst,
tdata=input_axis_tdata,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
pause=source_pause,
name='source'
)
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink'
)
# DUT
dut = dut_axis_register(clk,
rst,
current_test,
if os.system(build_cmd):
raise Exception("Error running build command")
input_axis_tdata,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser)
input_axis_tdata=input_axis_tdata,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser
)
@always(delay(4))
def clkgen():
@ -169,16 +143,14 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -192,16 +164,14 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -213,7 +183,7 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield delay(64)
@ -234,9 +204,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -254,8 +222,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
yield output_axis_tlast.posedge
@ -264,15 +232,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -290,8 +254,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -305,15 +269,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -331,8 +291,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -346,15 +306,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -369,16 +325,14 @@ def bench():
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame.user = 1
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
assert rx_frame.user[-1]
@ -387,7 +341,7 @@ def bench():
raise StopSimulation
return dut, source, sink, clkgen, check
return dut, source_logic, sink_logic, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))

52
lib/axis/tb/test_axis_register.v
View File

@ -24,43 +24,53 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1 ns / 1 ps
`timescale 1ns / 1ps
/*
* Testbench for axis_register
*/
module test_axis_register;
// Parameters
parameter DATA_WIDTH = 8;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] input_axis_tdata = 8'd0;
reg input_axis_tvalid = 1'b0;
reg input_axis_tlast = 1'b0;
reg input_axis_tuser = 1'b0;
reg output_axis_tready = 1'b0;
reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_axis_tready = 0;
// Outputs
wire input_axis_tready;
wire [7:0] output_axis_tdata;
wire [DATA_WIDTH-1:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
$from_myhdl(
clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready
);
$to_myhdl(
input_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser
);
// dump file
$dumpfile("test_axis_register.lxt");
@ -68,7 +78,7 @@ initial begin
end
axis_register #(
.DATA_WIDTH(8)
.DATA_WIDTH(DATA_WIDTH)
)
UUT (
.clk(clk),

203
lib/axis/tb/test_axis_register_64.py
View File

@ -26,65 +26,26 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_register_64'
testbench = 'test_%s' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_axis_register_64(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
DATA_WIDTH = 64
KEEP_WIDTH = (DATA_WIDTH/8)
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
@ -106,53 +67,63 @@ def bench():
output_axis_tuser = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
source = axis_ep.AXIStreamSource()
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
source_logic = source.create_logic(
clk,
rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
pause=source_pause,
name='source'
)
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink'
)
# DUT
dut = dut_axis_register_64(clk,
rst,
current_test,
if os.system(build_cmd):
raise Exception("Error running build command")
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser)
input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser
)
@always(delay(4))
def clkgen():
@ -179,16 +150,14 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -202,16 +171,14 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -223,7 +190,7 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield delay(64)
@ -244,9 +211,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -264,8 +229,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
yield output_axis_tlast.posedge
@ -274,15 +239,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -300,8 +261,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -315,15 +276,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -341,8 +298,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -356,15 +313,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -379,16 +332,14 @@ def bench():
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame.user = 1
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
assert rx_frame.user[-1]
@ -397,7 +348,7 @@ def bench():
raise StopSimulation
return dut, source, sink, clkgen, check
return dut, source_logic, sink_logic, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))

62
lib/axis/tb/test_axis_register_64.v
View File

@ -24,47 +24,58 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1 ns / 1 ps
`timescale 1ns / 1ps
/*
* Testbench for axis_register_64
*/
module test_axis_register_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_WIDTH = (DATA_WIDTH/8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [63:0] input_axis_tdata = 8'd0;
reg [7:0] input_axis_tkeep = 8'd0;
reg input_axis_tvalid = 1'b0;
reg input_axis_tlast = 1'b0;
reg input_axis_tuser = 1'b0;
reg output_axis_tready = 1'b0;
reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_axis_tready = 0;
// Outputs
wire input_axis_tready;
wire [63:0] output_axis_tdata;
wire [7:0] output_axis_tkeep;
wire [DATA_WIDTH-1:0] output_axis_tdata;
wire [KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
$from_myhdl(
clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready
);
$to_myhdl(
input_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser
);
// dump file
$dumpfile("test_axis_register_64.lxt");
@ -72,7 +83,8 @@ initial begin
end
axis_register_64 #(
.DATA_WIDTH(64)
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH)
)
UUT (
.clk(clk),

211
lib/axis/tb/test_axis_srl_fifo.py
View File

@ -26,71 +26,32 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_srl_fifo'
testbench = 'test_%s' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_axis_srl_fifo(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
count):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser,
count=count)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
DEPTH = 4
DATA_WIDTH = 8
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
@ -98,7 +59,7 @@ def bench():
# Outputs
input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[8:])
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
@ -106,51 +67,61 @@ def bench():
count = Signal(intbv(0)[3:])
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_axis_tdata,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
source = axis_ep.AXIStreamSource()
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
source_logic = source.create_logic(
clk,
rst,
tdata=input_axis_tdata,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
pause=source_pause,
name='source'
)
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink'
)
# DUT
dut = dut_axis_srl_fifo(clk,
rst,
current_test,
if os.system(build_cmd):
raise Exception("Error running build command")
input_axis_tdata,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
input_axis_tdata=input_axis_tdata,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
count)
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser,
count=count
)
@always(delay(4))
def clkgen():
@ -177,16 +148,14 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -200,16 +169,14 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -221,7 +188,7 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield delay(64)
@ -242,9 +209,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -262,8 +227,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
yield output_axis_tlast.posedge
@ -272,15 +237,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -298,8 +259,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -313,15 +274,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -339,8 +296,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -354,15 +311,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -377,16 +330,14 @@ def bench():
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame.user = 1
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
assert rx_frame.user[-1]
@ -400,7 +351,7 @@ def bench():
test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
sink_pause.next = 1
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield clk.posedge
yield clk.posedge
@ -411,9 +362,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -426,7 +375,7 @@ def bench():
test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
sink_pause.next = 1
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield clk.posedge
yield clk.posedge
@ -444,13 +393,13 @@ def bench():
yield clk.posedge
yield clk.posedge
assert sink_queue.empty()
assert sink.empty()
yield delay(100)
raise StopSimulation
return dut, source, sink, clkgen, check
return dut, source_logic, sink_logic, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))

49
lib/axis/tb/test_axis_srl_fifo.v
View File

@ -24,16 +24,23 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1 ns / 1 ps
`timescale 1ns / 1ps
/*
* Testbench for axis_srl_fifo
*/
module test_axis_srl_fifo;
// Parameters
parameter DEPTH = 4;
parameter DATA_WIDTH = 8;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] input_axis_tdata = 0;
reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
@ -41,7 +48,7 @@ reg output_axis_tready = 0;
// Outputs
wire input_axis_tready;
wire [7:0] output_axis_tdata;
wire [DATA_WIDTH-1:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
@ -50,20 +57,24 @@ wire [2:0] count;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser,
count);
$from_myhdl(
clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready
);
$to_myhdl(
input_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser,
count
);
// dump file
$dumpfile("test_axis_srl_fifo.lxt");
@ -71,8 +82,8 @@ initial begin
end
axis_srl_fifo #(
.DEPTH(4),
.DATA_WIDTH(8)
.DEPTH(DEPTH),
.DATA_WIDTH(DATA_WIDTH)
)
UUT (
.clk(clk),

228
lib/axis/tb/test_axis_srl_fifo_64.py
View File

@ -26,76 +26,34 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_srl_fifo_64'
testbench = 'test_%s' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_axis_srl_fifo_64(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
count):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser,
count=count)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
DEPTH = 4
DATA_WIDTH = 64
KEEP_WIDTH = (DATA_WIDTH/8)
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[64:])
input_axis_tkeep = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
@ -103,8 +61,8 @@ def bench():
# Outputs
input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[64:])
output_axis_tkeep = Signal(intbv(0)[8:])
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
@ -112,55 +70,65 @@ def bench():
count = Signal(intbv(0)[3:])
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
source = axis_ep.AXIStreamSource()
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
source_logic = source.create_logic(
clk,
rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
pause=source_pause,
name='source'
)
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink'
)
# DUT
dut = dut_axis_srl_fifo_64(clk,
rst,
current_test,
if os.system(build_cmd):
raise Exception("Error running build command")
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
count)
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser,
count=count
)
@always(delay(4))
def clkgen():
@ -187,16 +155,14 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -210,16 +176,14 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -231,7 +195,7 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield delay(64)
@ -252,9 +216,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -272,8 +234,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
yield output_axis_tlast.posedge
@ -282,15 +244,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -308,8 +266,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -323,15 +281,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -349,8 +303,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -364,15 +318,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -387,16 +337,14 @@ def bench():
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame.user = 1
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
assert rx_frame.user[-1]
@ -410,7 +358,7 @@ def bench():
test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
sink_pause.next = 1
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield clk.posedge
yield clk.posedge
@ -421,9 +369,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -436,7 +382,7 @@ def bench():
test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
sink_pause.next = 1
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield clk.posedge
yield clk.posedge
@ -454,13 +400,13 @@ def bench():
yield clk.posedge
yield clk.posedge
assert sink_queue.empty()
assert sink.empty()
yield delay(100)
raise StopSimulation
return dut, source, sink, clkgen, check
return dut, source_logic, sink_logic, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))

59
lib/axis/tb/test_axis_srl_fifo_64.v
View File

@ -24,17 +24,25 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1 ns / 1 ps
`timescale 1ns / 1ps
/*
* Testbench for axis_srl_fifo_64
*/
module test_axis_srl_fifo_64;
// Parameters
parameter DEPTH = 4;
parameter DATA_WIDTH = 64;
parameter KEEP_WIDTH = (DATA_WIDTH/8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [63:0] input_axis_tdata = 0;
reg [7:0] input_axis_tkeep = 0;
reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
@ -42,8 +50,8 @@ reg output_axis_tready = 0;
// Outputs
wire input_axis_tready;
wire [63:0] output_axis_tdata;
wire [7:0] output_axis_tkeep;
wire [DATA_WIDTH-1:0] output_axis_tdata;
wire [KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
@ -52,22 +60,26 @@ wire [2:0] count;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser,
count);
$from_myhdl(
clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready
);
$to_myhdl(
input_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser,
count
);
// dump file
$dumpfile("test_axis_srl_fifo_64.lxt");
@ -75,8 +87,9 @@ initial begin
end
axis_srl_fifo_64 #(
.DEPTH(4),
.DATA_WIDTH(64)
.DEPTH(DEPTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH)
)
UUT (
.clk(clk),

190
lib/axis/tb/test_axis_srl_register.py
View File

@ -26,61 +26,25 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_srl_register'
testbench = 'test_%s' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_axis_srl_register(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
DATA_WIDTH = 8
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
@ -100,49 +64,59 @@ def bench():
output_axis_tuser = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_axis_tdata,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
source = axis_ep.AXIStreamSource()
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
source_logic = source.create_logic(
clk,
rst,
tdata=input_axis_tdata,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
pause=source_pause,
name='source'
)
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink'
)
# DUT
dut = dut_axis_srl_register(clk,
rst,
current_test,
if os.system(build_cmd):
raise Exception("Error running build command")
input_axis_tdata,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser)
input_axis_tdata=input_axis_tdata,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser
)
@always(delay(4))
def clkgen():
@ -169,16 +143,14 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -192,16 +164,14 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -213,7 +183,7 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield delay(64)
@ -234,9 +204,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -254,8 +222,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
yield output_axis_tlast.posedge
@ -264,15 +232,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -290,8 +254,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -305,15 +269,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -331,8 +291,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -346,15 +306,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -369,16 +325,14 @@ def bench():
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame.user = 1
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
assert rx_frame.user[-1]
@ -387,7 +341,7 @@ def bench():
raise StopSimulation
return dut, source, sink, clkgen, check
return dut, source_logic, sink_logic, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))

52
lib/axis/tb/test_axis_srl_register.v
View File

@ -24,43 +24,53 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1 ns / 1 ps
`timescale 1ns / 1ps
/*
* Testbench for axis_srl_register
*/
module test_axis_srl_register;
// Parameters
parameter DATA_WIDTH = 8;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] input_axis_tdata = 8'd0;
reg input_axis_tvalid = 1'b0;
reg input_axis_tlast = 1'b0;
reg input_axis_tuser = 1'b0;
reg output_axis_tready = 1'b0;
reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_axis_tready = 0;
// Outputs
wire input_axis_tready;
wire [7:0] output_axis_tdata;
wire [DATA_WIDTH-1:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
$from_myhdl(
clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready
);
$to_myhdl(
input_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser
);
// dump file
$dumpfile("test_axis_srl_register.lxt");
@ -68,7 +78,7 @@ initial begin
end
axis_srl_register #(
.DATA_WIDTH(8)
.DATA_WIDTH(DATA_WIDTH)
)
UUT (
.clk(clk),

203
lib/axis/tb/test_axis_srl_register_64.py
View File

@ -26,65 +26,26 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_srl_register_64'
testbench = 'test_%s' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_axis_srl_register_64(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
DATA_WIDTH = 64
KEEP_WIDTH = (DATA_WIDTH/8)
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
@ -106,53 +67,63 @@ def bench():
output_axis_tuser = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
source = axis_ep.AXIStreamSource()
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
source_logic = source.create_logic(
clk,
rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
pause=source_pause,
name='source'
)
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink'
)
# DUT
dut = dut_axis_srl_register_64(clk,
rst,
current_test,
if os.system(build_cmd):
raise Exception("Error running build command")
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser)
input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser
)
@always(delay(4))
def clkgen():
@ -179,16 +150,14 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -202,16 +171,14 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -223,7 +190,7 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield delay(64)
@ -244,9 +211,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -264,8 +229,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
yield output_axis_tlast.posedge
@ -274,15 +239,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -300,8 +261,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -315,15 +276,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -341,8 +298,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
@ -356,15 +313,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -379,16 +332,14 @@ def bench():
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame.user = 1
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
assert rx_frame.user[-1]
@ -397,7 +348,7 @@ def bench():
raise StopSimulation
return dut, source, sink, clkgen, check
return dut, source_logic, sink_logic, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))

62
lib/axis/tb/test_axis_srl_register_64.v
View File

@ -24,47 +24,58 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1 ns / 1 ps
`timescale 1ns / 1ps
/*
* Testbench for axis_srl_register_64
*/
module test_axis_srl_register_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_WIDTH = (DATA_WIDTH/8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [63:0] input_axis_tdata = 8'd0;
reg [7:0] input_axis_tkeep = 8'd0;
reg input_axis_tvalid = 1'b0;
reg input_axis_tlast = 1'b0;
reg input_axis_tuser = 1'b0;
reg output_axis_tready = 1'b0;
reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_axis_tready = 0;
// Outputs
wire input_axis_tready;
wire [63:0] output_axis_tdata;
wire [7:0] output_axis_tkeep;
wire [DATA_WIDTH-1:0] output_axis_tdata;
wire [KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
$from_myhdl(
clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready
);
$to_myhdl(
input_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser
);
// dump file
$dumpfile("test_axis_srl_register_64.lxt");
@ -72,7 +83,8 @@ initial begin
end
axis_srl_register_64 #(
.DATA_WIDTH(64)
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH)
)
UUT (
.clk(clk),

278
lib/axis/tb/test_axis_stat_counter.py
View File

@ -25,87 +25,50 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import struct
import axis_ep
module = 'axis_stat_counter'
testbench = 'test_%s' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_axis_stat_counter(clk,
rst,
current_test,
monitor_axis_tdata,
monitor_axis_tkeep,
monitor_axis_tvalid,
monitor_axis_tready,
monitor_axis_tlast,
monitor_axis_tuser,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
tag,
trigger,
busy):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
monitor_axis_tdata=monitor_axis_tdata,
monitor_axis_tkeep=monitor_axis_tkeep,
monitor_axis_tvalid=monitor_axis_tvalid,
monitor_axis_tready=monitor_axis_tready,
monitor_axis_tlast=monitor_axis_tlast,
monitor_axis_tuser=monitor_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser,
tag=tag,
trigger=trigger,
busy=busy)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
DATA_WIDTH = 64
KEEP_WIDTH = (DATA_WIDTH/8)
TAG_ENABLE = 1
TAG_WIDTH = 16
TICK_COUNT_ENABLE = 1
TICK_COUNT_WIDTH = 32
BYTE_COUNT_ENABLE = 1
BYTE_COUNT_WIDTH = 32
FRAME_COUNT_ENABLE = 1
FRAME_COUNT_WIDTH = 32
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
monitor_axis_tdata = Signal(intbv(0)[64:])
monitor_axis_tkeep = Signal(intbv(0)[8:])
monitor_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
monitor_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
monitor_axis_tvalid = Signal(bool(0))
monitor_axis_tready = Signal(bool(0))
monitor_axis_tlast = Signal(bool(0))
monitor_axis_tuser = Signal(bool(0))
output_axis_tready = Signal(bool(0))
tag = Signal(intbv(16)[16:])
tag = Signal(intbv(16)[TAG_WIDTH:])
trigger = Signal(bool(0))
# Outputs
@ -116,69 +79,81 @@ def bench():
busy = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
monitor_sink_queue = Queue()
monitor_sink_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=monitor_axis_tdata,
tkeep=monitor_axis_tkeep,
tvalid=monitor_axis_tvalid,
tready=monitor_axis_tready,
tlast=monitor_axis_tlast,
tuser=monitor_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
source = axis_ep.AXIStreamSource()
monitor_sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=monitor_axis_tdata,
tkeep=monitor_axis_tkeep,
tvalid=monitor_axis_tvalid,
tready=monitor_axis_tready,
tlast=monitor_axis_tlast,
tuser=monitor_axis_tuser,
fifo=monitor_sink_queue,
pause=monitor_sink_pause,
name='monitor_sink')
source_logic = source.create_logic(
clk,
rst,
tdata=monitor_axis_tdata,
tkeep=monitor_axis_tkeep,
tvalid=monitor_axis_tvalid,
tready=monitor_axis_tready,
tlast=monitor_axis_tlast,
tuser=monitor_axis_tuser,
pause=source_pause,
name='source'
)
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
monitor_sink = axis_ep.AXIStreamSink()
monitor_sink_logic = monitor_sink.create_logic(
clk,
rst,
tdata=monitor_axis_tdata,
tkeep=monitor_axis_tkeep,
tvalid=monitor_axis_tvalid,
tready=monitor_axis_tready,
tlast=monitor_axis_tlast,
tuser=monitor_axis_tuser,
pause=monitor_sink_pause,
name='monitor_sink'
)
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink'
)
# DUT
dut = dut_axis_stat_counter(clk,
rst,
current_test,
if os.system(build_cmd):
raise Exception("Error running build command")
monitor_axis_tdata,
monitor_axis_tkeep,
monitor_axis_tvalid,
monitor_axis_tready,
monitor_axis_tlast,
monitor_axis_tuser,
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
monitor_axis_tdata=monitor_axis_tdata,
monitor_axis_tkeep=monitor_axis_tkeep,
monitor_axis_tvalid=monitor_axis_tvalid,
monitor_axis_tready=monitor_axis_tready,
monitor_axis_tlast=monitor_axis_tlast,
monitor_axis_tuser=monitor_axis_tuser,
tag,
trigger,
busy)
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser,
tag=tag,
trigger=trigger,
busy=busy
)
@always(delay(4))
def clkgen():
@ -223,12 +198,10 @@ def bench():
yield clk.posedge
# discard first trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
# check second trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
cycles = (stop_time - start_time) / 8
@ -257,7 +230,7 @@ def bench():
trigger.next = 1
yield clk.posedge
trigger.next = 0
while trigger or output_axis_tvalid:
sink_pause.next = True
yield clk.posedge
@ -270,12 +243,10 @@ def bench():
yield clk.posedge
# discard first trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
# check second trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
cycles = (stop_time - start_time) / 8
@ -301,7 +272,7 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
while monitor_axis_tvalid:
@ -323,12 +294,10 @@ def bench():
yield clk.posedge
# discard first trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
# check second trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
cycles = (stop_time - start_time) / 8
@ -355,7 +324,7 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
while monitor_axis_tvalid:
@ -377,12 +346,10 @@ def bench():
yield clk.posedge
# discard first trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
# check second trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
cycles = (stop_time - start_time) / 8
@ -409,7 +376,7 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield delay(64)
@ -445,12 +412,10 @@ def bench():
yield clk.posedge
# discard first trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
# check second trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
cycles = (stop_time - start_time) / 8
@ -481,8 +446,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while monitor_axis_tvalid:
@ -504,12 +469,10 @@ def bench():
yield clk.posedge
# discard first trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
# check second trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
cycles = (stop_time - start_time) / 8
@ -540,8 +503,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while monitor_axis_tvalid:
@ -563,12 +526,10 @@ def bench():
yield clk.posedge
# discard first trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
# check second trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
cycles = (stop_time - start_time) / 8
@ -599,8 +560,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while monitor_axis_tvalid:
@ -622,12 +583,10 @@ def bench():
yield clk.posedge
# discard first trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
# check second trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
cycles = (stop_time - start_time) / 8
@ -660,7 +619,7 @@ def bench():
bytearray(range(lens[i]))))
for f in test_frame:
source_queue.put(f)
source.send(f)
yield clk.posedge
while monitor_axis_tvalid:
@ -682,12 +641,10 @@ def bench():
yield clk.posedge
# discard first trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
# check second trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
cycles = (stop_time - start_time) / 8
@ -720,7 +677,7 @@ def bench():
bytearray(range(lens[i]))))
for f in test_frame:
source_queue.put(f)
source.send(f)
yield clk.posedge
yield delay(200)
@ -751,16 +708,13 @@ def bench():
yield clk.posedge
# discard first trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
# check second trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
# check second trigger output
if not sink_queue.empty():
rx_frame2 = sink_queue.get()
rx_frame2 = sink.recv()
rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
cycles = (stop_time - start_time) / 8
@ -783,7 +737,7 @@ def bench():
raise StopSimulation
return dut, source, monitor_sink, sink, clkgen, check
return dut, source_logic, monitor_sink_logic, sink_logic, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))

61
lib/axis/tb/test_axis_stat_counter.v
View File

@ -24,11 +24,14 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1 ns / 1 ps
`timescale 1ns / 1ps
/*
* Testbench for axis_stat_counter
*/
module test_axis_stat_counter;
// parameters
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter TAG_ENABLE = 1;
@ -45,14 +48,14 @@ reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [63:0] monitor_axis_tdata = 8'd0;
reg [7:0] monitor_axis_tkeep = 8'd0;
reg monitor_axis_tvalid = 1'b0;
reg monitor_axis_tready = 1'b0;
reg monitor_axis_tlast = 1'b0;
reg monitor_axis_tuser = 1'b0;
reg output_axis_tready = 1'b0;
reg [15:0] tag = 0;
reg [DATA_WIDTH-1:0] monitor_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] monitor_axis_tkeep = 0;
reg monitor_axis_tvalid = 0;
reg monitor_axis_tready = 0;
reg monitor_axis_tlast = 0;
reg monitor_axis_tuser = 0;
reg output_axis_tready = 0;
reg [TAG_WIDTH-1:0] tag = 0;
reg trigger = 0;
// Outputs
@ -64,23 +67,27 @@ wire busy;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
monitor_axis_tdata,
monitor_axis_tkeep,
monitor_axis_tvalid,
monitor_axis_tready,
monitor_axis_tlast,
monitor_axis_tuser,
output_axis_tready,
tag,
trigger);
$to_myhdl(output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser,
busy);
$from_myhdl(
clk,
rst,
current_test,
monitor_axis_tdata,
monitor_axis_tkeep,
monitor_axis_tvalid,
monitor_axis_tready,
monitor_axis_tlast,
monitor_axis_tuser,
output_axis_tready,
tag,
trigger
);
$to_myhdl(
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser,
busy
);
// dump file
$dumpfile("test_axis_stat_counter.lxt");

558
lib/axis/tb/test_axis_switch_4x4.py
View File

@ -26,15 +26,10 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_switch_4x4'
testbench = 'test_axis_switch_4x4'
testbench = 'test_%s' % module
srcs = []
@ -47,117 +42,6 @@ src = ' '.join(srcs)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def dut_axis_switch_4x4(clk,
rst,
current_test,
input_0_axis_tdata,
input_0_axis_tvalid,
input_0_axis_tready,
input_0_axis_tlast,
input_0_axis_tdest,
input_0_axis_tuser,
input_1_axis_tdata,
input_1_axis_tvalid,
input_1_axis_tready,
input_1_axis_tlast,
input_1_axis_tdest,
input_1_axis_tuser,
input_2_axis_tdata,
input_2_axis_tvalid,
input_2_axis_tready,
input_2_axis_tlast,
input_2_axis_tdest,
input_2_axis_tuser,
input_3_axis_tdata,
input_3_axis_tvalid,
input_3_axis_tready,
input_3_axis_tlast,
input_3_axis_tdest,
input_3_axis_tuser,
output_0_axis_tdata,
output_0_axis_tvalid,
output_0_axis_tready,
output_0_axis_tlast,
output_0_axis_tdest,
output_0_axis_tuser,
output_1_axis_tdata,
output_1_axis_tvalid,
output_1_axis_tready,
output_1_axis_tlast,
output_1_axis_tdest,
output_1_axis_tuser,
output_2_axis_tdata,
output_2_axis_tvalid,
output_2_axis_tready,
output_2_axis_tlast,
output_2_axis_tdest,
output_2_axis_tuser,
output_3_axis_tdata,
output_3_axis_tvalid,
output_3_axis_tready,
output_3_axis_tlast,
output_3_axis_tdest,
output_3_axis_tuser):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
input_0_axis_tdata=input_0_axis_tdata,
input_0_axis_tvalid=input_0_axis_tvalid,
input_0_axis_tready=input_0_axis_tready,
input_0_axis_tlast=input_0_axis_tlast,
input_0_axis_tdest=input_0_axis_tdest,
input_0_axis_tuser=input_0_axis_tuser,
input_1_axis_tdata=input_1_axis_tdata,
input_1_axis_tvalid=input_1_axis_tvalid,
input_1_axis_tready=input_1_axis_tready,
input_1_axis_tlast=input_1_axis_tlast,
input_1_axis_tdest=input_1_axis_tdest,
input_1_axis_tuser=input_1_axis_tuser,
input_2_axis_tdata=input_2_axis_tdata,
input_2_axis_tvalid=input_2_axis_tvalid,
input_2_axis_tready=input_2_axis_tready,
input_2_axis_tlast=input_2_axis_tlast,
input_2_axis_tdest=input_2_axis_tdest,
input_2_axis_tuser=input_2_axis_tuser,
input_3_axis_tdata=input_3_axis_tdata,
input_3_axis_tvalid=input_3_axis_tvalid,
input_3_axis_tready=input_3_axis_tready,
input_3_axis_tlast=input_3_axis_tlast,
input_3_axis_tdest=input_3_axis_tdest,
input_3_axis_tuser=input_3_axis_tuser,
output_0_axis_tdata=output_0_axis_tdata,
output_0_axis_tvalid=output_0_axis_tvalid,
output_0_axis_tready=output_0_axis_tready,
output_0_axis_tlast=output_0_axis_tlast,
output_0_axis_tdest=output_0_axis_tdest,
output_0_axis_tuser=output_0_axis_tuser,
output_1_axis_tdata=output_1_axis_tdata,
output_1_axis_tvalid=output_1_axis_tvalid,
output_1_axis_tready=output_1_axis_tready,
output_1_axis_tlast=output_1_axis_tlast,
output_1_axis_tdest=output_1_axis_tdest,
output_1_axis_tuser=output_1_axis_tuser,
output_2_axis_tdata=output_2_axis_tdata,
output_2_axis_tvalid=output_2_axis_tvalid,
output_2_axis_tready=output_2_axis_tready,
output_2_axis_tlast=output_2_axis_tlast,
output_2_axis_tdest=output_2_axis_tdest,
output_2_axis_tuser=output_2_axis_tuser,
output_3_axis_tdata=output_3_axis_tdata,
output_3_axis_tvalid=output_3_axis_tvalid,
output_3_axis_tready=output_3_axis_tready,
output_3_axis_tlast=output_3_axis_tlast,
output_3_axis_tdest=output_3_axis_tdest,
output_3_axis_tuser=output_3_axis_tuser)
def bench():
# Parameters
@ -235,165 +119,195 @@ def bench():
output_3_axis_tuser = Signal(bool(0))
# sources and sinks
source_0_queue = Queue()
source_0_pause = Signal(bool(0))
source_1_queue = Queue()
source_1_pause = Signal(bool(0))
source_2_queue = Queue()
source_2_pause = Signal(bool(0))
source_3_queue = Queue()
source_3_pause = Signal(bool(0))
sink_0_queue = Queue()
sink_0_pause = Signal(bool(0))
sink_1_queue = Queue()
sink_1_pause = Signal(bool(0))
sink_2_queue = Queue()
sink_2_pause = Signal(bool(0))
sink_3_queue = Queue()
sink_3_pause = Signal(bool(0))
source_0 = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_0_axis_tdata,
tvalid=input_0_axis_tvalid,
tready=input_0_axis_tready,
tlast=input_0_axis_tlast,
tdest=input_0_axis_tdest,
tuser=input_0_axis_tuser,
fifo=source_0_queue,
pause=source_0_pause,
name='source0')
source_1 = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_1_axis_tdata,
tvalid=input_1_axis_tvalid,
tready=input_1_axis_tready,
tlast=input_1_axis_tlast,
tdest=input_1_axis_tdest,
tuser=input_1_axis_tuser,
fifo=source_1_queue,
pause=source_1_pause,
name='source1')
source_2 = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_2_axis_tdata,
tvalid=input_2_axis_tvalid,
tready=input_2_axis_tready,
tlast=input_2_axis_tlast,
tdest=input_2_axis_tdest,
tuser=input_2_axis_tuser,
fifo=source_2_queue,
pause=source_2_pause,
name='source2')
source_3 = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_3_axis_tdata,
tvalid=input_3_axis_tvalid,
tready=input_3_axis_tready,
tlast=input_3_axis_tlast,
tdest=input_3_axis_tdest,
tuser=input_3_axis_tuser,
fifo=source_3_queue,
pause=source_3_pause,
name='source3')
source_0 = axis_ep.AXIStreamSource()
sink_0 = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_0_axis_tdata,
tvalid=output_0_axis_tvalid,
tready=output_0_axis_tready,
tlast=output_0_axis_tlast,
tdest=output_0_axis_tdest,
tuser=output_0_axis_tuser,
fifo=sink_0_queue,
pause=sink_0_pause,
name='sink0')
sink_1 = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_1_axis_tdata,
tvalid=output_1_axis_tvalid,
tready=output_1_axis_tready,
tlast=output_1_axis_tlast,
tdest=output_1_axis_tdest,
tuser=output_1_axis_tuser,
fifo=sink_1_queue,
pause=sink_1_pause,
name='sink1')
sink_2 = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_2_axis_tdata,
tvalid=output_2_axis_tvalid,
tready=output_2_axis_tready,
tlast=output_2_axis_tlast,
tdest=output_2_axis_tdest,
tuser=output_2_axis_tuser,
fifo=sink_2_queue,
pause=sink_2_pause,
name='sink2')
sink_3 = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_3_axis_tdata,
tvalid=output_3_axis_tvalid,
tready=output_3_axis_tready,
tlast=output_3_axis_tlast,
tdest=output_3_axis_tdest,
tuser=output_3_axis_tuser,
fifo=sink_3_queue,
pause=sink_3_pause,
name='sink3')
source_0_logic = source_0.create_logic(
clk,
rst,
tdata=input_0_axis_tdata,
tvalid=input_0_axis_tvalid,
tready=input_0_axis_tready,
tlast=input_0_axis_tlast,
tdest=input_0_axis_tdest,
tuser=input_0_axis_tuser,
pause=source_0_pause,
name='source_0'
)
source_1 = axis_ep.AXIStreamSource()
source_1_logic = source_1.create_logic(
clk,
rst,
tdata=input_1_axis_tdata,
tvalid=input_1_axis_tvalid,
tready=input_1_axis_tready,
tlast=input_1_axis_tlast,
tdest=input_1_axis_tdest,
tuser=input_1_axis_tuser,
pause=source_1_pause,
name='source_1'
)
source_2 = axis_ep.AXIStreamSource()
source_2_logic = source_2.create_logic(
clk,
rst,
tdata=input_2_axis_tdata,
tvalid=input_2_axis_tvalid,
tready=input_2_axis_tready,
tlast=input_2_axis_tlast,
tdest=input_2_axis_tdest,
tuser=input_2_axis_tuser,
pause=source_2_pause,
name='source_2'
)
source_3 = axis_ep.AXIStreamSource()
source_3_logic = source_3.create_logic(
clk,
rst,
tdata=input_3_axis_tdata,
tvalid=input_3_axis_tvalid,
tready=input_3_axis_tready,
tlast=input_3_axis_tlast,
tdest=input_3_axis_tdest,
tuser=input_3_axis_tuser,
pause=source_3_pause,
name='source_3'
)
sink_0 = axis_ep.AXIStreamSink()
sink_0_logic = sink_0.create_logic(
clk,
rst,
tdata=output_0_axis_tdata,
tvalid=output_0_axis_tvalid,
tready=output_0_axis_tready,
tlast=output_0_axis_tlast,
tdest=output_0_axis_tdest,
tuser=output_0_axis_tuser,
pause=sink_0_pause,
name='sink_0'
)
sink_1 = axis_ep.AXIStreamSink()
sink_1_logic = sink_1.create_logic(
clk,
rst,
tdata=output_1_axis_tdata,
tvalid=output_1_axis_tvalid,
tready=output_1_axis_tready,
tlast=output_1_axis_tlast,
tdest=output_1_axis_tdest,
tuser=output_1_axis_tuser,
pause=sink_1_pause,
name='sink_1'
)
sink_2 = axis_ep.AXIStreamSink()
sink_2_logic = sink_2.create_logic(
clk,
rst,
tdata=output_2_axis_tdata,
tvalid=output_2_axis_tvalid,
tready=output_2_axis_tready,
tlast=output_2_axis_tlast,
tdest=output_2_axis_tdest,
tuser=output_2_axis_tuser,
pause=sink_2_pause,
name='sink_2'
)
sink_3 = axis_ep.AXIStreamSink()
sink_3_logic = sink_3.create_logic(
clk,
rst,
tdata=output_3_axis_tdata,
tvalid=output_3_axis_tvalid,
tready=output_3_axis_tready,
tlast=output_3_axis_tlast,
tdest=output_3_axis_tdest,
tuser=output_3_axis_tuser,
pause=sink_3_pause,
name='sink_3'
)
# DUT
dut = dut_axis_switch_4x4(clk,
rst,
current_test,
input_0_axis_tdata,
input_0_axis_tvalid,
input_0_axis_tready,
input_0_axis_tlast,
input_0_axis_tdest,
input_0_axis_tuser,
input_1_axis_tdata,
input_1_axis_tvalid,
input_1_axis_tready,
input_1_axis_tlast,
input_1_axis_tdest,
input_1_axis_tuser,
input_2_axis_tdata,
input_2_axis_tvalid,
input_2_axis_tready,
input_2_axis_tlast,
input_2_axis_tdest,
input_2_axis_tuser,
input_3_axis_tdata,
input_3_axis_tvalid,
input_3_axis_tready,
input_3_axis_tlast,
input_3_axis_tdest,
input_3_axis_tuser,
output_0_axis_tdata,
output_0_axis_tvalid,
output_0_axis_tready,
output_0_axis_tlast,
output_0_axis_tdest,
output_0_axis_tuser,
output_1_axis_tdata,
output_1_axis_tvalid,
output_1_axis_tready,
output_1_axis_tlast,
output_1_axis_tdest,
output_1_axis_tuser,
output_2_axis_tdata,
output_2_axis_tvalid,
output_2_axis_tready,
output_2_axis_tlast,
output_2_axis_tdest,
output_2_axis_tuser,
output_3_axis_tdata,
output_3_axis_tvalid,
output_3_axis_tready,
output_3_axis_tlast,
output_3_axis_tdest,
output_3_axis_tuser)
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
input_0_axis_tdata=input_0_axis_tdata,
input_0_axis_tvalid=input_0_axis_tvalid,
input_0_axis_tready=input_0_axis_tready,
input_0_axis_tlast=input_0_axis_tlast,
input_0_axis_tdest=input_0_axis_tdest,
input_0_axis_tuser=input_0_axis_tuser,
input_1_axis_tdata=input_1_axis_tdata,
input_1_axis_tvalid=input_1_axis_tvalid,
input_1_axis_tready=input_1_axis_tready,
input_1_axis_tlast=input_1_axis_tlast,
input_1_axis_tdest=input_1_axis_tdest,
input_1_axis_tuser=input_1_axis_tuser,
input_2_axis_tdata=input_2_axis_tdata,
input_2_axis_tvalid=input_2_axis_tvalid,
input_2_axis_tready=input_2_axis_tready,
input_2_axis_tlast=input_2_axis_tlast,
input_2_axis_tdest=input_2_axis_tdest,
input_2_axis_tuser=input_2_axis_tuser,
input_3_axis_tdata=input_3_axis_tdata,
input_3_axis_tvalid=input_3_axis_tvalid,
input_3_axis_tready=input_3_axis_tready,
input_3_axis_tlast=input_3_axis_tlast,
input_3_axis_tdest=input_3_axis_tdest,
input_3_axis_tuser=input_3_axis_tuser,
output_0_axis_tdata=output_0_axis_tdata,
output_0_axis_tvalid=output_0_axis_tvalid,
output_0_axis_tready=output_0_axis_tready,
output_0_axis_tlast=output_0_axis_tlast,
output_0_axis_tdest=output_0_axis_tdest,
output_0_axis_tuser=output_0_axis_tuser,
output_1_axis_tdata=output_1_axis_tdata,
output_1_axis_tvalid=output_1_axis_tvalid,
output_1_axis_tready=output_1_axis_tready,
output_1_axis_tlast=output_1_axis_tlast,
output_1_axis_tdest=output_1_axis_tdest,
output_1_axis_tuser=output_1_axis_tuser,
output_2_axis_tdata=output_2_axis_tdata,
output_2_axis_tvalid=output_2_axis_tvalid,
output_2_axis_tready=output_2_axis_tready,
output_2_axis_tlast=output_2_axis_tlast,
output_2_axis_tdest=output_2_axis_tdest,
output_2_axis_tuser=output_2_axis_tuser,
output_3_axis_tdata=output_3_axis_tdata,
output_3_axis_tvalid=output_3_axis_tvalid,
output_3_axis_tready=output_3_axis_tready,
output_3_axis_tlast=output_3_axis_tlast,
output_3_axis_tdest=output_3_axis_tdest,
output_3_axis_tuser=output_3_axis_tuser
)
@always(delay(4))
def clkgen():
@ -456,10 +370,10 @@ def bench():
test_frame3 = axis_ep.AXIStreamFrame(b'\x01\x03\x03\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=3)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_0_queue.put(test_frame0)
source_1_queue.put(test_frame1)
source_2_queue.put(test_frame2)
source_3_queue.put(test_frame3)
source_0.send(test_frame0)
source_1.send(test_frame1)
source_2.send(test_frame2)
source_3.send(test_frame3)
yield clk.posedge
yield clk.posedge
@ -467,27 +381,19 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame0 = None
if not sink_0_queue.empty():
rx_frame0 = sink_0_queue.get()
rx_frame0 = sink_0.recv()
assert rx_frame0 == test_frame0
rx_frame1 = None
if not sink_1_queue.empty():
rx_frame1 = sink_1_queue.get()
rx_frame1 = sink_1.recv()
assert rx_frame1 == test_frame1
rx_frame2 = None
if not sink_2_queue.empty():
rx_frame2 = sink_2_queue.get()
rx_frame2 = sink_2.recv()
assert rx_frame2 == test_frame2
rx_frame3 = None
if not sink_3_queue.empty():
rx_frame3 = sink_3_queue.get()
rx_frame3 = sink_3.recv()
assert rx_frame3 == test_frame3
@ -503,10 +409,10 @@ def bench():
test_frame3 = axis_ep.AXIStreamFrame(b'\x02\x03\x00\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=0)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_0_queue.put(test_frame0)
source_1_queue.put(test_frame1)
source_2_queue.put(test_frame2)
source_3_queue.put(test_frame3)
source_0.send(test_frame0)
source_1.send(test_frame1)
source_2.send(test_frame2)
source_3.send(test_frame3)
yield clk.posedge
yield clk.posedge
@ -514,27 +420,19 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame0 = None
if not sink_0_queue.empty():
rx_frame0 = sink_0_queue.get()
rx_frame0 = sink_0.recv()
assert rx_frame0 == test_frame3
rx_frame1 = None
if not sink_1_queue.empty():
rx_frame1 = sink_1_queue.get()
rx_frame1 = sink_1.recv()
assert rx_frame1 == test_frame2
rx_frame2 = None
if not sink_2_queue.empty():
rx_frame2 = sink_2_queue.get()
rx_frame2 = sink_2.recv()
assert rx_frame2 == test_frame1
rx_frame3 = None
if not sink_3_queue.empty():
rx_frame3 = sink_3_queue.get()
rx_frame3 = sink_3.recv()
assert rx_frame3 == test_frame0
@ -550,10 +448,10 @@ def bench():
test_frame3 = axis_ep.AXIStreamFrame(b'\x02\x00\x03\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=3)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_0_queue.put(test_frame0)
source_0_queue.put(test_frame1)
source_0_queue.put(test_frame2)
source_0_queue.put(test_frame3)
source_0.send(test_frame0)
source_0.send(test_frame1)
source_0.send(test_frame2)
source_0.send(test_frame3)
yield clk.posedge
yield clk.posedge
@ -561,27 +459,19 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame0 = None
if not sink_0_queue.empty():
rx_frame0 = sink_0_queue.get()
rx_frame0 = sink_0.recv()
assert rx_frame0 == test_frame0
rx_frame1 = None
if not sink_1_queue.empty():
rx_frame1 = sink_1_queue.get()
rx_frame1 = sink_1.recv()
assert rx_frame1 == test_frame1
rx_frame2 = None
if not sink_2_queue.empty():
rx_frame2 = sink_2_queue.get()
rx_frame2 = sink_2.recv()
assert rx_frame2 == test_frame2
rx_frame3 = None
if not sink_3_queue.empty():
rx_frame3 = sink_3_queue.get()
rx_frame3 = sink_3.recv()
assert rx_frame3 == test_frame3
@ -595,40 +485,32 @@ def bench():
test_frame1 = axis_ep.AXIStreamFrame(b'\x02\x01\x00\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=0)
test_frame2 = axis_ep.AXIStreamFrame(b'\x02\x02\x00\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=0)
test_frame3 = axis_ep.AXIStreamFrame(b'\x02\x03\x00\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=0)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_0_queue.put(test_frame0)
source_0.send(test_frame0)
yield clk.posedge
source_1_queue.put(test_frame1)
source_2_queue.put(test_frame2)
source_3_queue.put(test_frame3)
source_1.send(test_frame1)
source_2.send(test_frame2)
source_3.send(test_frame3)
yield clk.posedge
yield wait()
yield clk.posedge
yield clk.posedge
rx_frame0 = None
if not sink_0_queue.empty():
rx_frame0 = sink_0_queue.get()
rx_frame0 = sink_0.recv()
assert rx_frame0 == test_frame0
rx_frame1 = None
if not sink_0_queue.empty():
rx_frame1 = sink_0_queue.get()
rx_frame1 = sink_0.recv()
assert rx_frame1 == test_frame1
rx_frame2 = None
if not sink_0_queue.empty():
rx_frame2 = sink_0_queue.get()
rx_frame2 = sink_0.recv()
assert rx_frame2 == test_frame2
rx_frame3 = None
if not sink_0_queue.empty():
rx_frame3 = sink_0_queue.get()
rx_frame3 = sink_0.recv()
assert rx_frame3 == test_frame3
@ -644,10 +526,10 @@ def bench():
test_frame3 = axis_ep.AXIStreamFrame(b'\x01\x03\x05\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=5)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_0_queue.put(test_frame0)
source_1_queue.put(test_frame1)
source_2_queue.put(test_frame2)
source_3_queue.put(test_frame3)
source_0.send(test_frame0)
source_1.send(test_frame1)
source_2.send(test_frame2)
source_3.send(test_frame3)
yield clk.posedge
yield clk.posedge
@ -655,15 +537,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame0 = None
if not sink_0_queue.empty():
rx_frame0 = sink_0_queue.get()
rx_frame0 = sink_0.recv()
assert rx_frame0 == test_frame0
rx_frame1 = None
if not sink_1_queue.empty():
rx_frame1 = sink_1_queue.get()
rx_frame1 = sink_1.recv()
assert rx_frame1 == test_frame1
@ -671,7 +549,7 @@ def bench():
raise StopSimulation
return dut, source_0, source_1, source_2, source_3, sink_0, sink_1, sink_2, sink_3, clkgen, check
return dut, source_0_logic, source_1_logic, source_2_logic, source_3_logic, sink_0_logic, sink_1_logic, sink_2_logic, sink_3_logic, clkgen, check
def test_bench():
sim = Simulation(bench())

106
lib/axis/tb/test_axis_switch_4x4.v
View File

@ -107,57 +107,61 @@ wire output_3_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_0_axis_tdata,
input_0_axis_tvalid,
input_0_axis_tlast,
input_0_axis_tdest,
input_0_axis_tuser,
input_1_axis_tdata,
input_1_axis_tvalid,
input_1_axis_tlast,
input_1_axis_tdest,
input_1_axis_tuser,
input_2_axis_tdata,
input_2_axis_tvalid,
input_2_axis_tlast,
input_2_axis_tdest,
input_2_axis_tuser,
input_3_axis_tdata,
input_3_axis_tvalid,
input_3_axis_tlast,
input_3_axis_tdest,
input_3_axis_tuser,
output_0_axis_tready,
output_1_axis_tready,
output_2_axis_tready,
output_3_axis_tready);
$to_myhdl(input_0_axis_tready,
input_1_axis_tready,
input_2_axis_tready,
input_3_axis_tready,
output_0_axis_tdata,
output_0_axis_tvalid,
output_0_axis_tlast,
output_0_axis_tdest,
output_0_axis_tuser,
output_1_axis_tdata,
output_1_axis_tvalid,
output_1_axis_tlast,
output_1_axis_tdest,
output_1_axis_tuser,
output_2_axis_tdata,
output_2_axis_tvalid,
output_2_axis_tlast,
output_2_axis_tdest,
output_2_axis_tuser,
output_3_axis_tdata,
output_3_axis_tvalid,
output_3_axis_tlast,
output_3_axis_tdest,
output_3_axis_tuser);
$from_myhdl(
clk,
rst,
current_test,
input_0_axis_tdata,
input_0_axis_tvalid,
input_0_axis_tlast,
input_0_axis_tdest,
input_0_axis_tuser,
input_1_axis_tdata,
input_1_axis_tvalid,
input_1_axis_tlast,
input_1_axis_tdest,
input_1_axis_tuser,
input_2_axis_tdata,
input_2_axis_tvalid,
input_2_axis_tlast,
input_2_axis_tdest,
input_2_axis_tuser,
input_3_axis_tdata,
input_3_axis_tvalid,
input_3_axis_tlast,
input_3_axis_tdest,
input_3_axis_tuser,
output_0_axis_tready,
output_1_axis_tready,
output_2_axis_tready,
output_3_axis_tready
);
$to_myhdl(
input_0_axis_tready,
input_1_axis_tready,
input_2_axis_tready,
input_3_axis_tready,
output_0_axis_tdata,
output_0_axis_tvalid,
output_0_axis_tlast,
output_0_axis_tdest,
output_0_axis_tuser,
output_1_axis_tdata,
output_1_axis_tvalid,
output_1_axis_tlast,
output_1_axis_tdest,
output_1_axis_tuser,
output_2_axis_tdata,
output_2_axis_tvalid,
output_2_axis_tlast,
output_2_axis_tdest,
output_2_axis_tuser,
output_3_axis_tdata,
output_3_axis_tvalid,
output_3_axis_tlast,
output_3_axis_tdest,
output_3_axis_tuser
);
// dump file
$dumpfile("test_axis_switch_4x4.lxt");

608
lib/axis/tb/test_axis_switch_64_4x4.py
View File

@ -26,15 +26,10 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_switch_64_4x4'
testbench = 'test_axis_switch_64_4x4'
testbench = 'test_%s' % module
srcs = []
@ -47,138 +42,11 @@ src = ' '.join(srcs)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def dut_axis_switch_64_4x4(clk,
rst,
current_test,
input_0_axis_tdata,
input_0_axis_tkeep,
input_0_axis_tvalid,
input_0_axis_tready,
input_0_axis_tlast,
input_0_axis_tdest,
input_0_axis_tuser,
input_1_axis_tdata,
input_1_axis_tkeep,
input_1_axis_tvalid,
input_1_axis_tready,
input_1_axis_tlast,
input_1_axis_tdest,
input_1_axis_tuser,
input_2_axis_tdata,
input_2_axis_tkeep,
input_2_axis_tvalid,
input_2_axis_tready,
input_2_axis_tlast,
input_2_axis_tdest,
input_2_axis_tuser,
input_3_axis_tdata,
input_3_axis_tkeep,
input_3_axis_tvalid,
input_3_axis_tready,
input_3_axis_tlast,
input_3_axis_tdest,
input_3_axis_tuser,
output_0_axis_tdata,
output_0_axis_tkeep,
output_0_axis_tvalid,
output_0_axis_tready,
output_0_axis_tlast,
output_0_axis_tdest,
output_0_axis_tuser,
output_1_axis_tdata,
output_1_axis_tkeep,
output_1_axis_tvalid,
output_1_axis_tready,
output_1_axis_tlast,
output_1_axis_tdest,
output_1_axis_tuser,
output_2_axis_tdata,
output_2_axis_tkeep,
output_2_axis_tvalid,
output_2_axis_tready,
output_2_axis_tlast,
output_2_axis_tdest,
output_2_axis_tuser,
output_3_axis_tdata,
output_3_axis_tkeep,
output_3_axis_tvalid,
output_3_axis_tready,
output_3_axis_tlast,
output_3_axis_tdest,
output_3_axis_tuser):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
input_0_axis_tdata=input_0_axis_tdata,
input_0_axis_tkeep=input_0_axis_tkeep,
input_0_axis_tvalid=input_0_axis_tvalid,
input_0_axis_tready=input_0_axis_tready,
input_0_axis_tlast=input_0_axis_tlast,
input_0_axis_tdest=input_0_axis_tdest,
input_0_axis_tuser=input_0_axis_tuser,
input_1_axis_tdata=input_1_axis_tdata,
input_1_axis_tkeep=input_1_axis_tkeep,
input_1_axis_tvalid=input_1_axis_tvalid,
input_1_axis_tready=input_1_axis_tready,
input_1_axis_tlast=input_1_axis_tlast,
input_1_axis_tdest=input_1_axis_tdest,
input_1_axis_tuser=input_1_axis_tuser,
input_2_axis_tdata=input_2_axis_tdata,
input_2_axis_tkeep=input_2_axis_tkeep,
input_2_axis_tvalid=input_2_axis_tvalid,
input_2_axis_tready=input_2_axis_tready,
input_2_axis_tlast=input_2_axis_tlast,
input_2_axis_tdest=input_2_axis_tdest,
input_2_axis_tuser=input_2_axis_tuser,
input_3_axis_tdata=input_3_axis_tdata,
input_3_axis_tkeep=input_3_axis_tkeep,
input_3_axis_tvalid=input_3_axis_tvalid,
input_3_axis_tready=input_3_axis_tready,
input_3_axis_tlast=input_3_axis_tlast,
input_3_axis_tdest=input_3_axis_tdest,
input_3_axis_tuser=input_3_axis_tuser,
output_0_axis_tdata=output_0_axis_tdata,
output_0_axis_tkeep=output_0_axis_tkeep,
output_0_axis_tvalid=output_0_axis_tvalid,
output_0_axis_tready=output_0_axis_tready,
output_0_axis_tlast=output_0_axis_tlast,
output_0_axis_tdest=output_0_axis_tdest,
output_0_axis_tuser=output_0_axis_tuser,
output_1_axis_tdata=output_1_axis_tdata,
output_1_axis_tkeep=output_1_axis_tkeep,
output_1_axis_tvalid=output_1_axis_tvalid,
output_1_axis_tready=output_1_axis_tready,
output_1_axis_tlast=output_1_axis_tlast,
output_1_axis_tdest=output_1_axis_tdest,
output_1_axis_tuser=output_1_axis_tuser,
output_2_axis_tdata=output_2_axis_tdata,
output_2_axis_tkeep=output_2_axis_tkeep,
output_2_axis_tvalid=output_2_axis_tvalid,
output_2_axis_tready=output_2_axis_tready,
output_2_axis_tlast=output_2_axis_tlast,
output_2_axis_tdest=output_2_axis_tdest,
output_2_axis_tuser=output_2_axis_tuser,
output_3_axis_tdata=output_3_axis_tdata,
output_3_axis_tkeep=output_3_axis_tkeep,
output_3_axis_tvalid=output_3_axis_tvalid,
output_3_axis_tready=output_3_axis_tready,
output_3_axis_tlast=output_3_axis_tlast,
output_3_axis_tdest=output_3_axis_tdest,
output_3_axis_tuser=output_3_axis_tuser)
def bench():
# Parameters
DATA_WIDTH = 64
KEEP_WIDTH = int(DATA_WIDTH/8)
KEEP_WIDTH = (DATA_WIDTH/8)
DEST_WIDTH = 3
OUT_0_BASE = 0
OUT_0_TOP = 0
@ -260,181 +128,211 @@ def bench():
output_3_axis_tuser = Signal(bool(0))
# sources and sinks
source_0_queue = Queue()
source_0_pause = Signal(bool(0))
source_1_queue = Queue()
source_1_pause = Signal(bool(0))
source_2_queue = Queue()
source_2_pause = Signal(bool(0))
source_3_queue = Queue()
source_3_pause = Signal(bool(0))
sink_0_queue = Queue()
sink_0_pause = Signal(bool(0))
sink_1_queue = Queue()
sink_1_pause = Signal(bool(0))
sink_2_queue = Queue()
sink_2_pause = Signal(bool(0))
sink_3_queue = Queue()
sink_3_pause = Signal(bool(0))
source_0 = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_0_axis_tdata,
tkeep=input_0_axis_tkeep,
tvalid=input_0_axis_tvalid,
tready=input_0_axis_tready,
tlast=input_0_axis_tlast,
tdest=input_0_axis_tdest,
tuser=input_0_axis_tuser,
fifo=source_0_queue,
pause=source_0_pause,
name='source0')
source_1 = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_1_axis_tdata,
tkeep=input_1_axis_tkeep,
tvalid=input_1_axis_tvalid,
tready=input_1_axis_tready,
tlast=input_1_axis_tlast,
tdest=input_1_axis_tdest,
tuser=input_1_axis_tuser,
fifo=source_1_queue,
pause=source_1_pause,
name='source1')
source_2 = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_2_axis_tdata,
tkeep=input_2_axis_tkeep,
tvalid=input_2_axis_tvalid,
tready=input_2_axis_tready,
tlast=input_2_axis_tlast,
tdest=input_2_axis_tdest,
tuser=input_2_axis_tuser,
fifo=source_2_queue,
pause=source_2_pause,
name='source2')
source_3 = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_3_axis_tdata,
tkeep=input_3_axis_tkeep,
tvalid=input_3_axis_tvalid,
tready=input_3_axis_tready,
tlast=input_3_axis_tlast,
tdest=input_3_axis_tdest,
tuser=input_3_axis_tuser,
fifo=source_3_queue,
pause=source_3_pause,
name='source3')
source_0 = axis_ep.AXIStreamSource()
sink_0 = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_0_axis_tdata,
tkeep=output_0_axis_tkeep,
tvalid=output_0_axis_tvalid,
tready=output_0_axis_tready,
tlast=output_0_axis_tlast,
tdest=output_0_axis_tdest,
tuser=output_0_axis_tuser,
fifo=sink_0_queue,
pause=sink_0_pause,
name='sink0')
sink_1 = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_1_axis_tdata,
tkeep=output_1_axis_tkeep,
tvalid=output_1_axis_tvalid,
tready=output_1_axis_tready,
tlast=output_1_axis_tlast,
tdest=output_1_axis_tdest,
tuser=output_1_axis_tuser,
fifo=sink_1_queue,
pause=sink_1_pause,
name='sink1')
sink_2 = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_2_axis_tdata,
tkeep=output_2_axis_tkeep,
tvalid=output_2_axis_tvalid,
tready=output_2_axis_tready,
tlast=output_2_axis_tlast,
tdest=output_2_axis_tdest,
tuser=output_2_axis_tuser,
fifo=sink_2_queue,
pause=sink_2_pause,
name='sink2')
sink_3 = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_3_axis_tdata,
tkeep=output_3_axis_tkeep,
tvalid=output_3_axis_tvalid,
tready=output_3_axis_tready,
tlast=output_3_axis_tlast,
tdest=output_3_axis_tdest,
tuser=output_3_axis_tuser,
fifo=sink_3_queue,
pause=sink_3_pause,
name='sink3')
source_0_logic = source_0.create_logic(
clk,
rst,
tdata=input_0_axis_tdata,
tkeep=input_0_axis_tkeep,
tvalid=input_0_axis_tvalid,
tready=input_0_axis_tready,
tlast=input_0_axis_tlast,
tdest=input_0_axis_tdest,
tuser=input_0_axis_tuser,
pause=source_0_pause,
name='source_0'
)
source_1 = axis_ep.AXIStreamSource()
source_1_logic = source_1.create_logic(
clk,
rst,
tdata=input_1_axis_tdata,
tkeep=input_1_axis_tkeep,
tvalid=input_1_axis_tvalid,
tready=input_1_axis_tready,
tlast=input_1_axis_tlast,
tdest=input_1_axis_tdest,
tuser=input_1_axis_tuser,
pause=source_1_pause,
name='source_1'
)
source_2 = axis_ep.AXIStreamSource()
source_2_logic = source_2.create_logic(
clk,
rst,
tdata=input_2_axis_tdata,
tkeep=input_2_axis_tkeep,
tvalid=input_2_axis_tvalid,
tready=input_2_axis_tready,
tlast=input_2_axis_tlast,
tdest=input_2_axis_tdest,
tuser=input_2_axis_tuser,
pause=source_2_pause,
name='source_2'
)
source_3 = axis_ep.AXIStreamSource()
source_3_logic = source_3.create_logic(
clk,
rst,
tdata=input_3_axis_tdata,
tkeep=input_3_axis_tkeep,
tvalid=input_3_axis_tvalid,
tready=input_3_axis_tready,
tlast=input_3_axis_tlast,
tdest=input_3_axis_tdest,
tuser=input_3_axis_tuser,
pause=source_3_pause,
name='source_3'
)
sink_0 = axis_ep.AXIStreamSink()
sink_0_logic = sink_0.create_logic(
clk,
rst,
tdata=output_0_axis_tdata,
tkeep=output_0_axis_tkeep,
tvalid=output_0_axis_tvalid,
tready=output_0_axis_tready,
tlast=output_0_axis_tlast,
tdest=output_0_axis_tdest,
tuser=output_0_axis_tuser,
pause=sink_0_pause,
name='sink_0'
)
sink_1 = axis_ep.AXIStreamSink()
sink_1_logic = sink_1.create_logic(
clk,
rst,
tdata=output_1_axis_tdata,
tkeep=output_1_axis_tkeep,
tvalid=output_1_axis_tvalid,
tready=output_1_axis_tready,
tlast=output_1_axis_tlast,
tdest=output_1_axis_tdest,
tuser=output_1_axis_tuser,
pause=sink_1_pause,
name='sink_1'
)
sink_2 = axis_ep.AXIStreamSink()
sink_2_logic = sink_2.create_logic(
clk,
rst,
tdata=output_2_axis_tdata,
tkeep=output_2_axis_tkeep,
tvalid=output_2_axis_tvalid,
tready=output_2_axis_tready,
tlast=output_2_axis_tlast,
tdest=output_2_axis_tdest,
tuser=output_2_axis_tuser,
pause=sink_2_pause,
name='sink_2'
)
sink_3 = axis_ep.AXIStreamSink()
sink_3_logic = sink_3.create_logic(
clk,
rst,
tdata=output_3_axis_tdata,
tkeep=output_3_axis_tkeep,
tvalid=output_3_axis_tvalid,
tready=output_3_axis_tready,
tlast=output_3_axis_tlast,
tdest=output_3_axis_tdest,
tuser=output_3_axis_tuser,
pause=sink_3_pause,
name='sink_3'
)
# DUT
dut = dut_axis_switch_64_4x4(clk,
rst,
current_test,
input_0_axis_tdata,
input_0_axis_tkeep,
input_0_axis_tvalid,
input_0_axis_tready,
input_0_axis_tlast,
input_0_axis_tdest,
input_0_axis_tuser,
input_1_axis_tdata,
input_1_axis_tkeep,
input_1_axis_tvalid,
input_1_axis_tready,
input_1_axis_tlast,
input_1_axis_tdest,
input_1_axis_tuser,
input_2_axis_tdata,
input_2_axis_tkeep,
input_2_axis_tvalid,
input_2_axis_tready,
input_2_axis_tlast,
input_2_axis_tdest,
input_2_axis_tuser,
input_3_axis_tdata,
input_3_axis_tkeep,
input_3_axis_tvalid,
input_3_axis_tready,
input_3_axis_tlast,
input_3_axis_tdest,
input_3_axis_tuser,
output_0_axis_tdata,
output_0_axis_tkeep,
output_0_axis_tvalid,
output_0_axis_tready,
output_0_axis_tlast,
output_0_axis_tdest,
output_0_axis_tuser,
output_1_axis_tdata,
output_1_axis_tkeep,
output_1_axis_tvalid,
output_1_axis_tready,
output_1_axis_tlast,
output_1_axis_tdest,
output_1_axis_tuser,
output_2_axis_tdata,
output_2_axis_tkeep,
output_2_axis_tvalid,
output_2_axis_tready,
output_2_axis_tlast,
output_2_axis_tdest,
output_2_axis_tuser,
output_3_axis_tdata,
output_3_axis_tkeep,
output_3_axis_tvalid,
output_3_axis_tready,
output_3_axis_tlast,
output_3_axis_tdest,
output_3_axis_tuser)
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
input_0_axis_tdata=input_0_axis_tdata,
input_0_axis_tkeep=input_0_axis_tkeep,
input_0_axis_tvalid=input_0_axis_tvalid,
input_0_axis_tready=input_0_axis_tready,
input_0_axis_tlast=input_0_axis_tlast,
input_0_axis_tdest=input_0_axis_tdest,
input_0_axis_tuser=input_0_axis_tuser,
input_1_axis_tdata=input_1_axis_tdata,
input_1_axis_tkeep=input_1_axis_tkeep,
input_1_axis_tvalid=input_1_axis_tvalid,
input_1_axis_tready=input_1_axis_tready,
input_1_axis_tlast=input_1_axis_tlast,
input_1_axis_tdest=input_1_axis_tdest,
input_1_axis_tuser=input_1_axis_tuser,
input_2_axis_tdata=input_2_axis_tdata,
input_2_axis_tkeep=input_2_axis_tkeep,
input_2_axis_tvalid=input_2_axis_tvalid,
input_2_axis_tready=input_2_axis_tready,
input_2_axis_tlast=input_2_axis_tlast,
input_2_axis_tdest=input_2_axis_tdest,
input_2_axis_tuser=input_2_axis_tuser,
input_3_axis_tdata=input_3_axis_tdata,
input_3_axis_tkeep=input_3_axis_tkeep,
input_3_axis_tvalid=input_3_axis_tvalid,
input_3_axis_tready=input_3_axis_tready,
input_3_axis_tlast=input_3_axis_tlast,
input_3_axis_tdest=input_3_axis_tdest,
input_3_axis_tuser=input_3_axis_tuser,
output_0_axis_tdata=output_0_axis_tdata,
output_0_axis_tkeep=output_0_axis_tkeep,
output_0_axis_tvalid=output_0_axis_tvalid,
output_0_axis_tready=output_0_axis_tready,
output_0_axis_tlast=output_0_axis_tlast,
output_0_axis_tdest=output_0_axis_tdest,
output_0_axis_tuser=output_0_axis_tuser,
output_1_axis_tdata=output_1_axis_tdata,
output_1_axis_tkeep=output_1_axis_tkeep,
output_1_axis_tvalid=output_1_axis_tvalid,
output_1_axis_tready=output_1_axis_tready,
output_1_axis_tlast=output_1_axis_tlast,
output_1_axis_tdest=output_1_axis_tdest,
output_1_axis_tuser=output_1_axis_tuser,
output_2_axis_tdata=output_2_axis_tdata,
output_2_axis_tkeep=output_2_axis_tkeep,
output_2_axis_tvalid=output_2_axis_tvalid,
output_2_axis_tready=output_2_axis_tready,
output_2_axis_tlast=output_2_axis_tlast,
output_2_axis_tdest=output_2_axis_tdest,
output_2_axis_tuser=output_2_axis_tuser,
output_3_axis_tdata=output_3_axis_tdata,
output_3_axis_tkeep=output_3_axis_tkeep,
output_3_axis_tvalid=output_3_axis_tvalid,
output_3_axis_tready=output_3_axis_tready,
output_3_axis_tlast=output_3_axis_tlast,
output_3_axis_tdest=output_3_axis_tdest,
output_3_axis_tuser=output_3_axis_tuser
)
@always(delay(4))
def clkgen():
@ -497,10 +395,10 @@ def bench():
test_frame3 = axis_ep.AXIStreamFrame(b'\x01\x03\x03\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=3)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_0_queue.put(test_frame0)
source_1_queue.put(test_frame1)
source_2_queue.put(test_frame2)
source_3_queue.put(test_frame3)
source_0.send(test_frame0)
source_1.send(test_frame1)
source_2.send(test_frame2)
source_3.send(test_frame3)
yield clk.posedge
yield clk.posedge
@ -508,27 +406,19 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame0 = None
if not sink_0_queue.empty():
rx_frame0 = sink_0_queue.get()
rx_frame0 = sink_0.recv()
assert rx_frame0 == test_frame0
rx_frame1 = None
if not sink_1_queue.empty():
rx_frame1 = sink_1_queue.get()
rx_frame1 = sink_1.recv()
assert rx_frame1 == test_frame1
rx_frame2 = None
if not sink_2_queue.empty():
rx_frame2 = sink_2_queue.get()
rx_frame2 = sink_2.recv()
assert rx_frame2 == test_frame2
rx_frame3 = None
if not sink_3_queue.empty():
rx_frame3 = sink_3_queue.get()
rx_frame3 = sink_3.recv()
assert rx_frame3 == test_frame3
@ -544,10 +434,10 @@ def bench():
test_frame3 = axis_ep.AXIStreamFrame(b'\x02\x03\x00\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=0)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_0_queue.put(test_frame0)
source_1_queue.put(test_frame1)
source_2_queue.put(test_frame2)
source_3_queue.put(test_frame3)
source_0.send(test_frame0)
source_1.send(test_frame1)
source_2.send(test_frame2)
source_3.send(test_frame3)
yield clk.posedge
yield clk.posedge
@ -555,27 +445,19 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame0 = None
if not sink_0_queue.empty():
rx_frame0 = sink_0_queue.get()
rx_frame0 = sink_0.recv()
assert rx_frame0 == test_frame3
rx_frame1 = None
if not sink_1_queue.empty():
rx_frame1 = sink_1_queue.get()
rx_frame1 = sink_1.recv()
assert rx_frame1 == test_frame2
rx_frame2 = None
if not sink_2_queue.empty():
rx_frame2 = sink_2_queue.get()
rx_frame2 = sink_2.recv()
assert rx_frame2 == test_frame1
rx_frame3 = None
if not sink_3_queue.empty():
rx_frame3 = sink_3_queue.get()
rx_frame3 = sink_3.recv()
assert rx_frame3 == test_frame0
@ -591,10 +473,10 @@ def bench():
test_frame3 = axis_ep.AXIStreamFrame(b'\x02\x00\x03\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=3)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_0_queue.put(test_frame0)
source_0_queue.put(test_frame1)
source_0_queue.put(test_frame2)
source_0_queue.put(test_frame3)
source_0.send(test_frame0)
source_0.send(test_frame1)
source_0.send(test_frame2)
source_0.send(test_frame3)
yield clk.posedge
yield clk.posedge
@ -602,27 +484,19 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame0 = None
if not sink_0_queue.empty():
rx_frame0 = sink_0_queue.get()
rx_frame0 = sink_0.recv()
assert rx_frame0 == test_frame0
rx_frame1 = None
if not sink_1_queue.empty():
rx_frame1 = sink_1_queue.get()
rx_frame1 = sink_1.recv()
assert rx_frame1 == test_frame1
rx_frame2 = None
if not sink_2_queue.empty():
rx_frame2 = sink_2_queue.get()
rx_frame2 = sink_2.recv()
assert rx_frame2 == test_frame2
rx_frame3 = None
if not sink_3_queue.empty():
rx_frame3 = sink_3_queue.get()
rx_frame3 = sink_3.recv()
assert rx_frame3 == test_frame3
@ -636,40 +510,32 @@ def bench():
test_frame1 = axis_ep.AXIStreamFrame(b'\x02\x01\x00\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=0)
test_frame2 = axis_ep.AXIStreamFrame(b'\x02\x02\x00\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=0)
test_frame3 = axis_ep.AXIStreamFrame(b'\x02\x03\x00\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=0)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_0_queue.put(test_frame0)
source_0.send(test_frame0)
yield clk.posedge
source_1_queue.put(test_frame1)
source_2_queue.put(test_frame2)
source_3_queue.put(test_frame3)
source_1.send(test_frame1)
source_2.send(test_frame2)
source_3.send(test_frame3)
yield clk.posedge
yield wait()
yield clk.posedge
yield clk.posedge
rx_frame0 = None
if not sink_0_queue.empty():
rx_frame0 = sink_0_queue.get()
rx_frame0 = sink_0.recv()
assert rx_frame0 == test_frame0
rx_frame1 = None
if not sink_0_queue.empty():
rx_frame1 = sink_0_queue.get()
rx_frame1 = sink_0.recv()
assert rx_frame1 == test_frame1
rx_frame2 = None
if not sink_0_queue.empty():
rx_frame2 = sink_0_queue.get()
rx_frame2 = sink_0.recv()
assert rx_frame2 == test_frame2
rx_frame3 = None
if not sink_0_queue.empty():
rx_frame3 = sink_0_queue.get()
rx_frame3 = sink_0.recv()
assert rx_frame3 == test_frame3
@ -685,10 +551,10 @@ def bench():
test_frame3 = axis_ep.AXIStreamFrame(b'\x01\x03\x05\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=5)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_0_queue.put(test_frame0)
source_1_queue.put(test_frame1)
source_2_queue.put(test_frame2)
source_3_queue.put(test_frame3)
source_0.send(test_frame0)
source_1.send(test_frame1)
source_2.send(test_frame2)
source_3.send(test_frame3)
yield clk.posedge
yield clk.posedge
@ -696,15 +562,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame0 = None
if not sink_0_queue.empty():
rx_frame0 = sink_0_queue.get()
rx_frame0 = sink_0.recv()
assert rx_frame0 == test_frame0
rx_frame1 = None
if not sink_1_queue.empty():
rx_frame1 = sink_1_queue.get()
rx_frame1 = sink_1.recv()
assert rx_frame1 == test_frame1
@ -712,7 +574,7 @@ def bench():
raise StopSimulation
return dut, source_0, source_1, source_2, source_3, sink_0, sink_1, sink_2, sink_3, clkgen, check
return dut, source_0_logic, source_1_logic, source_2_logic, source_3_logic, sink_0_logic, sink_1_logic, sink_2_logic, sink_3_logic, clkgen, check
def test_bench():
sim = Simulation(bench())

122
lib/axis/tb/test_axis_switch_64_4x4.v
View File

@ -116,65 +116,69 @@ wire output_3_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_0_axis_tdata,
input_0_axis_tkeep,
input_0_axis_tvalid,
input_0_axis_tlast,
input_0_axis_tdest,
input_0_axis_tuser,
input_1_axis_tdata,
input_1_axis_tkeep,
input_1_axis_tvalid,
input_1_axis_tlast,
input_1_axis_tdest,
input_1_axis_tuser,
input_2_axis_tdata,
input_2_axis_tkeep,
input_2_axis_tvalid,
input_2_axis_tlast,
input_2_axis_tdest,
input_2_axis_tuser,
input_3_axis_tdata,
input_3_axis_tkeep,
input_3_axis_tvalid,
input_3_axis_tlast,
input_3_axis_tdest,
input_3_axis_tuser,
output_0_axis_tready,
output_1_axis_tready,
output_2_axis_tready,
output_3_axis_tready);
$to_myhdl(input_0_axis_tready,
input_1_axis_tready,
input_2_axis_tready,
input_3_axis_tready,
output_0_axis_tdata,
output_0_axis_tkeep,
output_0_axis_tvalid,
output_0_axis_tlast,
output_0_axis_tdest,
output_0_axis_tuser,
output_1_axis_tdata,
output_1_axis_tkeep,
output_1_axis_tvalid,
output_1_axis_tlast,
output_1_axis_tdest,
output_1_axis_tuser,
output_2_axis_tdata,
output_2_axis_tkeep,
output_2_axis_tvalid,
output_2_axis_tlast,
output_2_axis_tdest,
output_2_axis_tuser,
output_3_axis_tdata,
output_3_axis_tkeep,
output_3_axis_tvalid,
output_3_axis_tlast,
output_3_axis_tdest,
output_3_axis_tuser);
$from_myhdl(
clk,
rst,
current_test,
input_0_axis_tdata,
input_0_axis_tkeep,
input_0_axis_tvalid,
input_0_axis_tlast,
input_0_axis_tdest,
input_0_axis_tuser,
input_1_axis_tdata,
input_1_axis_tkeep,
input_1_axis_tvalid,
input_1_axis_tlast,
input_1_axis_tdest,
input_1_axis_tuser,
input_2_axis_tdata,
input_2_axis_tkeep,
input_2_axis_tvalid,
input_2_axis_tlast,
input_2_axis_tdest,
input_2_axis_tuser,
input_3_axis_tdata,
input_3_axis_tkeep,
input_3_axis_tvalid,
input_3_axis_tlast,
input_3_axis_tdest,
input_3_axis_tuser,
output_0_axis_tready,
output_1_axis_tready,
output_2_axis_tready,
output_3_axis_tready
);
$to_myhdl(
input_0_axis_tready,
input_1_axis_tready,
input_2_axis_tready,
input_3_axis_tready,
output_0_axis_tdata,
output_0_axis_tkeep,
output_0_axis_tvalid,
output_0_axis_tlast,
output_0_axis_tdest,
output_0_axis_tuser,
output_1_axis_tdata,
output_1_axis_tkeep,
output_1_axis_tvalid,
output_1_axis_tlast,
output_1_axis_tdest,
output_1_axis_tuser,
output_2_axis_tdata,
output_2_axis_tkeep,
output_2_axis_tvalid,
output_2_axis_tlast,
output_2_axis_tdest,
output_2_axis_tuser,
output_3_axis_tdata,
output_3_axis_tkeep,
output_3_axis_tvalid,
output_3_axis_tlast,
output_3_axis_tdest,
output_3_axis_tuser
);
// dump file
$dumpfile("test_axis_switch_64_4x4.lxt");

201
lib/axis/tb/test_axis_tap.py
View File

@ -26,62 +26,31 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_tap'
testbench = 'test_%s' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_axis_tap(clk,
rst,
current_test,
tap_axis_tdata,
tap_axis_tvalid,
tap_axis_tready,
tap_axis_tlast,
tap_axis_tuser,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
tap_axis_tdata=tap_axis_tdata,
tap_axis_tvalid=tap_axis_tvalid,
tap_axis_tready=tap_axis_tready,
tap_axis_tlast=tap_axis_tlast,
tap_axis_tuser=tap_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
DATA_WIDTH = 8
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
tap_axis_tdata = Signal(intbv(0)[8:])
tap_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
tap_axis_tvalid = Signal(bool(0))
tap_axis_tready = Signal(bool(1))
tap_axis_tlast = Signal(bool(0))
@ -89,55 +58,65 @@ def bench():
output_axis_tready = Signal(bool(0))
# Outputs
output_axis_tdata = Signal(intbv(0)[8:])
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=tap_axis_tdata,
tvalid=tap_axis_tvalid,
tready=tap_axis_tready,
tlast=tap_axis_tlast,
tuser=tap_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
source = axis_ep.AXIStreamSource()
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
source_logic = source.create_logic(
clk,
rst,
tdata=tap_axis_tdata,
tvalid=tap_axis_tvalid,
tready=tap_axis_tready,
tlast=tap_axis_tlast,
tuser=tap_axis_tuser,
pause=source_pause,
name='source'
)
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink'
)
# DUT
dut = dut_axis_tap(clk,
rst,
current_test,
if os.system(build_cmd):
raise Exception("Error running build command")
tap_axis_tdata,
tap_axis_tvalid,
tap_axis_tready,
tap_axis_tlast,
tap_axis_tuser,
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser)
tap_axis_tdata=tap_axis_tdata,
tap_axis_tvalid=tap_axis_tvalid,
tap_axis_tready=tap_axis_tready,
tap_axis_tlast=tap_axis_tlast,
tap_axis_tuser=tap_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser
)
@always(delay(4))
def clkgen():
@ -164,16 +143,14 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -187,16 +164,14 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -210,7 +185,7 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield delay(64)
@ -224,9 +199,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -240,7 +213,7 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield delay(64)
@ -254,9 +227,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame.user[-1]
@ -274,8 +245,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
yield output_axis_tlast.posedge
@ -284,15 +255,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -310,8 +277,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while tap_axis_tvalid or output_axis_tvalid:
@ -325,15 +292,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -351,8 +314,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while tap_axis_tvalid or output_axis_tvalid:
@ -366,15 +329,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame.user[-1]
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame.user[-1]
@ -389,16 +348,14 @@ def bench():
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame.user = 1
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
assert rx_frame.user[-1]
@ -407,7 +364,7 @@ def bench():
raise StopSimulation
return dut, source, sink, clkgen, check
return dut, source_logic, sink_logic, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))

44
lib/axis/tb/test_axis_tap.v
View File

@ -24,16 +24,22 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1 ns / 1 ps
`timescale 1ns / 1ps
/*
* Testbench for axis_tap
*/
module test_axis_tap;
// Parameters
parameter DATA_WIDTH = 8;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] tap_axis_tdata = 0;
reg [DATA_WIDTH-1:0] tap_axis_tdata = 0;
reg tap_axis_tvalid = 0;
reg tap_axis_tready = 0;
reg tap_axis_tlast = 0;
@ -41,26 +47,30 @@ reg tap_axis_tuser = 0;
reg output_axis_tready = 0;
// Outputs
wire [7:0] output_axis_tdata;
wire [DATA_WIDTH-1:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
tap_axis_tdata,
tap_axis_tvalid,
tap_axis_tready,
tap_axis_tlast,
tap_axis_tuser,
output_axis_tready);
$to_myhdl(output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
$from_myhdl(
clk,
rst,
current_test,
tap_axis_tdata,
tap_axis_tvalid,
tap_axis_tready,
tap_axis_tlast,
tap_axis_tuser,
output_axis_tready
);
$to_myhdl(
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser
);
// dump file
$dumpfile("test_axis_tap.lxt");
@ -68,7 +78,7 @@ initial begin
end
axis_tap #(
.DATA_WIDTH(8)
.DATA_WIDTH(DATA_WIDTH)
)
UUT (
.clk(clk),

218
lib/axis/tb/test_axis_tap_64.py
View File

@ -26,67 +26,33 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_tap_64'
testbench = 'test_%s' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_axis_tap_64(clk,
rst,
current_test,
tap_axis_tdata,
tap_axis_tkeep,
tap_axis_tvalid,
tap_axis_tready,
tap_axis_tlast,
tap_axis_tuser,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
tap_axis_tdata=tap_axis_tdata,
tap_axis_tkeep=tap_axis_tkeep,
tap_axis_tvalid=tap_axis_tvalid,
tap_axis_tready=tap_axis_tready,
tap_axis_tlast=tap_axis_tlast,
tap_axis_tuser=tap_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
DATA_WIDTH = 64
KEEP_WIDTH = (DATA_WIDTH/8)
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
tap_axis_tdata = Signal(intbv(0)[64:])
tap_axis_tkeep = Signal(intbv(0)[8:])
tap_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
tap_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
tap_axis_tvalid = Signal(bool(0))
tap_axis_tready = Signal(bool(1))
tap_axis_tlast = Signal(bool(0))
@ -94,60 +60,70 @@ def bench():
output_axis_tready = Signal(bool(0))
# Outputs
output_axis_tdata = Signal(intbv(0)[64:])
output_axis_tkeep = Signal(intbv(0)[8:])
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=tap_axis_tdata,
tkeep=tap_axis_tkeep,
tvalid=tap_axis_tvalid,
tready=tap_axis_tready,
tlast=tap_axis_tlast,
tuser=tap_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
source = axis_ep.AXIStreamSource()
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
source_logic = source.create_logic(
clk,
rst,
tdata=tap_axis_tdata,
tkeep=tap_axis_tkeep,
tvalid=tap_axis_tvalid,
tready=tap_axis_tready,
tlast=tap_axis_tlast,
tuser=tap_axis_tuser,
pause=source_pause,
name='source'
)
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink'
)
# DUT
dut = dut_axis_tap_64(clk,
rst,
current_test,
if os.system(build_cmd):
raise Exception("Error running build command")
tap_axis_tdata,
tap_axis_tkeep,
tap_axis_tvalid,
tap_axis_tready,
tap_axis_tlast,
tap_axis_tuser,
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser)
tap_axis_tdata=tap_axis_tdata,
tap_axis_tkeep=tap_axis_tkeep,
tap_axis_tvalid=tap_axis_tvalid,
tap_axis_tready=tap_axis_tready,
tap_axis_tlast=tap_axis_tlast,
tap_axis_tuser=tap_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser
)
@always(delay(4))
def clkgen():
@ -174,16 +150,14 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -197,16 +171,14 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -220,7 +192,7 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield delay(64)
@ -234,9 +206,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
@ -250,7 +220,7 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield delay(64)
@ -264,9 +234,7 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame.user[-1]
@ -284,8 +252,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
yield output_axis_tlast.posedge
@ -294,15 +262,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -320,8 +284,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while tap_axis_tvalid or output_axis_tvalid:
@ -335,15 +299,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame2
@ -361,8 +321,8 @@ def bench():
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
source_queue.put(test_frame1)
source_queue.put(test_frame2)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while tap_axis_tvalid or output_axis_tvalid:
@ -376,15 +336,11 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame.user[-1]
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame.user[-1]
@ -399,16 +355,14 @@ def bench():
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame.user = 1
source_queue.put(test_frame)
source.send(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert rx_frame == test_frame
assert rx_frame.user[-1]
@ -417,7 +371,7 @@ def bench():
raise StopSimulation
return dut, source, sink, clkgen, check
return dut, source_logic, sink_logic, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))

55
lib/axis/tb/test_axis_tap_64.v
View File

@ -24,17 +24,24 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1 ns / 1 ps
`timescale 1ns / 1ps
/*
* Testbench for axis_tap_64
*/
module test_axis_tap_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_WIDTH = (DATA_WIDTH/8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [63:0] tap_axis_tdata = 0;
reg [7:0] tap_axis_tkeep = 0;
reg [DATA_WIDTH-1:0] tap_axis_tdata = 0;
reg [DATA_WIDTH-1:0] tap_axis_tkeep = 0;
reg tap_axis_tvalid = 0;
reg tap_axis_tready = 0;
reg tap_axis_tlast = 0;
@ -42,29 +49,33 @@ reg tap_axis_tuser = 0;
reg output_axis_tready = 0;
// Outputs
wire [63:0] output_axis_tdata;
wire [7:0] output_axis_tkeep;
wire [DATA_WIDTH-1:0] output_axis_tdata;
wire [DATA_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
tap_axis_tdata,
tap_axis_tkeep,
tap_axis_tvalid,
tap_axis_tready,
tap_axis_tlast,
tap_axis_tuser,
output_axis_tready);
$to_myhdl(output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
$from_myhdl(
clk,
rst,
current_test,
tap_axis_tdata,
tap_axis_tkeep,
tap_axis_tvalid,
tap_axis_tready,
tap_axis_tlast,
tap_axis_tuser,
output_axis_tready
);
$to_myhdl(
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser
);
// dump file
$dumpfile("test_axis_tap_64.lxt");
@ -72,8 +83,8 @@ initial begin
end
axis_tap_64 #(
.DATA_WIDTH(64),
.KEEP_WIDTH(8)
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH)
)
UUT (
.clk(clk),

165
lib/axis/tb/test_ll_axis_bridge.py
View File

@ -26,118 +26,95 @@ THE SOFTWARE.
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
import ll_ep
module = 'll_axis_bridge'
testbench = 'test_%s' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_ll_axis_bridge(clk,
rst,
current_test,
ll_data_in,
ll_sof_in_n,
ll_eof_in_n,
ll_src_rdy_in_n,
ll_dst_rdy_out_n,
axis_tdata,
axis_tvalid,
axis_tready,
axis_tlast):
os.system(build_cmd)
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
ll_data_in=ll_data_in,
ll_sof_in_n=ll_sof_in_n,
ll_eof_in_n=ll_eof_in_n,
ll_src_rdy_in_n=ll_src_rdy_in_n,
ll_dst_rdy_out_n=ll_dst_rdy_out_n,
axis_tdata=axis_tdata,
axis_tvalid=axis_tvalid,
axis_tready=axis_tready,
axis_tlast=axis_tlast)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
DATA_WIDTH = 8
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
ll_data_in = Signal(intbv(0)[8:])
ll_data_in = Signal(intbv(0)[DATA_WIDTH:])
ll_sof_in_n = Signal(bool(1))
ll_eof_in_n = Signal(bool(1))
ll_src_rdy_in_n = Signal(bool(1))
axis_tready = Signal(bool(0))
# Outputs
axis_tdata = Signal(intbv(0)[8:])
axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
axis_tvalid = Signal(bool(0))
axis_tlast = Signal(bool(0))
ll_dst_rdy_out_n = Signal(bool(1))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = ll_ep.LocalLinkSource(clk,
rst,
data_out=ll_data_in,
sof_out_n=ll_sof_in_n,
eof_out_n=ll_eof_in_n,
src_rdy_out_n=ll_src_rdy_in_n,
dst_rdy_in_n=ll_dst_rdy_out_n,
fifo=source_queue,
pause=source_pause,
name='source')
source = ll_ep.LocalLinkSource()
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=axis_tdata,
tvalid=axis_tvalid,
tready=axis_tready,
tlast=axis_tlast,
fifo=sink_queue,
pause=sink_pause,
name='sink')
source_logic = source.create_logic(
clk,
rst,
data_out=ll_data_in,
sof_out_n=ll_sof_in_n,
eof_out_n=ll_eof_in_n,
src_rdy_out_n=ll_src_rdy_in_n,
dst_rdy_in_n=ll_dst_rdy_out_n,
pause=source_pause,
name='source'
)
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
clk,
rst,
tdata=axis_tdata,
tvalid=axis_tvalid,
tready=axis_tready,
tlast=axis_tlast,
pause=sink_pause,
name='sink'
)
# DUT
dut = dut_ll_axis_bridge(clk,
rst,
current_test,
if os.system(build_cmd):
raise Exception("Error running build command")
ll_data_in,
ll_sof_in_n,
ll_eof_in_n,
ll_src_rdy_in_n,
ll_dst_rdy_out_n,
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
axis_tdata,
axis_tvalid,
axis_tready,
axis_tlast)
ll_data_in=ll_data_in,
ll_sof_in_n=ll_sof_in_n,
ll_eof_in_n=ll_eof_in_n,
ll_src_rdy_in_n=ll_src_rdy_in_n,
ll_dst_rdy_out_n=ll_dst_rdy_out_n,
axis_tdata=axis_tdata,
axis_tvalid=axis_tvalid,
axis_tready=axis_tready,
axis_tlast=axis_tlast
)
@always(delay(4))
def clkgen():
@ -160,24 +137,21 @@ def bench():
print("test 1: test packet")
current_test.next = 1
source_queue.put(bytearray(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'))
test_frame = bytearray(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source.send(test_frame)
yield clk.posedge
yield axis_tlast.negedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert bytearray(rx_frame) == (b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
assert bytearray(rx_frame) == test_frame
yield delay(100)
@ -185,10 +159,12 @@ def bench():
print("test 2: test packet with pauses")
current_test.next = 2
source_queue.put(bytearray(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'))
test_frame = bytearray(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source.send(test_frame)
yield clk.posedge
yield delay(64)
@ -209,20 +185,15 @@ def bench():
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame = sink.recv()
assert bytearray(rx_frame) == (b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
assert bytearray(rx_frame) == test_frame
yield delay(100)
raise StopSimulation
return dut, source, sink, clkgen, check
return dut, source_logic, sink_logic, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))

44
lib/axis/tb/test_ll_axis_bridge.v
View File

@ -24,16 +24,22 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1 ns / 1 ps
`timescale 1ns / 1ps
/*
* Testbench for ll_axis_bridge
*/
module test_ll_axis_bridge;
// Parameters
parameter DATA_WIDTH = 8;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] ll_data_in = 0;
reg [DATA_WIDTH-1:0] ll_data_in = 0;
reg ll_sof_in_n = 1;
reg ll_eof_in_n = 1;
reg ll_src_rdy_in_n = 1;
@ -41,31 +47,37 @@ reg axis_tready = 0;
// Outputs
wire ll_dst_rdy_out_n;
wire [7:0] axis_tdata;
wire [DATA_WIDTH-1:0] axis_tdata;
wire axis_tvalid;
wire axis_tlast;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
ll_data_in,
ll_sof_in_n,
ll_eof_in_n,
ll_src_rdy_in_n,
axis_tready);
$to_myhdl(axis_tdata,
axis_tvalid,
axis_tlast,
ll_dst_rdy_out_n);
$from_myhdl(
clk,
rst,
current_test,
ll_data_in,
ll_sof_in_n,
ll_eof_in_n,
ll_src_rdy_in_n,
axis_tready
);
$to_myhdl(
axis_tdata,
axis_tvalid,
axis_tlast,
ll_dst_rdy_out_n
);
// dump file
$dumpfile("test_ll_axis_bridge.lxt");
$dumpvars(0, test_ll_axis_bridge);
end
ll_axis_bridge
ll_axis_bridge #(
.DATA_WIDTH(DATA_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),

57
lib/axis/tb/test_priority_encoder.py
View File

@ -27,63 +27,50 @@ from myhdl import *
import os
module = 'priority_encoder'
testbench = 'test_%s' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_priority_encoder(clk,
rst,
current_test,
input_unencoded,
output_valid,
output_encoded,
output_unencoded):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_unencoded=input_unencoded,
output_valid=output_valid,
output_encoded=output_encoded,
output_unencoded=output_unencoded)
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
WIDTH = 32
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_unencoded = Signal(intbv(0)[32:])
input_unencoded = Signal(intbv(0)[WIDTH:])
# Outputs
output_valid = Signal(bool(0))
output_encoded = Signal(intbv(0)[5:])
output_unencoded = Signal(intbv(0)[32:])
output_unencoded = Signal(intbv(0)[WIDTH:])
# DUT
dut = dut_priority_encoder(clk,
rst,
current_test,
if os.system(build_cmd):
raise Exception("Error running build command")
input_unencoded,
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
output_valid,
output_encoded,
output_unencoded)
input_unencoded=input_unencoded,
output_valid=output_valid,
output_encoded=output_encoded,
output_unencoded=output_unencoded
)
@always(delay(4))
def clkgen():
@ -119,7 +106,7 @@ def bench():
print("test 2: two bits")
current_test.next = 2
for i in range(32):
for j in range(32):

25
lib/axis/tb/test_priority_encoder.v
View File

@ -24,11 +24,14 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1 ns / 1 ps
`timescale 1ns / 1ps
/*
* Testbench for priority_encoder
*/
module test_priority_encoder;
// parameters
// Parameters
localparam WIDTH = 32;
// Inputs
@ -45,13 +48,17 @@ wire [WIDTH-1:0] output_unencoded;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_unencoded);
$to_myhdl(output_valid,
output_encoded,
output_unencoded);
$from_myhdl(
clk,
rst,
current_test,
input_unencoded
);
$to_myhdl(
output_valid,
output_encoded,
output_unencoded
);
// dump file
$dumpfile("test_priority_encoder.lxt");