FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-14 06:43:18 +08:00
Code Issues Projects Releases Wiki Activity

Update .travis.yml

Browse Source
This commit is contained in:
Alex Forencich 2015-03-21 04:40:57 -07:00
parent 646ad2a293
commit 684f6967e5
1 changed files with 0 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
.travis.yml
View File

@ -1,8 +1,6 @@
language: python
python:
- "3.4"
virtualenv:
system_site_packages: true
before_install:
- export d=`pwd`
- sudo apt-get update -qq