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Workaround for MyHDL race condition

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This commit is contained in:
Alex Forencich 2018-10-31 13:42:33 -07:00
parent c08026277e
commit 68abccd0a1
1 changed files with 20 additions and 0 deletions
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20
tb/test_ip_eth_rx_64.py
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@ -286,6 +286,7 @@ def bench():
yield wait()
yield clk.posedge
yield sink.wait()
rx_frame = sink.recv()
@ -345,11 +346,13 @@ def bench():
yield wait()
yield clk.posedge
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame1
yield clk.posedge
yield sink.wait()
rx_frame = sink.recv()
@ -411,12 +414,14 @@ def bench():
yield wait()
yield clk.posedge
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame1
assert rx_frame.payload.user[-1]
yield clk.posedge
yield sink.wait()
rx_frame = sink.recv()
@ -478,11 +483,13 @@ def bench():
yield wait()
yield clk.posedge
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame1
yield clk.posedge
yield sink.wait()
rx_frame = sink.recv()
@ -544,11 +551,13 @@ def bench():
yield wait()
yield clk.posedge
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame1
yield clk.posedge
yield sink.wait()
rx_frame = sink.recv()
@ -611,12 +620,14 @@ def bench():
yield wait()
yield clk.posedge
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame1
assert rx_frame.payload.user[-1]
yield clk.posedge
yield sink.wait()
rx_frame = sink.recv()
@ -679,12 +690,14 @@ def bench():
yield wait()
yield clk.posedge
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame1
assert rx_frame.payload.user[-1]
yield clk.posedge
yield sink.wait()
rx_frame = sink.recv()
@ -748,12 +761,14 @@ def bench():
yield wait()
yield clk.posedge
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.payload.user[-1]
assert error_payload_early_termination_asserted
yield clk.posedge
yield sink.wait()
rx_frame = sink.recv()
@ -817,12 +832,14 @@ def bench():
yield wait()
yield clk.posedge
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.payload.user[-1]
assert error_payload_early_termination_asserted
yield clk.posedge
yield sink.wait()
rx_frame = sink.recv()
@ -884,6 +901,7 @@ def bench():
yield wait()
yield clk.posedge
yield sink.wait()
rx_frame = sink.recv()
@ -947,6 +965,7 @@ def bench():
yield wait()
yield clk.posedge
yield sink.wait()
rx_frame = sink.recv()
@ -1013,6 +1032,7 @@ def bench():
yield wait()
yield clk.posedge
yield sink.wait()
rx_frame = sink.recv()