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Add timing constraints for LED driver
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@ -49,6 +49,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
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# XDC files
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XDC_FILES = fpga.xdc
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XDC_FILES += led.tcl
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XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
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XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
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XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl
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12
example/fb2CG/fpga_10g/led.tcl
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12
example/fb2CG/fpga_10g/led.tcl
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@ -0,0 +1,12 @@
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# Timing constraints for led_sreg_driver
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foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == led_sreg_driver || REF_NAME == led_sreg_driver)}] {
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puts "Inserting timing constraints for led_sreg_driver instance $inst"
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set select_ffs [get_cells "$inst/led_sync_reg_1_reg[*] $inst/led_sync_reg_2_reg[*]"]
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if {[llength $select_ffs]} {
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set_property ASYNC_REG TRUE $select_ffs
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set_false_path -from [all_registers] -to [get_cells "$inst/led_sync_reg_1_reg[*]"]
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}
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}
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