From 6b18e56cb1644b4c98da9e215d85f1b0a05d5092 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Wed, 20 Oct 2021 17:29:12 -0700 Subject: [PATCH] Add default_nettype none and resetall directives --- example/ADM_PCIE_9V3/fpga_10g/rtl/debounce_switch.v | 4 ++++ example/ADM_PCIE_9V3/fpga_10g/rtl/eth_xcvr_phy_wrapper.v | 4 ++++ example/ADM_PCIE_9V3/fpga_10g/rtl/fpga.v | 4 ++++ example/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v | 4 ++++ example/ADM_PCIE_9V3/fpga_10g/rtl/sync_signal.v | 4 ++++ example/ADM_PCIE_9V3/fpga_25g/rtl/debounce_switch.v | 4 ++++ example/ADM_PCIE_9V3/fpga_25g/rtl/eth_xcvr_phy_wrapper.v | 4 ++++ example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v | 4 ++++ example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v | 4 ++++ example/ADM_PCIE_9V3/fpga_25g/rtl/sync_signal.v | 4 ++++ example/ATLYS/fpga/rtl/debounce_switch.v | 4 ++++ example/ATLYS/fpga/rtl/fpga.v | 4 ++++ example/ATLYS/fpga/rtl/fpga_core.v | 4 ++++ example/ATLYS/fpga/rtl/sync_signal.v | 4 ++++ example/AU200/fpga_10g/rtl/debounce_switch.v | 4 ++++ example/AU200/fpga_10g/rtl/eth_xcvr_phy_wrapper.v | 4 ++++ example/AU200/fpga_10g/rtl/fpga.v | 4 ++++ example/AU200/fpga_10g/rtl/fpga_core.v | 4 ++++ example/AU200/fpga_10g/rtl/sync_signal.v | 4 ++++ example/AU250/fpga_10g/rtl/debounce_switch.v | 4 ++++ example/AU250/fpga_10g/rtl/eth_xcvr_phy_wrapper.v | 4 ++++ example/AU250/fpga_10g/rtl/fpga.v | 4 ++++ example/AU250/fpga_10g/rtl/fpga_core.v | 4 ++++ example/AU250/fpga_10g/rtl/sync_signal.v | 4 ++++ example/AU280/fpga_10g/rtl/eth_xcvr_phy_wrapper.v | 4 ++++ example/AU280/fpga_10g/rtl/fpga.v | 4 ++++ example/AU280/fpga_10g/rtl/fpga_core.v | 4 ++++ example/AU280/fpga_10g/rtl/sync_signal.v | 4 ++++ example/AU50/fpga_10g/rtl/eth_xcvr_phy_wrapper.v | 4 ++++ example/AU50/fpga_10g/rtl/fpga.v | 4 ++++ example/AU50/fpga_10g/rtl/fpga_core.v | 4 ++++ example/AU50/fpga_10g/rtl/sync_signal.v | 4 ++++ example/Arty/fpga/rtl/debounce_switch.v | 4 ++++ example/Arty/fpga/rtl/fpga.v | 4 ++++ example/Arty/fpga/rtl/fpga_core.v | 4 ++++ example/Arty/fpga/rtl/sync_signal.v | 4 ++++ example/C10LP/fpga/rtl/debounce_switch.v | 4 ++++ example/C10LP/fpga/rtl/fpga.v | 4 ++++ example/C10LP/fpga/rtl/fpga_core.v | 4 ++++ example/C10LP/fpga/rtl/sync_signal.v | 4 ++++ example/DE2-115/fpga/rtl/debounce_switch.v | 4 ++++ example/DE2-115/fpga/rtl/fpga.v | 4 ++++ example/DE2-115/fpga/rtl/fpga_core.v | 4 ++++ example/DE2-115/fpga/rtl/hex_display.v | 4 ++++ example/DE2-115/fpga/rtl/sync_signal.v | 4 ++++ example/DE5-Net/fpga/rtl/debounce_switch.v | 4 ++++ example/DE5-Net/fpga/rtl/fpga.v | 4 ++++ example/DE5-Net/fpga/rtl/fpga_core.v | 4 ++++ example/DE5-Net/fpga/rtl/i2c_master.v | 4 ++++ example/DE5-Net/fpga/rtl/si570_i2c_init.v | 4 ++++ example/DE5-Net/fpga/rtl/sync_signal.v | 4 ++++ example/ExaNIC_X10/fpga/rtl/eth_xcvr_phy_wrapper.v | 4 ++++ example/ExaNIC_X10/fpga/rtl/fpga.v | 4 ++++ example/ExaNIC_X10/fpga/rtl/fpga_core.v | 4 ++++ example/ExaNIC_X10/fpga/rtl/sync_signal.v | 4 ++++ example/ExaNIC_X25/fpga_10g/rtl/eth_xcvr_phy_wrapper.v | 4 ++++ example/ExaNIC_X25/fpga_10g/rtl/fpga.v | 4 ++++ example/ExaNIC_X25/fpga_10g/rtl/fpga_core.v | 4 ++++ example/ExaNIC_X25/fpga_10g/rtl/sync_signal.v | 4 ++++ example/HTG9200/fpga_10g/rtl/debounce_switch.v | 4 ++++ example/HTG9200/fpga_10g/rtl/eth_xcvr_phy_wrapper.v | 4 ++++ example/HTG9200/fpga_10g/rtl/fpga.v | 4 ++++ example/HTG9200/fpga_10g/rtl/fpga_core.v | 4 ++++ example/HTG9200/fpga_10g/rtl/i2c_master.v | 4 ++++ example/HTG9200/fpga_10g/rtl/si5341_i2c_init.py | 4 ++++ example/HTG9200/fpga_10g/rtl/si5341_i2c_init.v | 4 ++++ example/HTG9200/fpga_10g/rtl/sync_signal.v | 4 ++++ example/HXT100G/fpga/rtl/debounce_switch.v | 4 ++++ example/HXT100G/fpga/rtl/eth_gth_phy_quad.v | 8 ++++++++ example/HXT100G/fpga/rtl/fpga.v | 8 ++++++++ example/HXT100G/fpga/rtl/fpga_core.v | 4 ++++ example/HXT100G/fpga/rtl/gth_i2c_init.v | 4 ++++ example/HXT100G/fpga/rtl/i2c_master.v | 4 ++++ example/HXT100G/fpga/rtl/sync_signal.v | 4 ++++ example/HXT100G/fpga_cxpt16/rtl/debounce_switch.v | 4 ++++ example/HXT100G/fpga_cxpt16/rtl/eth_gth_phy_quad.v | 8 ++++++++ example/HXT100G/fpga_cxpt16/rtl/fpga.v | 8 ++++++++ example/HXT100G/fpga_cxpt16/rtl/fpga_core.v | 4 ++++ example/HXT100G/fpga_cxpt16/rtl/gth_i2c_init.v | 4 ++++ example/HXT100G/fpga_cxpt16/rtl/i2c_master.v | 4 ++++ example/HXT100G/fpga_cxpt16/rtl/sync_signal.v | 4 ++++ example/KC705/fpga_gmii/rtl/debounce_switch.v | 4 ++++ example/KC705/fpga_gmii/rtl/fpga.v | 4 ++++ example/KC705/fpga_gmii/rtl/fpga_core.v | 4 ++++ example/KC705/fpga_gmii/rtl/sync_signal.v | 4 ++++ example/KC705/fpga_rgmii/rtl/debounce_switch.v | 4 ++++ example/KC705/fpga_rgmii/rtl/fpga.v | 4 ++++ example/KC705/fpga_rgmii/rtl/fpga_core.v | 4 ++++ example/KC705/fpga_rgmii/rtl/sync_signal.v | 4 ++++ example/KC705/fpga_sgmii/rtl/debounce_switch.v | 4 ++++ example/KC705/fpga_sgmii/rtl/fpga.v | 4 ++++ example/KC705/fpga_sgmii/rtl/fpga_core.v | 4 ++++ example/KC705/fpga_sgmii/rtl/sync_signal.v | 4 ++++ example/ML605/fpga_gmii/rtl/debounce_switch.v | 4 ++++ example/ML605/fpga_gmii/rtl/fpga.v | 4 ++++ example/ML605/fpga_gmii/rtl/fpga_core.v | 4 ++++ example/ML605/fpga_gmii/rtl/sync_signal.v | 4 ++++ example/ML605/fpga_rgmii/rtl/debounce_switch.v | 4 ++++ example/ML605/fpga_rgmii/rtl/fpga.v | 4 ++++ example/ML605/fpga_rgmii/rtl/fpga_core.v | 4 ++++ example/ML605/fpga_rgmii/rtl/sync_signal.v | 4 ++++ example/ML605/fpga_sgmii/rtl/debounce_switch.v | 4 ++++ example/ML605/fpga_sgmii/rtl/fpga.v | 4 ++++ example/ML605/fpga_sgmii/rtl/fpga_core.v | 4 ++++ example/ML605/fpga_sgmii/rtl/sync_signal.v | 4 ++++ example/NetFPGA_SUME/fpga/rtl/debounce_switch.v | 4 ++++ example/NetFPGA_SUME/fpga/rtl/fpga.v | 4 ++++ example/NetFPGA_SUME/fpga/rtl/fpga_core.v | 4 ++++ example/NetFPGA_SUME/fpga/rtl/i2c_master.v | 4 ++++ example/NetFPGA_SUME/fpga/rtl/si5324_i2c_init.v | 4 ++++ example/NexysVideo/fpga/rtl/debounce_switch.v | 4 ++++ example/NexysVideo/fpga/rtl/fpga.v | 4 ++++ example/NexysVideo/fpga/rtl/fpga_core.v | 4 ++++ example/NexysVideo/fpga/rtl/sync_signal.v | 4 ++++ example/S10DX_DK/fpga_10g/rtl/avst2axis.v | 4 ++++ example/S10DX_DK/fpga_10g/rtl/axis2avst.v | 4 ++++ example/S10DX_DK/fpga_10g/rtl/debounce_switch.v | 4 ++++ example/S10DX_DK/fpga_10g/rtl/eth_mac_quad_wrapper.v | 4 ++++ example/S10DX_DK/fpga_10g/rtl/fpga.v | 4 ++++ example/S10DX_DK/fpga_10g/rtl/fpga_core.v | 4 ++++ example/S10DX_DK/fpga_10g/rtl/sync_signal.v | 4 ++++ example/S10DX_DK/fpga_10g/rtl/xcvr_ctrl.v | 4 ++++ example/S10MX_DK/fpga_10g/rtl/eth_xcvr_phy_quad_wrapper.v | 4 ++++ example/S10MX_DK/fpga_10g/rtl/eth_xcvr_phy_wrapper.v | 4 ++++ example/S10MX_DK/fpga_10g/rtl/fpga.v | 4 ++++ example/S10MX_DK/fpga_10g/rtl/fpga_core.v | 4 ++++ example/S10MX_DK/fpga_10g/rtl/sync_signal.v | 4 ++++ example/VCU108/fpga_10g/rtl/debounce_switch.v | 4 ++++ example/VCU108/fpga_10g/rtl/eth_xcvr_phy_wrapper.v | 4 ++++ example/VCU108/fpga_10g/rtl/fpga.v | 4 ++++ example/VCU108/fpga_10g/rtl/fpga_core.v | 4 ++++ example/VCU108/fpga_10g/rtl/sync_signal.v | 4 ++++ example/VCU108/fpga_1g/rtl/debounce_switch.v | 4 ++++ example/VCU108/fpga_1g/rtl/fpga.v | 4 ++++ example/VCU108/fpga_1g/rtl/fpga_core.v | 4 ++++ example/VCU108/fpga_1g/rtl/sync_signal.v | 4 ++++ example/VCU118/fpga_10g/rtl/debounce_switch.v | 4 ++++ example/VCU118/fpga_10g/rtl/eth_xcvr_phy_wrapper.v | 4 ++++ example/VCU118/fpga_10g/rtl/fpga.v | 4 ++++ example/VCU118/fpga_10g/rtl/fpga_core.v | 4 ++++ example/VCU118/fpga_10g/rtl/mdio_master.v | 4 ++++ example/VCU118/fpga_10g/rtl/sync_signal.v | 4 ++++ example/VCU118/fpga_1g/rtl/debounce_switch.v | 4 ++++ example/VCU118/fpga_1g/rtl/fpga.v | 4 ++++ example/VCU118/fpga_1g/rtl/fpga_core.v | 4 ++++ example/VCU118/fpga_1g/rtl/mdio_master.v | 4 ++++ example/VCU118/fpga_1g/rtl/sync_signal.v | 4 ++++ example/VCU118/fpga_25g/rtl/debounce_switch.v | 4 ++++ example/VCU118/fpga_25g/rtl/eth_xcvr_phy_wrapper.v | 4 ++++ example/VCU118/fpga_25g/rtl/fpga.v | 4 ++++ example/VCU118/fpga_25g/rtl/fpga_core.v | 4 ++++ example/VCU118/fpga_25g/rtl/mdio_master.v | 4 ++++ example/VCU118/fpga_25g/rtl/sync_signal.v | 4 ++++ example/VCU1525/fpga_10g/rtl/debounce_switch.v | 4 ++++ example/VCU1525/fpga_10g/rtl/eth_xcvr_phy_wrapper.v | 4 ++++ example/VCU1525/fpga_10g/rtl/fpga.v | 4 ++++ example/VCU1525/fpga_10g/rtl/fpga_core.v | 4 ++++ example/VCU1525/fpga_10g/rtl/sync_signal.v | 4 ++++ example/ZCU102/fpga/rtl/debounce_switch.v | 4 ++++ example/ZCU102/fpga/rtl/eth_xcvr_phy_wrapper.v | 4 ++++ example/ZCU102/fpga/rtl/fpga.v | 4 ++++ example/ZCU102/fpga/rtl/fpga_core.v | 4 ++++ example/ZCU102/fpga/rtl/sync_signal.v | 4 ++++ example/ZCU106/fpga/rtl/debounce_switch.v | 4 ++++ example/ZCU106/fpga/rtl/eth_xcvr_phy_wrapper.v | 4 ++++ example/ZCU106/fpga/rtl/fpga.v | 4 ++++ example/ZCU106/fpga/rtl/fpga_core.v | 4 ++++ example/ZCU106/fpga/rtl/sync_signal.v | 4 ++++ example/fb2CG/fpga_10g/rtl/eth_xcvr_phy_wrapper.v | 4 ++++ example/fb2CG/fpga_10g/rtl/fpga.v | 4 ++++ example/fb2CG/fpga_10g/rtl/fpga_core.v | 4 ++++ example/fb2CG/fpga_10g/rtl/led_sreg_driver.v | 4 ++++ example/fb2CG/fpga_10g/rtl/sync_signal.v | 4 ++++ rtl/arp.v | 4 ++++ rtl/arp_cache.v | 4 ++++ rtl/arp_eth_rx.v | 4 ++++ rtl/arp_eth_tx.v | 4 ++++ rtl/axis_baser_rx_64.v | 4 ++++ rtl/axis_baser_tx_64.v | 4 ++++ rtl/axis_eth_fcs.v | 4 ++++ rtl/axis_eth_fcs_check.v | 4 ++++ rtl/axis_eth_fcs_check_64.v | 4 ++++ rtl/axis_eth_fcs_insert.v | 4 ++++ rtl/axis_eth_fcs_insert_64.v | 4 ++++ rtl/axis_gmii_rx.v | 4 ++++ rtl/axis_gmii_tx.v | 4 ++++ rtl/axis_xgmii_rx_32.v | 4 ++++ rtl/axis_xgmii_rx_64.v | 4 ++++ rtl/axis_xgmii_tx_32.v | 4 ++++ rtl/axis_xgmii_tx_64.v | 4 ++++ rtl/eth_arb_mux.v | 4 ++++ rtl/eth_axis_rx.v | 4 ++++ rtl/eth_axis_tx.v | 4 ++++ rtl/eth_demux.v | 4 ++++ rtl/eth_mac_10g.v | 4 ++++ rtl/eth_mac_10g_fifo.v | 4 ++++ rtl/eth_mac_1g.v | 4 ++++ rtl/eth_mac_1g_fifo.v | 4 ++++ rtl/eth_mac_1g_gmii.v | 4 ++++ rtl/eth_mac_1g_gmii_fifo.v | 4 ++++ rtl/eth_mac_1g_rgmii.v | 4 ++++ rtl/eth_mac_1g_rgmii_fifo.v | 4 ++++ rtl/eth_mac_mii.v | 4 ++++ rtl/eth_mac_mii_fifo.v | 4 ++++ rtl/eth_mac_phy_10g.v | 4 ++++ rtl/eth_mac_phy_10g_fifo.v | 4 ++++ rtl/eth_mac_phy_10g_rx.v | 4 ++++ rtl/eth_mac_phy_10g_tx.v | 4 ++++ rtl/eth_mux.v | 4 ++++ rtl/eth_phy_10g.v | 4 ++++ rtl/eth_phy_10g_rx.v | 4 ++++ rtl/eth_phy_10g_rx_ber_mon.v | 4 ++++ rtl/eth_phy_10g_rx_frame_sync.v | 4 ++++ rtl/eth_phy_10g_rx_if.v | 4 ++++ rtl/eth_phy_10g_rx_watchdog.v | 4 ++++ rtl/eth_phy_10g_tx.v | 4 ++++ rtl/eth_phy_10g_tx_if.v | 4 ++++ rtl/gmii_phy_if.v | 4 ++++ rtl/iddr.v | 4 ++++ rtl/ip.v | 4 ++++ rtl/ip_64.v | 4 ++++ rtl/ip_arb_mux.v | 4 ++++ rtl/ip_complete.v | 4 ++++ rtl/ip_complete_64.v | 4 ++++ rtl/ip_demux.v | 4 ++++ rtl/ip_eth_rx.v | 4 ++++ rtl/ip_eth_rx_64.v | 4 ++++ rtl/ip_eth_tx.v | 4 ++++ rtl/ip_eth_tx_64.v | 4 ++++ rtl/ip_mux.v | 4 ++++ rtl/lfsr.v | 4 ++++ rtl/mii_phy_if.v | 4 ++++ rtl/oddr.v | 4 ++++ rtl/ptp_clock.v | 4 ++++ rtl/ptp_clock_cdc.v | 4 ++++ rtl/ptp_perout.v | 4 ++++ rtl/ptp_tag_insert.v | 4 ++++ rtl/ptp_ts_extract.v | 4 ++++ rtl/rgmii_phy_if.v | 4 ++++ rtl/ssio_ddr_in.v | 4 ++++ rtl/ssio_ddr_in_diff.v | 4 ++++ rtl/ssio_ddr_out.v | 4 ++++ rtl/ssio_ddr_out_diff.v | 4 ++++ rtl/ssio_sdr_in.v | 4 ++++ rtl/ssio_sdr_in_diff.v | 4 ++++ rtl/ssio_sdr_out.v | 4 ++++ rtl/ssio_sdr_out_diff.v | 4 ++++ rtl/udp.v | 4 ++++ rtl/udp_64.v | 4 ++++ rtl/udp_arb_mux.v | 4 ++++ rtl/udp_checksum_gen.v | 4 ++++ rtl/udp_checksum_gen_64.v | 4 ++++ rtl/udp_complete.v | 4 ++++ rtl/udp_complete_64.v | 4 ++++ rtl/udp_demux.v | 4 ++++ rtl/udp_ip_rx.v | 4 ++++ rtl/udp_ip_rx_64.v | 4 ++++ rtl/udp_ip_tx.v | 4 ++++ rtl/udp_ip_tx_64.v | 4 ++++ rtl/udp_mux.v | 4 ++++ rtl/xgmii_baser_dec_64.v | 4 ++++ rtl/xgmii_baser_enc_64.v | 4 ++++ rtl/xgmii_deinterleave.v | 4 ++++ rtl/xgmii_interleave.v | 4 ++++ 264 files changed, 1072 insertions(+) diff --git a/example/ADM_PCIE_9V3/fpga_10g/rtl/debounce_switch.v b/example/ADM_PCIE_9V3/fpga_10g/rtl/debounce_switch.v index bb631cc3..8e93a50c 100644 --- a/example/ADM_PCIE_9V3/fpga_10g/rtl/debounce_switch.v +++ b/example/ADM_PCIE_9V3/fpga_10g/rtl/debounce_switch.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes switch and button inputs with a slow sampled shift register @@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin end endmodule + +`resetall diff --git a/example/ADM_PCIE_9V3/fpga_10g/rtl/eth_xcvr_phy_wrapper.v b/example/ADM_PCIE_9V3/fpga_10g/rtl/eth_xcvr_phy_wrapper.v index 9798e758..acac5e3f 100644 --- a/example/ADM_PCIE_9V3/fpga_10g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/ADM_PCIE_9V3/fpga_10g/rtl/eth_xcvr_phy_wrapper.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * Transceiver and PHY wrapper @@ -293,3 +295,5 @@ phy_inst ( ); endmodule + +`resetall diff --git a/example/ADM_PCIE_9V3/fpga_10g/rtl/fpga.v b/example/ADM_PCIE_9V3/fpga_10g/rtl/fpga.v index 1fedf9f2..f6e443d2 100644 --- a/example/ADM_PCIE_9V3/fpga_10g/rtl/fpga.v +++ b/example/ADM_PCIE_9V3/fpga_10g/rtl/fpga.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA top-level module @@ -782,3 +784,5 @@ core_inst ( ); endmodule + +`resetall diff --git a/example/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v b/example/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v index 81246eaf..cf6f9280 100644 --- a/example/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v +++ b/example/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA core logic @@ -659,3 +661,5 @@ udp_payload_fifo ( ); endmodule + +`resetall diff --git a/example/ADM_PCIE_9V3/fpga_10g/rtl/sync_signal.v b/example/ADM_PCIE_9V3/fpga_10g/rtl/sync_signal.v index b2a8ce3d..74b855fa 100644 --- a/example/ADM_PCIE_9V3/fpga_10g/rtl/sync_signal.v +++ b/example/ADM_PCIE_9V3/fpga_10g/rtl/sync_signal.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes an asyncronous signal to a given clock by using a pipeline of @@ -56,3 +58,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/ADM_PCIE_9V3/fpga_25g/rtl/debounce_switch.v b/example/ADM_PCIE_9V3/fpga_25g/rtl/debounce_switch.v index bb631cc3..8e93a50c 100644 --- a/example/ADM_PCIE_9V3/fpga_25g/rtl/debounce_switch.v +++ b/example/ADM_PCIE_9V3/fpga_25g/rtl/debounce_switch.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes switch and button inputs with a slow sampled shift register @@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin end endmodule + +`resetall diff --git a/example/ADM_PCIE_9V3/fpga_25g/rtl/eth_xcvr_phy_wrapper.v b/example/ADM_PCIE_9V3/fpga_25g/rtl/eth_xcvr_phy_wrapper.v index 9798e758..acac5e3f 100644 --- a/example/ADM_PCIE_9V3/fpga_25g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/ADM_PCIE_9V3/fpga_25g/rtl/eth_xcvr_phy_wrapper.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * Transceiver and PHY wrapper @@ -293,3 +295,5 @@ phy_inst ( ); endmodule + +`resetall diff --git a/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v b/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v index 707cf4df..43714da4 100644 --- a/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v +++ b/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA top-level module @@ -806,3 +808,5 @@ core_inst ( ); endmodule + +`resetall diff --git a/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v b/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v index 1e5d774a..670416bb 100644 --- a/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v +++ b/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA core logic @@ -659,3 +661,5 @@ udp_payload_fifo ( ); endmodule + +`resetall diff --git a/example/ADM_PCIE_9V3/fpga_25g/rtl/sync_signal.v b/example/ADM_PCIE_9V3/fpga_25g/rtl/sync_signal.v index b2a8ce3d..74b855fa 100644 --- a/example/ADM_PCIE_9V3/fpga_25g/rtl/sync_signal.v +++ b/example/ADM_PCIE_9V3/fpga_25g/rtl/sync_signal.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes an asyncronous signal to a given clock by using a pipeline of @@ -56,3 +58,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/ATLYS/fpga/rtl/debounce_switch.v b/example/ATLYS/fpga/rtl/debounce_switch.v index bb631cc3..8e93a50c 100644 --- a/example/ATLYS/fpga/rtl/debounce_switch.v +++ b/example/ATLYS/fpga/rtl/debounce_switch.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes switch and button inputs with a slow sampled shift register @@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin end endmodule + +`resetall diff --git a/example/ATLYS/fpga/rtl/fpga.v b/example/ATLYS/fpga/rtl/fpga.v index addf6c3a..29ebff31 100644 --- a/example/ATLYS/fpga/rtl/fpga.v +++ b/example/ATLYS/fpga/rtl/fpga.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA top-level module @@ -222,3 +224,5 @@ core_inst ( ); endmodule + +`resetall diff --git a/example/ATLYS/fpga/rtl/fpga_core.v b/example/ATLYS/fpga/rtl/fpga_core.v index 36a07e14..a2096012 100644 --- a/example/ATLYS/fpga/rtl/fpga_core.v +++ b/example/ATLYS/fpga/rtl/fpga_core.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA core logic @@ -581,3 +583,5 @@ udp_payload_fifo ( ); endmodule + +`resetall diff --git a/example/ATLYS/fpga/rtl/sync_signal.v b/example/ATLYS/fpga/rtl/sync_signal.v index b2a8ce3d..74b855fa 100644 --- a/example/ATLYS/fpga/rtl/sync_signal.v +++ b/example/ATLYS/fpga/rtl/sync_signal.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes an asyncronous signal to a given clock by using a pipeline of @@ -56,3 +58,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/AU200/fpga_10g/rtl/debounce_switch.v b/example/AU200/fpga_10g/rtl/debounce_switch.v index bb631cc3..8e93a50c 100644 --- a/example/AU200/fpga_10g/rtl/debounce_switch.v +++ b/example/AU200/fpga_10g/rtl/debounce_switch.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes switch and button inputs with a slow sampled shift register @@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin end endmodule + +`resetall diff --git a/example/AU200/fpga_10g/rtl/eth_xcvr_phy_wrapper.v b/example/AU200/fpga_10g/rtl/eth_xcvr_phy_wrapper.v index 9798e758..acac5e3f 100644 --- a/example/AU200/fpga_10g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/AU200/fpga_10g/rtl/eth_xcvr_phy_wrapper.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * Transceiver and PHY wrapper @@ -293,3 +295,5 @@ phy_inst ( ); endmodule + +`resetall diff --git a/example/AU200/fpga_10g/rtl/fpga.v b/example/AU200/fpga_10g/rtl/fpga.v index 52578cff..6917bc67 100644 --- a/example/AU200/fpga_10g/rtl/fpga.v +++ b/example/AU200/fpga_10g/rtl/fpga.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA top-level module @@ -898,3 +900,5 @@ core_inst ( ); endmodule + +`resetall diff --git a/example/AU200/fpga_10g/rtl/fpga_core.v b/example/AU200/fpga_10g/rtl/fpga_core.v index a840ea01..c8c2c444 100644 --- a/example/AU200/fpga_10g/rtl/fpga_core.v +++ b/example/AU200/fpga_10g/rtl/fpga_core.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA core logic @@ -662,3 +664,5 @@ udp_payload_fifo ( ); endmodule + +`resetall diff --git a/example/AU200/fpga_10g/rtl/sync_signal.v b/example/AU200/fpga_10g/rtl/sync_signal.v index b2a8ce3d..74b855fa 100644 --- a/example/AU200/fpga_10g/rtl/sync_signal.v +++ b/example/AU200/fpga_10g/rtl/sync_signal.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes an asyncronous signal to a given clock by using a pipeline of @@ -56,3 +58,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/AU250/fpga_10g/rtl/debounce_switch.v b/example/AU250/fpga_10g/rtl/debounce_switch.v index bb631cc3..8e93a50c 100644 --- a/example/AU250/fpga_10g/rtl/debounce_switch.v +++ b/example/AU250/fpga_10g/rtl/debounce_switch.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes switch and button inputs with a slow sampled shift register @@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin end endmodule + +`resetall diff --git a/example/AU250/fpga_10g/rtl/eth_xcvr_phy_wrapper.v b/example/AU250/fpga_10g/rtl/eth_xcvr_phy_wrapper.v index 9798e758..acac5e3f 100644 --- a/example/AU250/fpga_10g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/AU250/fpga_10g/rtl/eth_xcvr_phy_wrapper.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * Transceiver and PHY wrapper @@ -293,3 +295,5 @@ phy_inst ( ); endmodule + +`resetall diff --git a/example/AU250/fpga_10g/rtl/fpga.v b/example/AU250/fpga_10g/rtl/fpga.v index 52578cff..6917bc67 100644 --- a/example/AU250/fpga_10g/rtl/fpga.v +++ b/example/AU250/fpga_10g/rtl/fpga.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA top-level module @@ -898,3 +900,5 @@ core_inst ( ); endmodule + +`resetall diff --git a/example/AU250/fpga_10g/rtl/fpga_core.v b/example/AU250/fpga_10g/rtl/fpga_core.v index a840ea01..c8c2c444 100644 --- a/example/AU250/fpga_10g/rtl/fpga_core.v +++ b/example/AU250/fpga_10g/rtl/fpga_core.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA core logic @@ -662,3 +664,5 @@ udp_payload_fifo ( ); endmodule + +`resetall diff --git a/example/AU250/fpga_10g/rtl/sync_signal.v b/example/AU250/fpga_10g/rtl/sync_signal.v index b2a8ce3d..74b855fa 100644 --- a/example/AU250/fpga_10g/rtl/sync_signal.v +++ b/example/AU250/fpga_10g/rtl/sync_signal.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes an asyncronous signal to a given clock by using a pipeline of @@ -56,3 +58,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/AU280/fpga_10g/rtl/eth_xcvr_phy_wrapper.v b/example/AU280/fpga_10g/rtl/eth_xcvr_phy_wrapper.v index 9798e758..acac5e3f 100644 --- a/example/AU280/fpga_10g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/AU280/fpga_10g/rtl/eth_xcvr_phy_wrapper.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * Transceiver and PHY wrapper @@ -293,3 +295,5 @@ phy_inst ( ); endmodule + +`resetall diff --git a/example/AU280/fpga_10g/rtl/fpga.v b/example/AU280/fpga_10g/rtl/fpga.v index 3a026ab9..210024d7 100644 --- a/example/AU280/fpga_10g/rtl/fpga.v +++ b/example/AU280/fpga_10g/rtl/fpga.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA top-level module @@ -762,3 +764,5 @@ core_inst ( ); endmodule + +`resetall diff --git a/example/AU280/fpga_10g/rtl/fpga_core.v b/example/AU280/fpga_10g/rtl/fpga_core.v index e55921ac..3e970d84 100644 --- a/example/AU280/fpga_10g/rtl/fpga_core.v +++ b/example/AU280/fpga_10g/rtl/fpga_core.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA core logic @@ -647,3 +649,5 @@ udp_payload_fifo ( ); endmodule + +`resetall diff --git a/example/AU280/fpga_10g/rtl/sync_signal.v b/example/AU280/fpga_10g/rtl/sync_signal.v index b2a8ce3d..74b855fa 100644 --- a/example/AU280/fpga_10g/rtl/sync_signal.v +++ b/example/AU280/fpga_10g/rtl/sync_signal.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes an asyncronous signal to a given clock by using a pipeline of @@ -56,3 +58,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/AU50/fpga_10g/rtl/eth_xcvr_phy_wrapper.v b/example/AU50/fpga_10g/rtl/eth_xcvr_phy_wrapper.v index 9798e758..acac5e3f 100644 --- a/example/AU50/fpga_10g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/AU50/fpga_10g/rtl/eth_xcvr_phy_wrapper.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * Transceiver and PHY wrapper @@ -293,3 +295,5 @@ phy_inst ( ); endmodule + +`resetall diff --git a/example/AU50/fpga_10g/rtl/fpga.v b/example/AU50/fpga_10g/rtl/fpga.v index 90112604..f17738c8 100644 --- a/example/AU50/fpga_10g/rtl/fpga.v +++ b/example/AU50/fpga_10g/rtl/fpga.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA top-level module @@ -464,3 +466,5 @@ core_inst ( ); endmodule + +`resetall diff --git a/example/AU50/fpga_10g/rtl/fpga_core.v b/example/AU50/fpga_10g/rtl/fpga_core.v index bc0ebb13..a59896f6 100644 --- a/example/AU50/fpga_10g/rtl/fpga_core.v +++ b/example/AU50/fpga_10g/rtl/fpga_core.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA core logic @@ -614,3 +616,5 @@ udp_payload_fifo ( ); endmodule + +`resetall diff --git a/example/AU50/fpga_10g/rtl/sync_signal.v b/example/AU50/fpga_10g/rtl/sync_signal.v index b2a8ce3d..74b855fa 100644 --- a/example/AU50/fpga_10g/rtl/sync_signal.v +++ b/example/AU50/fpga_10g/rtl/sync_signal.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes an asyncronous signal to a given clock by using a pipeline of @@ -56,3 +58,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/Arty/fpga/rtl/debounce_switch.v b/example/Arty/fpga/rtl/debounce_switch.v index bb631cc3..8e93a50c 100644 --- a/example/Arty/fpga/rtl/debounce_switch.v +++ b/example/Arty/fpga/rtl/debounce_switch.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes switch and button inputs with a slow sampled shift register @@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin end endmodule + +`resetall diff --git a/example/Arty/fpga/rtl/fpga.v b/example/Arty/fpga/rtl/fpga.v index f881ee66..ea2f8f7c 100644 --- a/example/Arty/fpga/rtl/fpga.v +++ b/example/Arty/fpga/rtl/fpga.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA top-level module @@ -268,3 +270,5 @@ core_inst ( ); endmodule + +`resetall diff --git a/example/Arty/fpga/rtl/fpga_core.v b/example/Arty/fpga/rtl/fpga_core.v index 68e7c047..13ba63b7 100644 --- a/example/Arty/fpga/rtl/fpga_core.v +++ b/example/Arty/fpga/rtl/fpga_core.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA core logic @@ -588,3 +590,5 @@ udp_payload_fifo ( ); endmodule + +`resetall diff --git a/example/Arty/fpga/rtl/sync_signal.v b/example/Arty/fpga/rtl/sync_signal.v index b2a8ce3d..74b855fa 100644 --- a/example/Arty/fpga/rtl/sync_signal.v +++ b/example/Arty/fpga/rtl/sync_signal.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes an asyncronous signal to a given clock by using a pipeline of @@ -56,3 +58,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/C10LP/fpga/rtl/debounce_switch.v b/example/C10LP/fpga/rtl/debounce_switch.v index bb631cc3..8e93a50c 100644 --- a/example/C10LP/fpga/rtl/debounce_switch.v +++ b/example/C10LP/fpga/rtl/debounce_switch.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes switch and button inputs with a slow sampled shift register @@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin end endmodule + +`resetall diff --git a/example/C10LP/fpga/rtl/fpga.v b/example/C10LP/fpga/rtl/fpga.v index 166d94c8..a9d42929 100644 --- a/example/C10LP/fpga/rtl/fpga.v +++ b/example/C10LP/fpga/rtl/fpga.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA top-level module @@ -230,3 +232,5 @@ core_inst ( ); endmodule + +`resetall diff --git a/example/C10LP/fpga/rtl/fpga_core.v b/example/C10LP/fpga/rtl/fpga_core.v index 1a71c239..83fc9401 100644 --- a/example/C10LP/fpga/rtl/fpga_core.v +++ b/example/C10LP/fpga/rtl/fpga_core.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA core logic @@ -565,3 +567,5 @@ udp_payload_fifo ( ); endmodule + +`resetall diff --git a/example/C10LP/fpga/rtl/sync_signal.v b/example/C10LP/fpga/rtl/sync_signal.v index b2a8ce3d..74b855fa 100644 --- a/example/C10LP/fpga/rtl/sync_signal.v +++ b/example/C10LP/fpga/rtl/sync_signal.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes an asyncronous signal to a given clock by using a pipeline of @@ -56,3 +58,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/DE2-115/fpga/rtl/debounce_switch.v b/example/DE2-115/fpga/rtl/debounce_switch.v index bb631cc3..8e93a50c 100644 --- a/example/DE2-115/fpga/rtl/debounce_switch.v +++ b/example/DE2-115/fpga/rtl/debounce_switch.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes switch and button inputs with a slow sampled shift register @@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin end endmodule + +`resetall diff --git a/example/DE2-115/fpga/rtl/fpga.v b/example/DE2-115/fpga/rtl/fpga.v index e72e3497..ca43d8b1 100644 --- a/example/DE2-115/fpga/rtl/fpga.v +++ b/example/DE2-115/fpga/rtl/fpga.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA top-level module @@ -263,3 +265,5 @@ core_inst ( ); endmodule + +`resetall diff --git a/example/DE2-115/fpga/rtl/fpga_core.v b/example/DE2-115/fpga/rtl/fpga_core.v index f570d998..8ce5a6f4 100644 --- a/example/DE2-115/fpga/rtl/fpga_core.v +++ b/example/DE2-115/fpga/rtl/fpga_core.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA core logic @@ -673,3 +675,5 @@ udp_payload_fifo ( ); endmodule + +`resetall diff --git a/example/DE2-115/fpga/rtl/hex_display.v b/example/DE2-115/fpga/rtl/hex_display.v index dddf57de..355667b2 100644 --- a/example/DE2-115/fpga/rtl/hex_display.v +++ b/example/DE2-115/fpga/rtl/hex_display.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * 7 segment display hexadecimal encoding @@ -68,3 +70,5 @@ end assign out = INVERT ? ~enc : enc; endmodule + +`resetall diff --git a/example/DE2-115/fpga/rtl/sync_signal.v b/example/DE2-115/fpga/rtl/sync_signal.v index b2a8ce3d..74b855fa 100644 --- a/example/DE2-115/fpga/rtl/sync_signal.v +++ b/example/DE2-115/fpga/rtl/sync_signal.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes an asyncronous signal to a given clock by using a pipeline of @@ -56,3 +58,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/DE5-Net/fpga/rtl/debounce_switch.v b/example/DE5-Net/fpga/rtl/debounce_switch.v index bb631cc3..8e93a50c 100644 --- a/example/DE5-Net/fpga/rtl/debounce_switch.v +++ b/example/DE5-Net/fpga/rtl/debounce_switch.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes switch and button inputs with a slow sampled shift register @@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin end endmodule + +`resetall diff --git a/example/DE5-Net/fpga/rtl/fpga.v b/example/DE5-Net/fpga/rtl/fpga.v index 031b5870..b451b28b 100644 --- a/example/DE5-Net/fpga/rtl/fpga.v +++ b/example/DE5-Net/fpga/rtl/fpga.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA top-level module @@ -468,3 +470,5 @@ core_inst ( ); endmodule + +`resetall diff --git a/example/DE5-Net/fpga/rtl/fpga_core.v b/example/DE5-Net/fpga/rtl/fpga_core.v index 1352793b..10e42515 100644 --- a/example/DE5-Net/fpga/rtl/fpga_core.v +++ b/example/DE5-Net/fpga/rtl/fpga_core.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA core logic @@ -612,3 +614,5 @@ udp_payload_fifo ( ); endmodule + +`resetall diff --git a/example/DE5-Net/fpga/rtl/i2c_master.v b/example/DE5-Net/fpga/rtl/i2c_master.v index 95d3a521..5161245b 100644 --- a/example/DE5-Net/fpga/rtl/i2c_master.v +++ b/example/DE5-Net/fpga/rtl/i2c_master.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * I2C master @@ -893,3 +895,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/DE5-Net/fpga/rtl/si570_i2c_init.v b/example/DE5-Net/fpga/rtl/si570_i2c_init.v index e4dc5625..618a805d 100644 --- a/example/DE5-Net/fpga/rtl/si570_i2c_init.v +++ b/example/DE5-Net/fpga/rtl/si570_i2c_init.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * si570_i2c_init @@ -453,3 +455,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/DE5-Net/fpga/rtl/sync_signal.v b/example/DE5-Net/fpga/rtl/sync_signal.v index b2a8ce3d..74b855fa 100644 --- a/example/DE5-Net/fpga/rtl/sync_signal.v +++ b/example/DE5-Net/fpga/rtl/sync_signal.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes an asyncronous signal to a given clock by using a pipeline of @@ -56,3 +58,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/ExaNIC_X10/fpga/rtl/eth_xcvr_phy_wrapper.v b/example/ExaNIC_X10/fpga/rtl/eth_xcvr_phy_wrapper.v index b80a7399..2a34f8e0 100644 --- a/example/ExaNIC_X10/fpga/rtl/eth_xcvr_phy_wrapper.v +++ b/example/ExaNIC_X10/fpga/rtl/eth_xcvr_phy_wrapper.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * Transceiver and PHY wrapper @@ -301,3 +303,5 @@ phy_inst ( ); endmodule + +`resetall diff --git a/example/ExaNIC_X10/fpga/rtl/fpga.v b/example/ExaNIC_X10/fpga/rtl/fpga.v index 3f4b4b9b..885fec03 100644 --- a/example/ExaNIC_X10/fpga/rtl/fpga.v +++ b/example/ExaNIC_X10/fpga/rtl/fpga.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA top-level module @@ -349,3 +351,5 @@ core_inst ( ); endmodule + +`resetall diff --git a/example/ExaNIC_X10/fpga/rtl/fpga_core.v b/example/ExaNIC_X10/fpga/rtl/fpga_core.v index e894c601..ba26330d 100644 --- a/example/ExaNIC_X10/fpga/rtl/fpga_core.v +++ b/example/ExaNIC_X10/fpga/rtl/fpga_core.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA core logic @@ -592,3 +594,5 @@ udp_payload_fifo ( ); endmodule + +`resetall diff --git a/example/ExaNIC_X10/fpga/rtl/sync_signal.v b/example/ExaNIC_X10/fpga/rtl/sync_signal.v index b2a8ce3d..74b855fa 100644 --- a/example/ExaNIC_X10/fpga/rtl/sync_signal.v +++ b/example/ExaNIC_X10/fpga/rtl/sync_signal.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes an asyncronous signal to a given clock by using a pipeline of @@ -56,3 +58,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/ExaNIC_X25/fpga_10g/rtl/eth_xcvr_phy_wrapper.v b/example/ExaNIC_X25/fpga_10g/rtl/eth_xcvr_phy_wrapper.v index 64a4293f..bbdbf9dd 100644 --- a/example/ExaNIC_X25/fpga_10g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/ExaNIC_X25/fpga_10g/rtl/eth_xcvr_phy_wrapper.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * Transceiver and PHY wrapper @@ -301,3 +303,5 @@ phy_inst ( ); endmodule + +`resetall diff --git a/example/ExaNIC_X25/fpga_10g/rtl/fpga.v b/example/ExaNIC_X25/fpga_10g/rtl/fpga.v index ddc33252..71de10a4 100644 --- a/example/ExaNIC_X25/fpga_10g/rtl/fpga.v +++ b/example/ExaNIC_X25/fpga_10g/rtl/fpga.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA top-level module @@ -349,3 +351,5 @@ core_inst ( ); endmodule + +`resetall diff --git a/example/ExaNIC_X25/fpga_10g/rtl/fpga_core.v b/example/ExaNIC_X25/fpga_10g/rtl/fpga_core.v index e894c601..ba26330d 100644 --- a/example/ExaNIC_X25/fpga_10g/rtl/fpga_core.v +++ b/example/ExaNIC_X25/fpga_10g/rtl/fpga_core.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA core logic @@ -592,3 +594,5 @@ udp_payload_fifo ( ); endmodule + +`resetall diff --git a/example/ExaNIC_X25/fpga_10g/rtl/sync_signal.v b/example/ExaNIC_X25/fpga_10g/rtl/sync_signal.v index b2a8ce3d..74b855fa 100644 --- a/example/ExaNIC_X25/fpga_10g/rtl/sync_signal.v +++ b/example/ExaNIC_X25/fpga_10g/rtl/sync_signal.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes an asyncronous signal to a given clock by using a pipeline of @@ -56,3 +58,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/HTG9200/fpga_10g/rtl/debounce_switch.v b/example/HTG9200/fpga_10g/rtl/debounce_switch.v index ab84126e..f63a5a2e 100644 --- a/example/HTG9200/fpga_10g/rtl/debounce_switch.v +++ b/example/HTG9200/fpga_10g/rtl/debounce_switch.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes switch and button inputs with a slow sampled shift register @@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin end endmodule + +`resetall diff --git a/example/HTG9200/fpga_10g/rtl/eth_xcvr_phy_wrapper.v b/example/HTG9200/fpga_10g/rtl/eth_xcvr_phy_wrapper.v index 9798e758..acac5e3f 100644 --- a/example/HTG9200/fpga_10g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/HTG9200/fpga_10g/rtl/eth_xcvr_phy_wrapper.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * Transceiver and PHY wrapper @@ -293,3 +295,5 @@ phy_inst ( ); endmodule + +`resetall diff --git a/example/HTG9200/fpga_10g/rtl/fpga.v b/example/HTG9200/fpga_10g/rtl/fpga.v index f27c901f..c7176a5e 100644 --- a/example/HTG9200/fpga_10g/rtl/fpga.v +++ b/example/HTG9200/fpga_10g/rtl/fpga.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA top-level module @@ -2845,3 +2847,5 @@ core_inst ( ); endmodule + +`resetall diff --git a/example/HTG9200/fpga_10g/rtl/fpga_core.v b/example/HTG9200/fpga_10g/rtl/fpga_core.v index f5e165a9..78479023 100644 --- a/example/HTG9200/fpga_10g/rtl/fpga_core.v +++ b/example/HTG9200/fpga_10g/rtl/fpga_core.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA core logic @@ -955,3 +957,5 @@ udp_payload_fifo ( ); endmodule + +`resetall diff --git a/example/HTG9200/fpga_10g/rtl/i2c_master.v b/example/HTG9200/fpga_10g/rtl/i2c_master.v index 9c69b48e..b933316a 100644 --- a/example/HTG9200/fpga_10g/rtl/i2c_master.v +++ b/example/HTG9200/fpga_10g/rtl/i2c_master.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * I2C master @@ -895,3 +897,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/HTG9200/fpga_10g/rtl/si5341_i2c_init.py b/example/HTG9200/fpga_10g/rtl/si5341_i2c_init.py index 2186cf93..f564d125 100755 --- a/example/HTG9200/fpga_10g/rtl/si5341_i2c_init.py +++ b/example/HTG9200/fpga_10g/rtl/si5341_i2c_init.py @@ -130,7 +130,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * {{name}} @@ -581,6 +583,8 @@ end endmodule +`resetall + """) print(f"Writing file '{output}'...") diff --git a/example/HTG9200/fpga_10g/rtl/si5341_i2c_init.v b/example/HTG9200/fpga_10g/rtl/si5341_i2c_init.v index d37327a6..f3dd9a34 100644 --- a/example/HTG9200/fpga_10g/rtl/si5341_i2c_init.v +++ b/example/HTG9200/fpga_10g/rtl/si5341_i2c_init.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * si5341_i2c_init @@ -1035,3 +1037,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/HTG9200/fpga_10g/rtl/sync_signal.v b/example/HTG9200/fpga_10g/rtl/sync_signal.v index 1b8a3232..64531930 100644 --- a/example/HTG9200/fpga_10g/rtl/sync_signal.v +++ b/example/HTG9200/fpga_10g/rtl/sync_signal.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes an asyncronous signal to a given clock by using a pipeline of @@ -56,3 +58,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/HXT100G/fpga/rtl/debounce_switch.v b/example/HXT100G/fpga/rtl/debounce_switch.v index 69f30d70..8a5545a2 100644 --- a/example/HXT100G/fpga/rtl/debounce_switch.v +++ b/example/HXT100G/fpga/rtl/debounce_switch.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes switch and button inputs with a slow sampled shift register @@ -87,3 +89,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/HXT100G/fpga/rtl/eth_gth_phy_quad.v b/example/HXT100G/fpga/rtl/eth_gth_phy_quad.v index 60ab0f13..42a06001 100644 --- a/example/HXT100G/fpga/rtl/eth_gth_phy_quad.v +++ b/example/HXT100G/fpga/rtl/eth_gth_phy_quad.v @@ -22,6 +22,12 @@ THE SOFTWARE. */ +// Language: Verilog 2001 + +`resetall +`timescale 1 ns / 1 ps +`default_nettype none + module eth_gth_phy_quad ( /* * Clock and reset @@ -567,3 +573,5 @@ mgmt_arb_inst ); endmodule + +`resetall diff --git a/example/HXT100G/fpga/rtl/fpga.v b/example/HXT100G/fpga/rtl/fpga.v index 3afb47cf..c735fdb6 100644 --- a/example/HXT100G/fpga/rtl/fpga.v +++ b/example/HXT100G/fpga/rtl/fpga.v @@ -22,6 +22,12 @@ THE SOFTWARE. */ +// Language: Verilog 2001 + +`resetall +`timescale 1 ns / 1 ps +`default_nettype none + module fpga ( /* * Clock: 50MHz @@ -1129,3 +1135,5 @@ core_inst ( ); endmodule + +`resetall diff --git a/example/HXT100G/fpga/rtl/fpga_core.v b/example/HXT100G/fpga/rtl/fpga_core.v index 09d2c171..d3423eeb 100644 --- a/example/HXT100G/fpga/rtl/fpga_core.v +++ b/example/HXT100G/fpga/rtl/fpga_core.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none module fpga_core ( @@ -756,3 +758,5 @@ udp_payload_fifo ( ); endmodule + +`resetall diff --git a/example/HXT100G/fpga/rtl/gth_i2c_init.v b/example/HXT100G/fpga/rtl/gth_i2c_init.v index a8eff170..c7be9fc7 100644 --- a/example/HXT100G/fpga/rtl/gth_i2c_init.v +++ b/example/HXT100G/fpga/rtl/gth_i2c_init.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * gth_i2c_init @@ -506,3 +508,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/HXT100G/fpga/rtl/i2c_master.v b/example/HXT100G/fpga/rtl/i2c_master.v index 95d3a521..5161245b 100644 --- a/example/HXT100G/fpga/rtl/i2c_master.v +++ b/example/HXT100G/fpga/rtl/i2c_master.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * I2C master @@ -893,3 +895,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/HXT100G/fpga/rtl/sync_signal.v b/example/HXT100G/fpga/rtl/sync_signal.v index b2a8ce3d..74b855fa 100644 --- a/example/HXT100G/fpga/rtl/sync_signal.v +++ b/example/HXT100G/fpga/rtl/sync_signal.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes an asyncronous signal to a given clock by using a pipeline of @@ -56,3 +58,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/HXT100G/fpga_cxpt16/rtl/debounce_switch.v b/example/HXT100G/fpga_cxpt16/rtl/debounce_switch.v index 69f30d70..8a5545a2 100644 --- a/example/HXT100G/fpga_cxpt16/rtl/debounce_switch.v +++ b/example/HXT100G/fpga_cxpt16/rtl/debounce_switch.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes switch and button inputs with a slow sampled shift register @@ -87,3 +89,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/HXT100G/fpga_cxpt16/rtl/eth_gth_phy_quad.v b/example/HXT100G/fpga_cxpt16/rtl/eth_gth_phy_quad.v index 60ab0f13..42a06001 100644 --- a/example/HXT100G/fpga_cxpt16/rtl/eth_gth_phy_quad.v +++ b/example/HXT100G/fpga_cxpt16/rtl/eth_gth_phy_quad.v @@ -22,6 +22,12 @@ THE SOFTWARE. */ +// Language: Verilog 2001 + +`resetall +`timescale 1 ns / 1 ps +`default_nettype none + module eth_gth_phy_quad ( /* * Clock and reset @@ -567,3 +573,5 @@ mgmt_arb_inst ); endmodule + +`resetall diff --git a/example/HXT100G/fpga_cxpt16/rtl/fpga.v b/example/HXT100G/fpga_cxpt16/rtl/fpga.v index 3afb47cf..c735fdb6 100644 --- a/example/HXT100G/fpga_cxpt16/rtl/fpga.v +++ b/example/HXT100G/fpga_cxpt16/rtl/fpga.v @@ -22,6 +22,12 @@ THE SOFTWARE. */ +// Language: Verilog 2001 + +`resetall +`timescale 1 ns / 1 ps +`default_nettype none + module fpga ( /* * Clock: 50MHz @@ -1129,3 +1135,5 @@ core_inst ( ); endmodule + +`resetall diff --git a/example/HXT100G/fpga_cxpt16/rtl/fpga_core.v b/example/HXT100G/fpga_cxpt16/rtl/fpga_core.v index 99cda302..b4a7cf74 100644 --- a/example/HXT100G/fpga_cxpt16/rtl/fpga_core.v +++ b/example/HXT100G/fpga_cxpt16/rtl/fpga_core.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none module fpga_core ( @@ -459,3 +461,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/HXT100G/fpga_cxpt16/rtl/gth_i2c_init.v b/example/HXT100G/fpga_cxpt16/rtl/gth_i2c_init.v index a8eff170..c7be9fc7 100644 --- a/example/HXT100G/fpga_cxpt16/rtl/gth_i2c_init.v +++ b/example/HXT100G/fpga_cxpt16/rtl/gth_i2c_init.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * gth_i2c_init @@ -506,3 +508,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/HXT100G/fpga_cxpt16/rtl/i2c_master.v b/example/HXT100G/fpga_cxpt16/rtl/i2c_master.v index 95d3a521..5161245b 100644 --- a/example/HXT100G/fpga_cxpt16/rtl/i2c_master.v +++ b/example/HXT100G/fpga_cxpt16/rtl/i2c_master.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * I2C master @@ -893,3 +895,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/HXT100G/fpga_cxpt16/rtl/sync_signal.v b/example/HXT100G/fpga_cxpt16/rtl/sync_signal.v index b2a8ce3d..74b855fa 100644 --- a/example/HXT100G/fpga_cxpt16/rtl/sync_signal.v +++ b/example/HXT100G/fpga_cxpt16/rtl/sync_signal.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes an asyncronous signal to a given clock by using a pipeline of @@ -56,3 +58,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/KC705/fpga_gmii/rtl/debounce_switch.v b/example/KC705/fpga_gmii/rtl/debounce_switch.v index bb631cc3..8e93a50c 100644 --- a/example/KC705/fpga_gmii/rtl/debounce_switch.v +++ b/example/KC705/fpga_gmii/rtl/debounce_switch.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes switch and button inputs with a slow sampled shift register @@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin end endmodule + +`resetall diff --git a/example/KC705/fpga_gmii/rtl/fpga.v b/example/KC705/fpga_gmii/rtl/fpga.v index 90402a7c..60ca7ee2 100644 --- a/example/KC705/fpga_gmii/rtl/fpga.v +++ b/example/KC705/fpga_gmii/rtl/fpga.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA top-level module @@ -253,3 +255,5 @@ core_inst ( ); endmodule + +`resetall diff --git a/example/KC705/fpga_gmii/rtl/fpga_core.v b/example/KC705/fpga_gmii/rtl/fpga_core.v index fbf0d7af..0e0b46ff 100644 --- a/example/KC705/fpga_gmii/rtl/fpga_core.v +++ b/example/KC705/fpga_gmii/rtl/fpga_core.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA core logic @@ -585,3 +587,5 @@ udp_payload_fifo ( ); endmodule + +`resetall diff --git a/example/KC705/fpga_gmii/rtl/sync_signal.v b/example/KC705/fpga_gmii/rtl/sync_signal.v index b2a8ce3d..74b855fa 100644 --- a/example/KC705/fpga_gmii/rtl/sync_signal.v +++ b/example/KC705/fpga_gmii/rtl/sync_signal.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes an asyncronous signal to a given clock by using a pipeline of @@ -56,3 +58,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/KC705/fpga_rgmii/rtl/debounce_switch.v b/example/KC705/fpga_rgmii/rtl/debounce_switch.v index bb631cc3..8e93a50c 100644 --- a/example/KC705/fpga_rgmii/rtl/debounce_switch.v +++ b/example/KC705/fpga_rgmii/rtl/debounce_switch.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes switch and button inputs with a slow sampled shift register @@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin end endmodule + +`resetall diff --git a/example/KC705/fpga_rgmii/rtl/fpga.v b/example/KC705/fpga_rgmii/rtl/fpga.v index ba0cad1e..92188383 100644 --- a/example/KC705/fpga_rgmii/rtl/fpga.v +++ b/example/KC705/fpga_rgmii/rtl/fpga.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA top-level module @@ -369,3 +371,5 @@ core_inst ( ); endmodule + +`resetall diff --git a/example/KC705/fpga_rgmii/rtl/fpga_core.v b/example/KC705/fpga_rgmii/rtl/fpga_core.v index 43075db8..1505d330 100644 --- a/example/KC705/fpga_rgmii/rtl/fpga_core.v +++ b/example/KC705/fpga_rgmii/rtl/fpga_core.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA core logic @@ -582,3 +584,5 @@ udp_payload_fifo ( ); endmodule + +`resetall diff --git a/example/KC705/fpga_rgmii/rtl/sync_signal.v b/example/KC705/fpga_rgmii/rtl/sync_signal.v index b2a8ce3d..74b855fa 100644 --- a/example/KC705/fpga_rgmii/rtl/sync_signal.v +++ b/example/KC705/fpga_rgmii/rtl/sync_signal.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes an asyncronous signal to a given clock by using a pipeline of @@ -56,3 +58,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/KC705/fpga_sgmii/rtl/debounce_switch.v b/example/KC705/fpga_sgmii/rtl/debounce_switch.v index bb631cc3..8e93a50c 100644 --- a/example/KC705/fpga_sgmii/rtl/debounce_switch.v +++ b/example/KC705/fpga_sgmii/rtl/debounce_switch.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes switch and button inputs with a slow sampled shift register @@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin end endmodule + +`resetall diff --git a/example/KC705/fpga_sgmii/rtl/fpga.v b/example/KC705/fpga_sgmii/rtl/fpga.v index 82073ea1..4846ab21 100644 --- a/example/KC705/fpga_sgmii/rtl/fpga.v +++ b/example/KC705/fpga_sgmii/rtl/fpga.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA top-level module @@ -363,3 +365,5 @@ core_inst ( ); endmodule + +`resetall diff --git a/example/KC705/fpga_sgmii/rtl/fpga_core.v b/example/KC705/fpga_sgmii/rtl/fpga_core.v index 5d863286..fe73ad5b 100644 --- a/example/KC705/fpga_sgmii/rtl/fpga_core.v +++ b/example/KC705/fpga_sgmii/rtl/fpga_core.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA core logic @@ -582,3 +584,5 @@ udp_payload_fifo ( ); endmodule + +`resetall diff --git a/example/KC705/fpga_sgmii/rtl/sync_signal.v b/example/KC705/fpga_sgmii/rtl/sync_signal.v index b2a8ce3d..74b855fa 100644 --- a/example/KC705/fpga_sgmii/rtl/sync_signal.v +++ b/example/KC705/fpga_sgmii/rtl/sync_signal.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes an asyncronous signal to a given clock by using a pipeline of @@ -56,3 +58,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/ML605/fpga_gmii/rtl/debounce_switch.v b/example/ML605/fpga_gmii/rtl/debounce_switch.v index bb631cc3..8e93a50c 100644 --- a/example/ML605/fpga_gmii/rtl/debounce_switch.v +++ b/example/ML605/fpga_gmii/rtl/debounce_switch.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes switch and button inputs with a slow sampled shift register @@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin end endmodule + +`resetall diff --git a/example/ML605/fpga_gmii/rtl/fpga.v b/example/ML605/fpga_gmii/rtl/fpga.v index 14f15c08..4312faef 100644 --- a/example/ML605/fpga_gmii/rtl/fpga.v +++ b/example/ML605/fpga_gmii/rtl/fpga.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA top-level module @@ -279,3 +281,5 @@ core_inst ( ); endmodule + +`resetall diff --git a/example/ML605/fpga_gmii/rtl/fpga_core.v b/example/ML605/fpga_gmii/rtl/fpga_core.v index 6a82bc63..1bae139a 100644 --- a/example/ML605/fpga_gmii/rtl/fpga_core.v +++ b/example/ML605/fpga_gmii/rtl/fpga_core.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA core logic @@ -594,3 +596,5 @@ udp_payload_fifo ( ); endmodule + +`resetall diff --git a/example/ML605/fpga_gmii/rtl/sync_signal.v b/example/ML605/fpga_gmii/rtl/sync_signal.v index b2a8ce3d..74b855fa 100644 --- a/example/ML605/fpga_gmii/rtl/sync_signal.v +++ b/example/ML605/fpga_gmii/rtl/sync_signal.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes an asyncronous signal to a given clock by using a pipeline of @@ -56,3 +58,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/ML605/fpga_rgmii/rtl/debounce_switch.v b/example/ML605/fpga_rgmii/rtl/debounce_switch.v index bb631cc3..8e93a50c 100644 --- a/example/ML605/fpga_rgmii/rtl/debounce_switch.v +++ b/example/ML605/fpga_rgmii/rtl/debounce_switch.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes switch and button inputs with a slow sampled shift register @@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin end endmodule + +`resetall diff --git a/example/ML605/fpga_rgmii/rtl/fpga.v b/example/ML605/fpga_rgmii/rtl/fpga.v index 38640ccc..efd9c4c5 100644 --- a/example/ML605/fpga_rgmii/rtl/fpga.v +++ b/example/ML605/fpga_rgmii/rtl/fpga.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA top-level module @@ -282,3 +284,5 @@ core_inst ( ); endmodule + +`resetall diff --git a/example/ML605/fpga_rgmii/rtl/fpga_core.v b/example/ML605/fpga_rgmii/rtl/fpga_core.v index 9aa01032..1fcb6fa3 100644 --- a/example/ML605/fpga_rgmii/rtl/fpga_core.v +++ b/example/ML605/fpga_rgmii/rtl/fpga_core.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA core logic @@ -591,3 +593,5 @@ udp_payload_fifo ( ); endmodule + +`resetall diff --git a/example/ML605/fpga_rgmii/rtl/sync_signal.v b/example/ML605/fpga_rgmii/rtl/sync_signal.v index b2a8ce3d..74b855fa 100644 --- a/example/ML605/fpga_rgmii/rtl/sync_signal.v +++ b/example/ML605/fpga_rgmii/rtl/sync_signal.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes an asyncronous signal to a given clock by using a pipeline of @@ -56,3 +58,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/ML605/fpga_sgmii/rtl/debounce_switch.v b/example/ML605/fpga_sgmii/rtl/debounce_switch.v index bb631cc3..8e93a50c 100644 --- a/example/ML605/fpga_sgmii/rtl/debounce_switch.v +++ b/example/ML605/fpga_sgmii/rtl/debounce_switch.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes switch and button inputs with a slow sampled shift register @@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin end endmodule + +`resetall diff --git a/example/ML605/fpga_sgmii/rtl/fpga.v b/example/ML605/fpga_sgmii/rtl/fpga.v index bf3e6ecc..06f8a6df 100644 --- a/example/ML605/fpga_sgmii/rtl/fpga.v +++ b/example/ML605/fpga_sgmii/rtl/fpga.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA top-level module @@ -395,3 +397,5 @@ core_inst ( ); endmodule + +`resetall diff --git a/example/ML605/fpga_sgmii/rtl/fpga_core.v b/example/ML605/fpga_sgmii/rtl/fpga_core.v index 0f720144..565a4123 100644 --- a/example/ML605/fpga_sgmii/rtl/fpga_core.v +++ b/example/ML605/fpga_sgmii/rtl/fpga_core.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA core logic @@ -591,3 +593,5 @@ udp_payload_fifo ( ); endmodule + +`resetall diff --git a/example/ML605/fpga_sgmii/rtl/sync_signal.v b/example/ML605/fpga_sgmii/rtl/sync_signal.v index b2a8ce3d..74b855fa 100644 --- a/example/ML605/fpga_sgmii/rtl/sync_signal.v +++ b/example/ML605/fpga_sgmii/rtl/sync_signal.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes an asyncronous signal to a given clock by using a pipeline of @@ -56,3 +58,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/NetFPGA_SUME/fpga/rtl/debounce_switch.v b/example/NetFPGA_SUME/fpga/rtl/debounce_switch.v index bb631cc3..8e93a50c 100644 --- a/example/NetFPGA_SUME/fpga/rtl/debounce_switch.v +++ b/example/NetFPGA_SUME/fpga/rtl/debounce_switch.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes switch and button inputs with a slow sampled shift register @@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin end endmodule + +`resetall diff --git a/example/NetFPGA_SUME/fpga/rtl/fpga.v b/example/NetFPGA_SUME/fpga/rtl/fpga.v index fb7134c0..d7827bca 100644 --- a/example/NetFPGA_SUME/fpga/rtl/fpga.v +++ b/example/NetFPGA_SUME/fpga/rtl/fpga.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA top-level module @@ -712,3 +714,5 @@ core_inst ( ); endmodule + +`resetall diff --git a/example/NetFPGA_SUME/fpga/rtl/fpga_core.v b/example/NetFPGA_SUME/fpga/rtl/fpga_core.v index c72ccecd..f80f8a34 100644 --- a/example/NetFPGA_SUME/fpga/rtl/fpga_core.v +++ b/example/NetFPGA_SUME/fpga/rtl/fpga_core.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA core logic @@ -625,3 +627,5 @@ udp_payload_fifo ( ); endmodule + +`resetall diff --git a/example/NetFPGA_SUME/fpga/rtl/i2c_master.v b/example/NetFPGA_SUME/fpga/rtl/i2c_master.v index 95d3a521..5161245b 100644 --- a/example/NetFPGA_SUME/fpga/rtl/i2c_master.v +++ b/example/NetFPGA_SUME/fpga/rtl/i2c_master.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * I2C master @@ -893,3 +895,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/NetFPGA_SUME/fpga/rtl/si5324_i2c_init.v b/example/NetFPGA_SUME/fpga/rtl/si5324_i2c_init.v index 3669903e..c809e523 100644 --- a/example/NetFPGA_SUME/fpga/rtl/si5324_i2c_init.v +++ b/example/NetFPGA_SUME/fpga/rtl/si5324_i2c_init.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * si5324_i2c_init @@ -492,3 +494,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/NexysVideo/fpga/rtl/debounce_switch.v b/example/NexysVideo/fpga/rtl/debounce_switch.v index bb631cc3..8e93a50c 100644 --- a/example/NexysVideo/fpga/rtl/debounce_switch.v +++ b/example/NexysVideo/fpga/rtl/debounce_switch.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes switch and button inputs with a slow sampled shift register @@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin end endmodule + +`resetall diff --git a/example/NexysVideo/fpga/rtl/fpga.v b/example/NexysVideo/fpga/rtl/fpga.v index b79dd493..87de5554 100644 --- a/example/NexysVideo/fpga/rtl/fpga.v +++ b/example/NexysVideo/fpga/rtl/fpga.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA top-level module @@ -371,3 +373,5 @@ core_inst ( ); endmodule + +`resetall diff --git a/example/NexysVideo/fpga/rtl/fpga_core.v b/example/NexysVideo/fpga/rtl/fpga_core.v index 14275247..5f94b530 100644 --- a/example/NexysVideo/fpga/rtl/fpga_core.v +++ b/example/NexysVideo/fpga/rtl/fpga_core.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA core logic @@ -580,3 +582,5 @@ udp_payload_fifo ( ); endmodule + +`resetall diff --git a/example/NexysVideo/fpga/rtl/sync_signal.v b/example/NexysVideo/fpga/rtl/sync_signal.v index b2a8ce3d..74b855fa 100644 --- a/example/NexysVideo/fpga/rtl/sync_signal.v +++ b/example/NexysVideo/fpga/rtl/sync_signal.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes an asyncronous signal to a given clock by using a pipeline of @@ -56,3 +58,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/S10DX_DK/fpga_10g/rtl/avst2axis.v b/example/S10DX_DK/fpga_10g/rtl/avst2axis.v index 8119081b..eb0b6d27 100644 --- a/example/S10DX_DK/fpga_10g/rtl/avst2axis.v +++ b/example/S10DX_DK/fpga_10g/rtl/avst2axis.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * Avalon-ST to AXI stream @@ -81,3 +83,5 @@ assign axis_tlast = avst_endofpacket; assign axis_tuser = avst_error; endmodule + +`resetall diff --git a/example/S10DX_DK/fpga_10g/rtl/axis2avst.v b/example/S10DX_DK/fpga_10g/rtl/axis2avst.v index 918e1449..dc8f1c2e 100644 --- a/example/S10DX_DK/fpga_10g/rtl/axis2avst.v +++ b/example/S10DX_DK/fpga_10g/rtl/axis2avst.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI stream to Avalon-ST @@ -107,3 +109,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/S10DX_DK/fpga_10g/rtl/debounce_switch.v b/example/S10DX_DK/fpga_10g/rtl/debounce_switch.v index 37f7d127..4104007f 100644 --- a/example/S10DX_DK/fpga_10g/rtl/debounce_switch.v +++ b/example/S10DX_DK/fpga_10g/rtl/debounce_switch.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes switch and button inputs with a slow sampled shift register @@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin end endmodule + +`resetall diff --git a/example/S10DX_DK/fpga_10g/rtl/eth_mac_quad_wrapper.v b/example/S10DX_DK/fpga_10g/rtl/eth_mac_quad_wrapper.v index f6f3e119..c67de5f1 100644 --- a/example/S10DX_DK/fpga_10g/rtl/eth_mac_quad_wrapper.v +++ b/example/S10DX_DK/fpga_10g/rtl/eth_mac_quad_wrapper.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * Quad Ethernet MAC wrapper @@ -364,3 +366,5 @@ end endgenerate endmodule + +`resetall diff --git a/example/S10DX_DK/fpga_10g/rtl/fpga.v b/example/S10DX_DK/fpga_10g/rtl/fpga.v index e1db4504..c5da588d 100644 --- a/example/S10DX_DK/fpga_10g/rtl/fpga.v +++ b/example/S10DX_DK/fpga_10g/rtl/fpga.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA top-level module @@ -535,3 +537,5 @@ core_inst ( ); endmodule + +`resetall diff --git a/example/S10DX_DK/fpga_10g/rtl/fpga_core.v b/example/S10DX_DK/fpga_10g/rtl/fpga_core.v index 459d456d..f73913ab 100644 --- a/example/S10DX_DK/fpga_10g/rtl/fpga_core.v +++ b/example/S10DX_DK/fpga_10g/rtl/fpga_core.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA core logic @@ -828,3 +830,5 @@ udp_payload_fifo ( ); endmodule + +`resetall diff --git a/example/S10DX_DK/fpga_10g/rtl/sync_signal.v b/example/S10DX_DK/fpga_10g/rtl/sync_signal.v index b2a8ce3d..74b855fa 100644 --- a/example/S10DX_DK/fpga_10g/rtl/sync_signal.v +++ b/example/S10DX_DK/fpga_10g/rtl/sync_signal.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes an asyncronous signal to a given clock by using a pipeline of @@ -56,3 +58,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/S10DX_DK/fpga_10g/rtl/xcvr_ctrl.v b/example/S10DX_DK/fpga_10g/rtl/xcvr_ctrl.v index 475b7aab..b1e52b02 100644 --- a/example/S10DX_DK/fpga_10g/rtl/xcvr_ctrl.v +++ b/example/S10DX_DK/fpga_10g/rtl/xcvr_ctrl.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * Transceiver control @@ -262,3 +264,5 @@ always @(posedge reconfig_clk) begin end endmodule + +`resetall diff --git a/example/S10MX_DK/fpga_10g/rtl/eth_xcvr_phy_quad_wrapper.v b/example/S10MX_DK/fpga_10g/rtl/eth_xcvr_phy_quad_wrapper.v index 94a2d22f..85ace075 100644 --- a/example/S10MX_DK/fpga_10g/rtl/eth_xcvr_phy_quad_wrapper.v +++ b/example/S10MX_DK/fpga_10g/rtl/eth_xcvr_phy_quad_wrapper.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * Transceiver and PHY quad wrapper @@ -267,3 +269,5 @@ eth_xcvr_phy_wrapper eth_xcvr_phy_4 ( ); endmodule + +`resetall diff --git a/example/S10MX_DK/fpga_10g/rtl/eth_xcvr_phy_wrapper.v b/example/S10MX_DK/fpga_10g/rtl/eth_xcvr_phy_wrapper.v index e683a68b..c79772fd 100644 --- a/example/S10MX_DK/fpga_10g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/S10MX_DK/fpga_10g/rtl/eth_xcvr_phy_wrapper.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * Transceiver and PHY wrapper @@ -161,3 +163,5 @@ phy_inst ( ); endmodule + +`resetall diff --git a/example/S10MX_DK/fpga_10g/rtl/fpga.v b/example/S10MX_DK/fpga_10g/rtl/fpga.v index 688c9df4..0f1718f1 100644 --- a/example/S10MX_DK/fpga_10g/rtl/fpga.v +++ b/example/S10MX_DK/fpga_10g/rtl/fpga.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA top-level module @@ -356,3 +358,5 @@ core_inst ( ); endmodule + +`resetall diff --git a/example/S10MX_DK/fpga_10g/rtl/fpga_core.v b/example/S10MX_DK/fpga_10g/rtl/fpga_core.v index 5e8fb3a6..59e53f9c 100644 --- a/example/S10MX_DK/fpga_10g/rtl/fpga_core.v +++ b/example/S10MX_DK/fpga_10g/rtl/fpga_core.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA core logic @@ -651,3 +653,5 @@ udp_payload_fifo ( ); endmodule + +`resetall diff --git a/example/S10MX_DK/fpga_10g/rtl/sync_signal.v b/example/S10MX_DK/fpga_10g/rtl/sync_signal.v index b2a8ce3d..74b855fa 100644 --- a/example/S10MX_DK/fpga_10g/rtl/sync_signal.v +++ b/example/S10MX_DK/fpga_10g/rtl/sync_signal.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes an asyncronous signal to a given clock by using a pipeline of @@ -56,3 +58,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/VCU108/fpga_10g/rtl/debounce_switch.v b/example/VCU108/fpga_10g/rtl/debounce_switch.v index bb631cc3..8e93a50c 100644 --- a/example/VCU108/fpga_10g/rtl/debounce_switch.v +++ b/example/VCU108/fpga_10g/rtl/debounce_switch.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes switch and button inputs with a slow sampled shift register @@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin end endmodule + +`resetall diff --git a/example/VCU108/fpga_10g/rtl/eth_xcvr_phy_wrapper.v b/example/VCU108/fpga_10g/rtl/eth_xcvr_phy_wrapper.v index 9798e758..acac5e3f 100644 --- a/example/VCU108/fpga_10g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/VCU108/fpga_10g/rtl/eth_xcvr_phy_wrapper.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * Transceiver and PHY wrapper @@ -293,3 +295,5 @@ phy_inst ( ); endmodule + +`resetall diff --git a/example/VCU108/fpga_10g/rtl/fpga.v b/example/VCU108/fpga_10g/rtl/fpga.v index e7ae7155..29d21342 100644 --- a/example/VCU108/fpga_10g/rtl/fpga.v +++ b/example/VCU108/fpga_10g/rtl/fpga.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA top-level module @@ -696,3 +698,5 @@ core_inst ( ); endmodule + +`resetall diff --git a/example/VCU108/fpga_10g/rtl/fpga_core.v b/example/VCU108/fpga_10g/rtl/fpga_core.v index b78a54c3..1dbb9540 100644 --- a/example/VCU108/fpga_10g/rtl/fpga_core.v +++ b/example/VCU108/fpga_10g/rtl/fpga_core.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA core logic @@ -869,3 +871,5 @@ udp_payload_fifo ( ); endmodule + +`resetall diff --git a/example/VCU108/fpga_10g/rtl/sync_signal.v b/example/VCU108/fpga_10g/rtl/sync_signal.v index b2a8ce3d..74b855fa 100644 --- a/example/VCU108/fpga_10g/rtl/sync_signal.v +++ b/example/VCU108/fpga_10g/rtl/sync_signal.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes an asyncronous signal to a given clock by using a pipeline of @@ -56,3 +58,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/VCU108/fpga_1g/rtl/debounce_switch.v b/example/VCU108/fpga_1g/rtl/debounce_switch.v index bb631cc3..8e93a50c 100644 --- a/example/VCU108/fpga_1g/rtl/debounce_switch.v +++ b/example/VCU108/fpga_1g/rtl/debounce_switch.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes switch and button inputs with a slow sampled shift register @@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin end endmodule + +`resetall diff --git a/example/VCU108/fpga_1g/rtl/fpga.v b/example/VCU108/fpga_1g/rtl/fpga.v index e5a1d920..72a79373 100644 --- a/example/VCU108/fpga_1g/rtl/fpga.v +++ b/example/VCU108/fpga_1g/rtl/fpga.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA top-level module @@ -359,3 +361,5 @@ core_inst ( ); endmodule + +`resetall diff --git a/example/VCU108/fpga_1g/rtl/fpga_core.v b/example/VCU108/fpga_1g/rtl/fpga_core.v index 253ba9e5..8db7f759 100644 --- a/example/VCU108/fpga_1g/rtl/fpga_core.v +++ b/example/VCU108/fpga_1g/rtl/fpga_core.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA core logic @@ -582,3 +584,5 @@ udp_payload_fifo ( ); endmodule + +`resetall diff --git a/example/VCU108/fpga_1g/rtl/sync_signal.v b/example/VCU108/fpga_1g/rtl/sync_signal.v index b2a8ce3d..74b855fa 100644 --- a/example/VCU108/fpga_1g/rtl/sync_signal.v +++ b/example/VCU108/fpga_1g/rtl/sync_signal.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes an asyncronous signal to a given clock by using a pipeline of @@ -56,3 +58,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/VCU118/fpga_10g/rtl/debounce_switch.v b/example/VCU118/fpga_10g/rtl/debounce_switch.v index bb631cc3..8e93a50c 100644 --- a/example/VCU118/fpga_10g/rtl/debounce_switch.v +++ b/example/VCU118/fpga_10g/rtl/debounce_switch.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes switch and button inputs with a slow sampled shift register @@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin end endmodule + +`resetall diff --git a/example/VCU118/fpga_10g/rtl/eth_xcvr_phy_wrapper.v b/example/VCU118/fpga_10g/rtl/eth_xcvr_phy_wrapper.v index 9798e758..acac5e3f 100644 --- a/example/VCU118/fpga_10g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/VCU118/fpga_10g/rtl/eth_xcvr_phy_wrapper.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * Transceiver and PHY wrapper @@ -293,3 +295,5 @@ phy_inst ( ); endmodule + +`resetall diff --git a/example/VCU118/fpga_10g/rtl/fpga.v b/example/VCU118/fpga_10g/rtl/fpga.v index 1492ac35..b207cd1b 100644 --- a/example/VCU118/fpga_10g/rtl/fpga.v +++ b/example/VCU118/fpga_10g/rtl/fpga.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA top-level module @@ -1208,3 +1210,5 @@ core_inst ( ); endmodule + +`resetall diff --git a/example/VCU118/fpga_10g/rtl/fpga_core.v b/example/VCU118/fpga_10g/rtl/fpga_core.v index 79fcd6a8..b88642a3 100644 --- a/example/VCU118/fpga_10g/rtl/fpga_core.v +++ b/example/VCU118/fpga_10g/rtl/fpga_core.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA core logic @@ -910,3 +912,5 @@ udp_payload_fifo ( ); endmodule + +`resetall diff --git a/example/VCU118/fpga_10g/rtl/mdio_master.v b/example/VCU118/fpga_10g/rtl/mdio_master.v index 1dc56a8c..d3098a88 100644 --- a/example/VCU118/fpga_10g/rtl/mdio_master.v +++ b/example/VCU118/fpga_10g/rtl/mdio_master.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * MDIO master @@ -223,3 +225,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/VCU118/fpga_10g/rtl/sync_signal.v b/example/VCU118/fpga_10g/rtl/sync_signal.v index b2a8ce3d..74b855fa 100644 --- a/example/VCU118/fpga_10g/rtl/sync_signal.v +++ b/example/VCU118/fpga_10g/rtl/sync_signal.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes an asyncronous signal to a given clock by using a pipeline of @@ -56,3 +58,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/VCU118/fpga_1g/rtl/debounce_switch.v b/example/VCU118/fpga_1g/rtl/debounce_switch.v index bb631cc3..8e93a50c 100644 --- a/example/VCU118/fpga_1g/rtl/debounce_switch.v +++ b/example/VCU118/fpga_1g/rtl/debounce_switch.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes switch and button inputs with a slow sampled shift register @@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin end endmodule + +`resetall diff --git a/example/VCU118/fpga_1g/rtl/fpga.v b/example/VCU118/fpga_1g/rtl/fpga.v index 3039d6df..fd1b922a 100644 --- a/example/VCU118/fpga_1g/rtl/fpga.v +++ b/example/VCU118/fpga_1g/rtl/fpga.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA top-level module @@ -568,3 +570,5 @@ core_inst ( ); endmodule + +`resetall diff --git a/example/VCU118/fpga_1g/rtl/fpga_core.v b/example/VCU118/fpga_1g/rtl/fpga_core.v index 253ba9e5..8db7f759 100644 --- a/example/VCU118/fpga_1g/rtl/fpga_core.v +++ b/example/VCU118/fpga_1g/rtl/fpga_core.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA core logic @@ -582,3 +584,5 @@ udp_payload_fifo ( ); endmodule + +`resetall diff --git a/example/VCU118/fpga_1g/rtl/mdio_master.v b/example/VCU118/fpga_1g/rtl/mdio_master.v index 1dc56a8c..d3098a88 100644 --- a/example/VCU118/fpga_1g/rtl/mdio_master.v +++ b/example/VCU118/fpga_1g/rtl/mdio_master.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * MDIO master @@ -223,3 +225,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/VCU118/fpga_1g/rtl/sync_signal.v b/example/VCU118/fpga_1g/rtl/sync_signal.v index b2a8ce3d..74b855fa 100644 --- a/example/VCU118/fpga_1g/rtl/sync_signal.v +++ b/example/VCU118/fpga_1g/rtl/sync_signal.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes an asyncronous signal to a given clock by using a pipeline of @@ -56,3 +58,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/VCU118/fpga_25g/rtl/debounce_switch.v b/example/VCU118/fpga_25g/rtl/debounce_switch.v index bb631cc3..8e93a50c 100644 --- a/example/VCU118/fpga_25g/rtl/debounce_switch.v +++ b/example/VCU118/fpga_25g/rtl/debounce_switch.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes switch and button inputs with a slow sampled shift register @@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin end endmodule + +`resetall diff --git a/example/VCU118/fpga_25g/rtl/eth_xcvr_phy_wrapper.v b/example/VCU118/fpga_25g/rtl/eth_xcvr_phy_wrapper.v index 9798e758..acac5e3f 100644 --- a/example/VCU118/fpga_25g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/VCU118/fpga_25g/rtl/eth_xcvr_phy_wrapper.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * Transceiver and PHY wrapper @@ -293,3 +295,5 @@ phy_inst ( ); endmodule + +`resetall diff --git a/example/VCU118/fpga_25g/rtl/fpga.v b/example/VCU118/fpga_25g/rtl/fpga.v index f0812940..1eb21344 100644 --- a/example/VCU118/fpga_25g/rtl/fpga.v +++ b/example/VCU118/fpga_25g/rtl/fpga.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA top-level module @@ -1232,3 +1234,5 @@ core_inst ( ); endmodule + +`resetall diff --git a/example/VCU118/fpga_25g/rtl/fpga_core.v b/example/VCU118/fpga_25g/rtl/fpga_core.v index e6868c4a..404c1b76 100644 --- a/example/VCU118/fpga_25g/rtl/fpga_core.v +++ b/example/VCU118/fpga_25g/rtl/fpga_core.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA core logic @@ -910,3 +912,5 @@ udp_payload_fifo ( ); endmodule + +`resetall diff --git a/example/VCU118/fpga_25g/rtl/mdio_master.v b/example/VCU118/fpga_25g/rtl/mdio_master.v index 1dc56a8c..d3098a88 100644 --- a/example/VCU118/fpga_25g/rtl/mdio_master.v +++ b/example/VCU118/fpga_25g/rtl/mdio_master.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * MDIO master @@ -223,3 +225,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/VCU118/fpga_25g/rtl/sync_signal.v b/example/VCU118/fpga_25g/rtl/sync_signal.v index b2a8ce3d..74b855fa 100644 --- a/example/VCU118/fpga_25g/rtl/sync_signal.v +++ b/example/VCU118/fpga_25g/rtl/sync_signal.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes an asyncronous signal to a given clock by using a pipeline of @@ -56,3 +58,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/VCU1525/fpga_10g/rtl/debounce_switch.v b/example/VCU1525/fpga_10g/rtl/debounce_switch.v index bb631cc3..8e93a50c 100644 --- a/example/VCU1525/fpga_10g/rtl/debounce_switch.v +++ b/example/VCU1525/fpga_10g/rtl/debounce_switch.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes switch and button inputs with a slow sampled shift register @@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin end endmodule + +`resetall diff --git a/example/VCU1525/fpga_10g/rtl/eth_xcvr_phy_wrapper.v b/example/VCU1525/fpga_10g/rtl/eth_xcvr_phy_wrapper.v index 9798e758..acac5e3f 100644 --- a/example/VCU1525/fpga_10g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/VCU1525/fpga_10g/rtl/eth_xcvr_phy_wrapper.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * Transceiver and PHY wrapper @@ -293,3 +295,5 @@ phy_inst ( ); endmodule + +`resetall diff --git a/example/VCU1525/fpga_10g/rtl/fpga.v b/example/VCU1525/fpga_10g/rtl/fpga.v index 52578cff..6917bc67 100644 --- a/example/VCU1525/fpga_10g/rtl/fpga.v +++ b/example/VCU1525/fpga_10g/rtl/fpga.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA top-level module @@ -898,3 +900,5 @@ core_inst ( ); endmodule + +`resetall diff --git a/example/VCU1525/fpga_10g/rtl/fpga_core.v b/example/VCU1525/fpga_10g/rtl/fpga_core.v index a840ea01..c8c2c444 100644 --- a/example/VCU1525/fpga_10g/rtl/fpga_core.v +++ b/example/VCU1525/fpga_10g/rtl/fpga_core.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA core logic @@ -662,3 +664,5 @@ udp_payload_fifo ( ); endmodule + +`resetall diff --git a/example/VCU1525/fpga_10g/rtl/sync_signal.v b/example/VCU1525/fpga_10g/rtl/sync_signal.v index b2a8ce3d..74b855fa 100644 --- a/example/VCU1525/fpga_10g/rtl/sync_signal.v +++ b/example/VCU1525/fpga_10g/rtl/sync_signal.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes an asyncronous signal to a given clock by using a pipeline of @@ -56,3 +58,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/ZCU102/fpga/rtl/debounce_switch.v b/example/ZCU102/fpga/rtl/debounce_switch.v index bb631cc3..8e93a50c 100644 --- a/example/ZCU102/fpga/rtl/debounce_switch.v +++ b/example/ZCU102/fpga/rtl/debounce_switch.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes switch and button inputs with a slow sampled shift register @@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin end endmodule + +`resetall diff --git a/example/ZCU102/fpga/rtl/eth_xcvr_phy_wrapper.v b/example/ZCU102/fpga/rtl/eth_xcvr_phy_wrapper.v index afbaddd0..bbbfd08d 100644 --- a/example/ZCU102/fpga/rtl/eth_xcvr_phy_wrapper.v +++ b/example/ZCU102/fpga/rtl/eth_xcvr_phy_wrapper.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * Transceiver and PHY wrapper @@ -293,3 +295,5 @@ phy_inst ( ); endmodule + +`resetall diff --git a/example/ZCU102/fpga/rtl/fpga.v b/example/ZCU102/fpga/rtl/fpga.v index 6cd71740..2df13cbf 100644 --- a/example/ZCU102/fpga/rtl/fpga.v +++ b/example/ZCU102/fpga/rtl/fpga.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA top-level module @@ -545,3 +547,5 @@ core_inst ( ); endmodule + +`resetall diff --git a/example/ZCU102/fpga/rtl/fpga_core.v b/example/ZCU102/fpga/rtl/fpga_core.v index b181d52f..85a8c0bc 100644 --- a/example/ZCU102/fpga/rtl/fpga_core.v +++ b/example/ZCU102/fpga/rtl/fpga_core.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA core logic @@ -624,3 +626,5 @@ udp_payload_fifo ( ); endmodule + +`resetall diff --git a/example/ZCU102/fpga/rtl/sync_signal.v b/example/ZCU102/fpga/rtl/sync_signal.v index b2a8ce3d..74b855fa 100644 --- a/example/ZCU102/fpga/rtl/sync_signal.v +++ b/example/ZCU102/fpga/rtl/sync_signal.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes an asyncronous signal to a given clock by using a pipeline of @@ -56,3 +58,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/ZCU106/fpga/rtl/debounce_switch.v b/example/ZCU106/fpga/rtl/debounce_switch.v index bb631cc3..8e93a50c 100644 --- a/example/ZCU106/fpga/rtl/debounce_switch.v +++ b/example/ZCU106/fpga/rtl/debounce_switch.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes switch and button inputs with a slow sampled shift register @@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin end endmodule + +`resetall diff --git a/example/ZCU106/fpga/rtl/eth_xcvr_phy_wrapper.v b/example/ZCU106/fpga/rtl/eth_xcvr_phy_wrapper.v index afbaddd0..bbbfd08d 100644 --- a/example/ZCU106/fpga/rtl/eth_xcvr_phy_wrapper.v +++ b/example/ZCU106/fpga/rtl/eth_xcvr_phy_wrapper.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * Transceiver and PHY wrapper @@ -293,3 +295,5 @@ phy_inst ( ); endmodule + +`resetall diff --git a/example/ZCU106/fpga/rtl/fpga.v b/example/ZCU106/fpga/rtl/fpga.v index cf0e40c9..64c45346 100644 --- a/example/ZCU106/fpga/rtl/fpga.v +++ b/example/ZCU106/fpga/rtl/fpga.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA top-level module @@ -398,3 +400,5 @@ core_inst ( ); endmodule + +`resetall diff --git a/example/ZCU106/fpga/rtl/fpga_core.v b/example/ZCU106/fpga/rtl/fpga_core.v index a53ab0d1..2c6f0193 100644 --- a/example/ZCU106/fpga/rtl/fpga_core.v +++ b/example/ZCU106/fpga/rtl/fpga_core.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA core logic @@ -604,3 +606,5 @@ udp_payload_fifo ( ); endmodule + +`resetall diff --git a/example/ZCU106/fpga/rtl/sync_signal.v b/example/ZCU106/fpga/rtl/sync_signal.v index b2a8ce3d..74b855fa 100644 --- a/example/ZCU106/fpga/rtl/sync_signal.v +++ b/example/ZCU106/fpga/rtl/sync_signal.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes an asyncronous signal to a given clock by using a pipeline of @@ -56,3 +58,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/fb2CG/fpga_10g/rtl/eth_xcvr_phy_wrapper.v b/example/fb2CG/fpga_10g/rtl/eth_xcvr_phy_wrapper.v index 9798e758..acac5e3f 100644 --- a/example/fb2CG/fpga_10g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/fb2CG/fpga_10g/rtl/eth_xcvr_phy_wrapper.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * Transceiver and PHY wrapper @@ -293,3 +295,5 @@ phy_inst ( ); endmodule + +`resetall diff --git a/example/fb2CG/fpga_10g/rtl/fpga.v b/example/fb2CG/fpga_10g/rtl/fpga.v index 7c601f2f..90b85fbd 100644 --- a/example/fb2CG/fpga_10g/rtl/fpga.v +++ b/example/fb2CG/fpga_10g/rtl/fpga.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA top-level module @@ -862,3 +864,5 @@ core_inst ( ); endmodule + +`resetall diff --git a/example/fb2CG/fpga_10g/rtl/fpga_core.v b/example/fb2CG/fpga_10g/rtl/fpga_core.v index d38ee928..18f1e32f 100644 --- a/example/fb2CG/fpga_10g/rtl/fpga_core.v +++ b/example/fb2CG/fpga_10g/rtl/fpga_core.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * FPGA core logic @@ -660,3 +662,5 @@ udp_payload_fifo ( ); endmodule + +`resetall diff --git a/example/fb2CG/fpga_10g/rtl/led_sreg_driver.v b/example/fb2CG/fpga_10g/rtl/led_sreg_driver.v index fa81ea1a..be970e9b 100644 --- a/example/fb2CG/fpga_10g/rtl/led_sreg_driver.v +++ b/example/fb2CG/fpga_10g/rtl/led_sreg_driver.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * LED shift register driver @@ -133,3 +135,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/example/fb2CG/fpga_10g/rtl/sync_signal.v b/example/fb2CG/fpga_10g/rtl/sync_signal.v index b2a8ce3d..74b855fa 100644 --- a/example/fb2CG/fpga_10g/rtl/sync_signal.v +++ b/example/fb2CG/fpga_10g/rtl/sync_signal.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog-2001 +`resetall `timescale 1 ns / 1 ps +`default_nettype none /* * Synchronizes an asyncronous signal to a given clock by using a pipeline of @@ -56,3 +58,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/arp.v b/rtl/arp.v index ea57d5e8..1bf8786a 100644 --- a/rtl/arp.v +++ b/rtl/arp.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * ARP block for IPv4, ethernet frame interface @@ -446,3 +448,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/arp_cache.v b/rtl/arp_cache.v index e0c4c066..53fe6cd7 100644 --- a/rtl/arp_cache.v +++ b/rtl/arp_cache.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * ARP cache @@ -241,3 +243,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/arp_eth_rx.v b/rtl/arp_eth_rx.v index eb7ea983..1bac60c6 100644 --- a/rtl/arp_eth_rx.v +++ b/rtl/arp_eth_rx.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * ARP ethernet frame receiver (Ethernet frame in, ARP frame out) @@ -321,3 +323,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/arp_eth_tx.v b/rtl/arp_eth_tx.v index 7ea1b3dc..9ef78f5b 100644 --- a/rtl/arp_eth_tx.v +++ b/rtl/arp_eth_tx.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * ARP ethernet frame transmitter (ARP frame in, Ethernet frame out) @@ -358,3 +360,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/axis_baser_rx_64.v b/rtl/axis_baser_rx_64.v index 8e1f535a..57da8bd5 100644 --- a/rtl/axis_baser_rx_64.v +++ b/rtl/axis_baser_rx_64.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4-Stream 10GBASE-R frame receiver (10GBASE-R in, AXI out) @@ -603,3 +605,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/axis_baser_tx_64.v b/rtl/axis_baser_tx_64.v index 00a1e447..915bdb8a 100644 --- a/rtl/axis_baser_tx_64.v +++ b/rtl/axis_baser_tx_64.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4-Stream 10GBASE-R frame transmitter (AXI in, 10GBASE-R out) @@ -911,3 +913,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/axis_eth_fcs.v b/rtl/axis_eth_fcs.v index e09cd208..984351cb 100644 --- a/rtl/axis_eth_fcs.v +++ b/rtl/axis_eth_fcs.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4-Stream Ethernet FCS Generator @@ -135,3 +137,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/axis_eth_fcs_check.v b/rtl/axis_eth_fcs_check.v index 00625238..5c731ade 100644 --- a/rtl/axis_eth_fcs_check.v +++ b/rtl/axis_eth_fcs_check.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4-Stream Ethernet FCS checker @@ -339,3 +341,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/axis_eth_fcs_check_64.v b/rtl/axis_eth_fcs_check_64.v index 1fd17206..4f157c08 100644 --- a/rtl/axis_eth_fcs_check_64.v +++ b/rtl/axis_eth_fcs_check_64.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4-Stream Ethernet FCS checker (64 bit datapath) @@ -476,3 +478,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/axis_eth_fcs_insert.v b/rtl/axis_eth_fcs_insert.v index a73baab0..306cc868 100644 --- a/rtl/axis_eth_fcs_insert.v +++ b/rtl/axis_eth_fcs_insert.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4-Stream Ethernet FCS inserter @@ -366,3 +368,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/axis_eth_fcs_insert_64.v b/rtl/axis_eth_fcs_insert_64.v index 887cc431..c20a16ee 100644 --- a/rtl/axis_eth_fcs_insert_64.v +++ b/rtl/axis_eth_fcs_insert_64.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4-Stream Ethernet FCS inserter (64 bit datapath) @@ -715,3 +717,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/axis_gmii_rx.v b/rtl/axis_gmii_rx.v index 60416a15..cdddc5b0 100644 --- a/rtl/axis_gmii_rx.v +++ b/rtl/axis_gmii_rx.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4-Stream GMII frame receiver (GMII in, AXI out) @@ -339,3 +341,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/axis_gmii_tx.v b/rtl/axis_gmii_tx.v index e29f380c..1b097272 100644 --- a/rtl/axis_gmii_tx.v +++ b/rtl/axis_gmii_tx.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4-Stream GMII frame transmitter (AXI in, GMII out) @@ -443,3 +445,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/axis_xgmii_rx_32.v b/rtl/axis_xgmii_rx_32.v index bb5c7474..097ced18 100644 --- a/rtl/axis_xgmii_rx_32.v +++ b/rtl/axis_xgmii_rx_32.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4-Stream XGMII frame receiver (XGMII in, AXI out) @@ -430,3 +432,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/axis_xgmii_rx_64.v b/rtl/axis_xgmii_rx_64.v index 213d00fc..9f083006 100644 --- a/rtl/axis_xgmii_rx_64.v +++ b/rtl/axis_xgmii_rx_64.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4-Stream XGMII frame receiver (XGMII in, AXI out) @@ -542,3 +544,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/axis_xgmii_tx_32.v b/rtl/axis_xgmii_tx_32.v index 8016eee2..f9ee0c54 100644 --- a/rtl/axis_xgmii_tx_32.v +++ b/rtl/axis_xgmii_tx_32.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4-Stream XGMII frame transmitter (AXI in, XGMII out) @@ -622,3 +624,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/axis_xgmii_tx_64.v b/rtl/axis_xgmii_tx_64.v index 1471ffa0..7f0cc3fc 100644 --- a/rtl/axis_xgmii_tx_64.v +++ b/rtl/axis_xgmii_tx_64.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4-Stream XGMII frame transmitter (AXI in, XGMII out) @@ -779,3 +781,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/eth_arb_mux.v b/rtl/eth_arb_mux.v index c4b0d0fa..1956f444 100644 --- a/rtl/eth_arb_mux.v +++ b/rtl/eth_arb_mux.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * Ethernet arbitrated multiplexer @@ -309,3 +311,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/eth_axis_rx.v b/rtl/eth_axis_rx.v index e0a20e43..f75fee23 100644 --- a/rtl/eth_axis_rx.v +++ b/rtl/eth_axis_rx.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4-Stream ethernet frame receiver (AXI in, Ethernet frame out) @@ -395,3 +397,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/eth_axis_tx.v b/rtl/eth_axis_tx.v index 5d582c42..55ddca1e 100644 --- a/rtl/eth_axis_tx.v +++ b/rtl/eth_axis_tx.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * AXI4-Stream ethernet frame transmitter (Ethernet frame in, AXI out) @@ -398,3 +400,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/eth_demux.v b/rtl/eth_demux.v index 0433b9ef..17ecfbec 100644 --- a/rtl/eth_demux.v +++ b/rtl/eth_demux.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * Ethernet demultiplexer @@ -303,3 +305,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/eth_mac_10g.v b/rtl/eth_mac_10g.v index 800731c8..46a57433 100644 --- a/rtl/eth_mac_10g.v +++ b/rtl/eth_mac_10g.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * 10G Ethernet MAC @@ -250,3 +252,5 @@ end endgenerate endmodule + +`resetall diff --git a/rtl/eth_mac_10g_fifo.v b/rtl/eth_mac_10g_fifo.v index c61b4762..d4460925 100644 --- a/rtl/eth_mac_10g_fifo.v +++ b/rtl/eth_mac_10g_fifo.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * 10G Ethernet MAC with TX and RX FIFOs @@ -486,3 +488,5 @@ rx_fifo ( ); endmodule + +`resetall diff --git a/rtl/eth_mac_1g.v b/rtl/eth_mac_1g.v index 4f1075c1..d94f7747 100644 --- a/rtl/eth_mac_1g.v +++ b/rtl/eth_mac_1g.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * 1G Ethernet MAC @@ -165,3 +167,5 @@ axis_gmii_tx_inst ( ); endmodule + +`resetall diff --git a/rtl/eth_mac_1g_fifo.v b/rtl/eth_mac_1g_fifo.v index 029c66c6..c16a86cb 100644 --- a/rtl/eth_mac_1g_fifo.v +++ b/rtl/eth_mac_1g_fifo.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * 1G Ethernet MAC with TX and RX FIFOs @@ -319,3 +321,5 @@ rx_fifo ( ); endmodule + +`resetall diff --git a/rtl/eth_mac_1g_gmii.v b/rtl/eth_mac_1g_gmii.v index dc0927c8..6b119692 100644 --- a/rtl/eth_mac_1g_gmii.v +++ b/rtl/eth_mac_1g_gmii.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * 1G Ethernet MAC with GMII interface @@ -246,3 +248,5 @@ eth_mac_1g_inst ( ); endmodule + +`resetall diff --git a/rtl/eth_mac_1g_gmii_fifo.v b/rtl/eth_mac_1g_gmii_fifo.v index b003cd72..d8577478 100644 --- a/rtl/eth_mac_1g_gmii_fifo.v +++ b/rtl/eth_mac_1g_gmii_fifo.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * 1G Ethernet MAC with GMII interface and TX and RX FIFOs @@ -350,3 +352,5 @@ rx_fifo ( ); endmodule + +`resetall diff --git a/rtl/eth_mac_1g_rgmii.v b/rtl/eth_mac_1g_rgmii.v index 04e1370c..a6aaaded 100644 --- a/rtl/eth_mac_1g_rgmii.v +++ b/rtl/eth_mac_1g_rgmii.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * 1G Ethernet MAC with RGMII interface @@ -246,3 +248,5 @@ eth_mac_1g_inst ( ); endmodule + +`resetall diff --git a/rtl/eth_mac_1g_rgmii_fifo.v b/rtl/eth_mac_1g_rgmii_fifo.v index 2a80a467..6855a994 100644 --- a/rtl/eth_mac_1g_rgmii_fifo.v +++ b/rtl/eth_mac_1g_rgmii_fifo.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * 1G Ethernet MAC with RGMII interface and TX and RX FIFOs @@ -348,3 +350,5 @@ rx_fifo ( ); endmodule + +`resetall diff --git a/rtl/eth_mac_mii.v b/rtl/eth_mac_mii.v index 75c1f86c..8c1a4723 100644 --- a/rtl/eth_mac_mii.v +++ b/rtl/eth_mac_mii.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * 10M/100M Ethernet MAC with MII interface @@ -164,3 +166,5 @@ eth_mac_1g_inst ( ); endmodule + +`resetall diff --git a/rtl/eth_mac_mii_fifo.v b/rtl/eth_mac_mii_fifo.v index 0ac4ae83..1d70c7de 100644 --- a/rtl/eth_mac_mii_fifo.v +++ b/rtl/eth_mac_mii_fifo.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * 10M/100M Ethernet MAC with MII interface and TX and RX FIFOs @@ -327,3 +329,5 @@ rx_fifo ( ); endmodule + +`resetall diff --git a/rtl/eth_mac_phy_10g.v b/rtl/eth_mac_phy_10g.v index 3200b5c9..a92316ca 100644 --- a/rtl/eth_mac_phy_10g.v +++ b/rtl/eth_mac_phy_10g.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * 10G Ethernet MAC/PHY combination @@ -200,3 +202,5 @@ eth_mac_phy_10g_tx_inst ( ); endmodule + +`resetall diff --git a/rtl/eth_mac_phy_10g_fifo.v b/rtl/eth_mac_phy_10g_fifo.v index 012eaaf5..f8721240 100644 --- a/rtl/eth_mac_phy_10g_fifo.v +++ b/rtl/eth_mac_phy_10g_fifo.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * 10G Ethernet MAC/PHY combination with TX and RX FIFOs @@ -521,3 +523,5 @@ rx_fifo ( ); endmodule + +`resetall diff --git a/rtl/eth_mac_phy_10g_rx.v b/rtl/eth_mac_phy_10g_rx.v index ebc2986b..6074fe43 100644 --- a/rtl/eth_mac_phy_10g_rx.v +++ b/rtl/eth_mac_phy_10g_rx.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * 10G Ethernet MAC/PHY combination @@ -163,3 +165,5 @@ axis_baser_rx_inst ( ); endmodule + +`resetall diff --git a/rtl/eth_mac_phy_10g_tx.v b/rtl/eth_mac_phy_10g_tx.v index 29b7e244..4e6f5571 100644 --- a/rtl/eth_mac_phy_10g_tx.v +++ b/rtl/eth_mac_phy_10g_tx.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * 10G Ethernet MAC/PHY combination @@ -165,3 +167,5 @@ eth_phy_10g_tx_if_inst ( ); endmodule + +`resetall diff --git a/rtl/eth_mux.v b/rtl/eth_mux.v index 4fe32659..05bcd408 100644 --- a/rtl/eth_mux.v +++ b/rtl/eth_mux.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * Ethernet multiplexer @@ -297,3 +299,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/eth_phy_10g.v b/rtl/eth_phy_10g.v index 2f9458c1..e7b18a94 100644 --- a/rtl/eth_phy_10g.v +++ b/rtl/eth_phy_10g.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * 10G Ethernet PHY @@ -134,3 +136,5 @@ eth_phy_10g_tx_inst ( ); endmodule + +`resetall diff --git a/rtl/eth_phy_10g_rx.v b/rtl/eth_phy_10g_rx.v index bba424ad..f4b6d389 100644 --- a/rtl/eth_phy_10g_rx.v +++ b/rtl/eth_phy_10g_rx.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * 10G Ethernet PHY RX @@ -141,3 +143,5 @@ xgmii_baser_dec_inst ( ); endmodule + +`resetall diff --git a/rtl/eth_phy_10g_rx_ber_mon.v b/rtl/eth_phy_10g_rx_ber_mon.v index 04f39391..f2ba8d45 100644 --- a/rtl/eth_phy_10g_rx_ber_mon.v +++ b/rtl/eth_phy_10g_rx_ber_mon.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * 10G Ethernet PHY BER monitor @@ -118,3 +120,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/eth_phy_10g_rx_frame_sync.v b/rtl/eth_phy_10g_rx_frame_sync.v index 43be5e2f..5b851c02 100644 --- a/rtl/eth_phy_10g_rx_frame_sync.v +++ b/rtl/eth_phy_10g_rx_frame_sync.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * 10G Ethernet PHY frame sync @@ -140,3 +142,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/eth_phy_10g_rx_if.v b/rtl/eth_phy_10g_rx_if.v index 127044cb..3c810878 100644 --- a/rtl/eth_phy_10g_rx_if.v +++ b/rtl/eth_phy_10g_rx_if.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * 10G Ethernet PHY RX IF @@ -262,3 +264,5 @@ eth_phy_10g_rx_watchdog_inst ( ); endmodule + +`resetall diff --git a/rtl/eth_phy_10g_rx_watchdog.v b/rtl/eth_phy_10g_rx_watchdog.v index b4fd67b1..3f202f71 100644 --- a/rtl/eth_phy_10g_rx_watchdog.v +++ b/rtl/eth_phy_10g_rx_watchdog.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * 10G Ethernet PHY serdes watchdog @@ -138,3 +140,5 @@ always @(posedge clk or posedge rst) begin end endmodule + +`resetall diff --git a/rtl/eth_phy_10g_tx.v b/rtl/eth_phy_10g_tx.v index 95040f15..692ce4e7 100644 --- a/rtl/eth_phy_10g_tx.v +++ b/rtl/eth_phy_10g_tx.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * 10G Ethernet PHY TX @@ -121,3 +123,5 @@ eth_phy_10g_tx_if_inst ( ); endmodule + +`resetall diff --git a/rtl/eth_phy_10g_tx_if.v b/rtl/eth_phy_10g_tx_if.v index 70ea70b7..d61474e7 100644 --- a/rtl/eth_phy_10g_tx_if.v +++ b/rtl/eth_phy_10g_tx_if.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * 10G Ethernet PHY TX IF @@ -177,3 +179,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/gmii_phy_if.v b/rtl/gmii_phy_if.v index be6ea4ec..dac5b954 100644 --- a/rtl/gmii_phy_if.v +++ b/rtl/gmii_phy_if.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * GMII PHY interface @@ -146,3 +148,5 @@ always @(posedge mac_gmii_rx_clk or posedge rst) begin end endmodule + +`resetall diff --git a/rtl/iddr.v b/rtl/iddr.v index 473a06d3..d11f5160 100644 --- a/rtl/iddr.v +++ b/rtl/iddr.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * Generic IDDR module @@ -149,3 +151,5 @@ end endgenerate endmodule + +`resetall diff --git a/rtl/ip.v b/rtl/ip.v index 6c884ce3..6a35e355 100644 --- a/rtl/ip.v +++ b/rtl/ip.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * IPv4 block, ethernet frame interface @@ -339,3 +341,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/ip_64.v b/rtl/ip_64.v index be1464f4..d4cb8fff 100644 --- a/rtl/ip_64.v +++ b/rtl/ip_64.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * IPv4 block, ethernet frame interface (64 bit datapath) @@ -347,3 +349,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/ip_arb_mux.v b/rtl/ip_arb_mux.v index 68cfbf3a..eb55776e 100644 --- a/rtl/ip_arb_mux.v +++ b/rtl/ip_arb_mux.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * IP arbitrated multiplexer @@ -400,3 +402,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/ip_complete.v b/rtl/ip_complete.v index a878b71a..e25a5fd4 100644 --- a/rtl/ip_complete.v +++ b/rtl/ip_complete.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * IPv4 and ARP block, ethernet frame interface @@ -438,3 +440,5 @@ arp_inst ( ); endmodule + +`resetall diff --git a/rtl/ip_complete_64.v b/rtl/ip_complete_64.v index 6e0d4df8..95cec13c 100644 --- a/rtl/ip_complete_64.v +++ b/rtl/ip_complete_64.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * IPv4 and ARP block, ethernet frame interface (64 bit datapath) @@ -457,3 +459,5 @@ arp_inst ( ); endmodule + +`resetall diff --git a/rtl/ip_demux.v b/rtl/ip_demux.v index b86e60bd..08f5cbac 100644 --- a/rtl/ip_demux.v +++ b/rtl/ip_demux.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * IP demultiplexer @@ -394,3 +396,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/ip_eth_rx.v b/rtl/ip_eth_rx.v index 5d057914..5dd99676 100644 --- a/rtl/ip_eth_rx.v +++ b/rtl/ip_eth_rx.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * IP ethernet frame receiver (Ethernet frame in, IP frame out) @@ -575,3 +577,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/ip_eth_rx_64.v b/rtl/ip_eth_rx_64.v index 47554645..8f0e3342 100644 --- a/rtl/ip_eth_rx_64.v +++ b/rtl/ip_eth_rx_64.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * IP ethernet frame receiver (Ethernet frame in, IP frame out, 64 bit datapath) @@ -684,3 +686,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/ip_eth_tx.v b/rtl/ip_eth_tx.v index 14619f88..4b52dd49 100644 --- a/rtl/ip_eth_tx.v +++ b/rtl/ip_eth_tx.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * IP ethernet frame transmitter (IP frame in, Ethernet frame out) @@ -495,3 +497,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/ip_eth_tx_64.v b/rtl/ip_eth_tx_64.v index 471cf239..f8caa3b4 100644 --- a/rtl/ip_eth_tx_64.v +++ b/rtl/ip_eth_tx_64.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * IP ethernet frame transmitter (IP frame in, Ethernet frame out, 64 bit datapath) @@ -646,3 +648,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/ip_mux.v b/rtl/ip_mux.v index f05edf6b..86018a35 100644 --- a/rtl/ip_mux.v +++ b/rtl/ip_mux.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * IP multiplexer @@ -388,3 +390,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/lfsr.v b/rtl/lfsr.v index 1548daef..02472447 100644 --- a/rtl/lfsr.v +++ b/rtl/lfsr.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * Parametrizable combinatorial parallel LFSR/CRC @@ -440,3 +442,5 @@ end endgenerate endmodule + +`resetall diff --git a/rtl/mii_phy_if.v b/rtl/mii_phy_if.v index 0e8cb8ce..baec829b 100644 --- a/rtl/mii_phy_if.v +++ b/rtl/mii_phy_if.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * MII PHY interface @@ -135,3 +137,5 @@ always @(posedge mac_mii_rx_clk or posedge rst) begin end endmodule + +`resetall diff --git a/rtl/oddr.v b/rtl/oddr.v index db2d1442..2d9e8a58 100644 --- a/rtl/oddr.v +++ b/rtl/oddr.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * Generic ODDR module @@ -140,3 +142,5 @@ end endgenerate endmodule + +`resetall diff --git a/rtl/ptp_clock.v b/rtl/ptp_clock.v index b8c1d6bd..0e89277a 100644 --- a/rtl/ptp_clock.v +++ b/rtl/ptp_clock.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * PTP clock module @@ -244,3 +246,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/ptp_clock_cdc.v b/rtl/ptp_clock_cdc.v index 76b30730..00fbd70c 100644 --- a/rtl/ptp_clock_cdc.v +++ b/rtl/ptp_clock_cdc.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * PTP clock CDC (clock domain crossing) module @@ -683,3 +685,5 @@ always @(posedge output_clk) begin end endmodule + +`resetall diff --git a/rtl/ptp_perout.v b/rtl/ptp_perout.v index a5a34157..3430616d 100644 --- a/rtl/ptp_perout.v +++ b/rtl/ptp_perout.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * PTP period out module @@ -308,3 +310,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/ptp_tag_insert.v b/rtl/ptp_tag_insert.v index e693d154..f83c2138 100644 --- a/rtl/ptp_tag_insert.v +++ b/rtl/ptp_tag_insert.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * PTP tag insert module @@ -105,3 +107,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/ptp_ts_extract.v b/rtl/ptp_ts_extract.v index 8a97d4b3..3946bbbb 100644 --- a/rtl/ptp_ts_extract.v +++ b/rtl/ptp_ts_extract.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * PTP timestamp extract module @@ -69,3 +71,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/rgmii_phy_if.v b/rtl/rgmii_phy_if.v index 623f15ec..ca82572c 100644 --- a/rtl/rgmii_phy_if.v +++ b/rtl/rgmii_phy_if.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * RGMII PHY interface @@ -259,3 +261,5 @@ always @(posedge mac_gmii_rx_clk or posedge rst) begin end endmodule + +`resetall diff --git a/rtl/ssio_ddr_in.v b/rtl/ssio_ddr_in.v index 8fc9e58d..1dd18409 100644 --- a/rtl/ssio_ddr_in.v +++ b/rtl/ssio_ddr_in.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * Generic source synchronous DDR input @@ -145,3 +147,5 @@ data_iddr_inst ( ); endmodule + +`resetall diff --git a/rtl/ssio_ddr_in_diff.v b/rtl/ssio_ddr_in_diff.v index 3f9052c9..b4d97b86 100644 --- a/rtl/ssio_ddr_in_diff.v +++ b/rtl/ssio_ddr_in_diff.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * Generic source synchronous DDR input @@ -116,3 +118,5 @@ ssio_ddr_in_inst( ); endmodule + +`resetall diff --git a/rtl/ssio_ddr_out.v b/rtl/ssio_ddr_out.v index c77aa691..e6aab759 100644 --- a/rtl/ssio_ddr_out.v +++ b/rtl/ssio_ddr_out.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * Generic source synchronous DDR output @@ -80,3 +82,5 @@ data_oddr_inst ( ); endmodule + +`resetall diff --git a/rtl/ssio_ddr_out_diff.v b/rtl/ssio_ddr_out_diff.v index ba1beadc..4e4430bf 100644 --- a/rtl/ssio_ddr_out_diff.v +++ b/rtl/ssio_ddr_out_diff.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * Generic source synchronous DDR output @@ -117,3 +119,5 @@ end endgenerate endmodule + +`resetall diff --git a/rtl/ssio_sdr_in.v b/rtl/ssio_sdr_in.v index 09797f4c..56baa03c 100644 --- a/rtl/ssio_sdr_in.v +++ b/rtl/ssio_sdr_in.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * Generic source synchronous SDR input @@ -161,3 +163,5 @@ always @(posedge clk_io) begin end endmodule + +`resetall diff --git a/rtl/ssio_sdr_in_diff.v b/rtl/ssio_sdr_in_diff.v index 62501438..7a0d7c1e 100644 --- a/rtl/ssio_sdr_in_diff.v +++ b/rtl/ssio_sdr_in_diff.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * Generic source synchronous SDR input @@ -111,3 +113,5 @@ ssio_ddr_in_inst( ); endmodule + +`resetall diff --git a/rtl/ssio_sdr_out.v b/rtl/ssio_sdr_out.v index 702f9060..5aafbd0a 100644 --- a/rtl/ssio_sdr_out.v +++ b/rtl/ssio_sdr_out.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * Generic source synchronous SDR output @@ -71,3 +73,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/ssio_sdr_out_diff.v b/rtl/ssio_sdr_out_diff.v index 5fe26076..d343f72c 100644 --- a/rtl/ssio_sdr_out_diff.v +++ b/rtl/ssio_sdr_out_diff.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * Generic source synchronous SDR output @@ -110,3 +112,5 @@ end endgenerate endmodule + +`resetall diff --git a/rtl/udp.v b/rtl/udp.v index bca73aa4..892d6bc4 100644 --- a/rtl/udp.v +++ b/rtl/udp.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * UDP block, IP interface @@ -411,3 +413,5 @@ udp_ip_tx_inst ( ); endmodule + +`resetall diff --git a/rtl/udp_64.v b/rtl/udp_64.v index 25393dae..6dc2eee4 100644 --- a/rtl/udp_64.v +++ b/rtl/udp_64.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * UDP block, IP interface (64 bit datapath) @@ -422,3 +424,5 @@ udp_ip_tx_64_inst ( ); endmodule + +`resetall diff --git a/rtl/udp_arb_mux.v b/rtl/udp_arb_mux.v index a76218cb..e8abae12 100644 --- a/rtl/udp_arb_mux.v +++ b/rtl/udp_arb_mux.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * UDP arbitrated multiplexer @@ -428,3 +430,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/udp_checksum_gen.v b/rtl/udp_checksum_gen.v index e6e474ca..3038506b 100644 --- a/rtl/udp_checksum_gen.v +++ b/rtl/udp_checksum_gen.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * UDP checksum calculation module @@ -555,3 +557,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/udp_checksum_gen_64.v b/rtl/udp_checksum_gen_64.v index 9cc7b94c..ecc91e6d 100644 --- a/rtl/udp_checksum_gen_64.v +++ b/rtl/udp_checksum_gen_64.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * UDP checksum calculation module (64 bit datapath) @@ -591,3 +593,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/udp_complete.v b/rtl/udp_complete.v index 389c00fc..191e0bc7 100644 --- a/rtl/udp_complete.v +++ b/rtl/udp_complete.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * IPv4 and ARP block with UDP support, ethernet frame interface @@ -635,3 +637,5 @@ udp_inst ( ); endmodule + +`resetall diff --git a/rtl/udp_complete_64.v b/rtl/udp_complete_64.v index 3a1d4d5a..cb8e3a9b 100644 --- a/rtl/udp_complete_64.v +++ b/rtl/udp_complete_64.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * IPv4 and ARP block with UDP support, ethernet frame interface (64 bit datapath) @@ -655,3 +657,5 @@ udp_64_inst ( ); endmodule + +`resetall diff --git a/rtl/udp_demux.v b/rtl/udp_demux.v index f4dfb8cc..64c5cbff 100644 --- a/rtl/udp_demux.v +++ b/rtl/udp_demux.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * UDP demultiplexer @@ -422,3 +424,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/udp_ip_rx.v b/rtl/udp_ip_rx.v index 609ff09a..9b1a6846 100644 --- a/rtl/udp_ip_rx.v +++ b/rtl/udp_ip_rx.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * UDP ethernet frame receiver (IP frame in, UDP frame out) @@ -530,3 +532,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/udp_ip_rx_64.v b/rtl/udp_ip_rx_64.v index e3244ce2..65bbc418 100644 --- a/rtl/udp_ip_rx_64.v +++ b/rtl/udp_ip_rx_64.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * UDP ethernet frame receiver (IP frame in, UDP frame out, 64 bit datapath) @@ -558,3 +560,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/udp_ip_tx.v b/rtl/udp_ip_tx.v index 23ae0ee4..25398e7c 100644 --- a/rtl/udp_ip_tx.v +++ b/rtl/udp_ip_tx.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * UDP ethernet frame transmitter (UDP frame in, IP frame out) @@ -491,3 +493,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/udp_ip_tx_64.v b/rtl/udp_ip_tx_64.v index fe899b90..b027e3e7 100644 --- a/rtl/udp_ip_tx_64.v +++ b/rtl/udp_ip_tx_64.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * UDP ethernet frame transmitter (UDP frame in, IP frame out, 64-bit datapath) @@ -547,3 +549,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/udp_mux.v b/rtl/udp_mux.v index 7d33cedb..aab08024 100644 --- a/rtl/udp_mux.v +++ b/rtl/udp_mux.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * UDP multiplexer @@ -416,3 +418,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/xgmii_baser_dec_64.v b/rtl/xgmii_baser_dec_64.v index 39f5f0a4..a164f1c0 100644 --- a/rtl/xgmii_baser_dec_64.v +++ b/rtl/xgmii_baser_dec_64.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * XGMII 10GBASE-R decoder @@ -382,3 +384,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/xgmii_baser_enc_64.v b/rtl/xgmii_baser_enc_64.v index b16862f7..7436fd25 100644 --- a/rtl/xgmii_baser_enc_64.v +++ b/rtl/xgmii_baser_enc_64.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * XGMII 10GBASE-R encoder @@ -278,3 +280,5 @@ always @(posedge clk) begin end endmodule + +`resetall diff --git a/rtl/xgmii_deinterleave.v b/rtl/xgmii_deinterleave.v index 5410bc95..50ad70be 100644 --- a/rtl/xgmii_deinterleave.v +++ b/rtl/xgmii_deinterleave.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * XGMII control/data deinterleave @@ -55,3 +57,5 @@ assign output_xgmii_d[63:56] = input_xgmii_dc[70:63]; assign output_xgmii_c[7] = input_xgmii_dc[71]; endmodule + +`resetall diff --git a/rtl/xgmii_interleave.v b/rtl/xgmii_interleave.v index cf365e2f..ac25faca 100644 --- a/rtl/xgmii_interleave.v +++ b/rtl/xgmii_interleave.v @@ -24,7 +24,9 @@ THE SOFTWARE. // Language: Verilog 2001 +`resetall `timescale 1ns / 1ps +`default_nettype none /* * XGMII control/data interleave @@ -55,3 +57,5 @@ assign output_xgmii_dc[70:63] = input_xgmii_d[63:56]; assign output_xgmii_dc[71] = input_xgmii_c[7]; endmodule + +`resetall