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Properly reset all registers

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This commit is contained in:
Alex Forencich 2015-07-09 11:11:32 -07:00
parent 87fe1a561f
commit 6bd7309b9d
2 changed files with 4 additions and 0 deletions
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2
rtl/axis_async_fifo.v
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@ -125,6 +125,7 @@ end
always @(posedge input_clk or posedge input_rst_sync2) begin
if (input_rst_sync2) begin
wr_ptr <= 0;
wr_ptr_gray <= 0;
end else if (write) begin
mem[wr_ptr[ADDR_WIDTH-1:0]] <= data_in;
wr_ptr_next = wr_ptr + 1;
@ -148,6 +149,7 @@ end
always @(posedge output_clk or posedge output_rst_sync2) begin
if (output_rst_sync2) begin
rd_ptr <= 0;
rd_ptr_gray <= 0;
end else if (read) begin
data_out_reg <= mem[rd_ptr[ADDR_WIDTH-1:0]];
rd_ptr_next = rd_ptr + 1;

2
rtl/axis_async_fifo_64.v
View File

@ -128,6 +128,7 @@ end
always @(posedge input_clk or posedge input_rst_sync2) begin
if (input_rst_sync2) begin
wr_ptr <= 0;
wr_ptr_gray <= 0;
end else if (write) begin
mem[wr_ptr[ADDR_WIDTH-1:0]] <= data_in;
wr_ptr_next = wr_ptr + 1;
@ -151,6 +152,7 @@ end
always @(posedge output_clk or posedge output_rst_sync2) begin
if (output_rst_sync2) begin
rd_ptr <= 0;
rd_ptr_gray <= 0;
end else if (read) begin
data_out_reg <= mem[rd_ptr[ADDR_WIDTH-1:0]];
rd_ptr_next = rd_ptr + 1;