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https://github.com/alexforencich/verilog-ethernet.git
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merged changes in axis
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commit
70912e8255
@ -125,7 +125,7 @@ always @(posedge output_clk or posedge async_rst) begin
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output_rst_sync3_reg <= 1'b1;
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end else begin
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output_rst_sync1_reg <= 1'b0;
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output_rst_sync2_reg <= output_rst_sync1_reg;
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output_rst_sync2_reg <= input_rst_sync1_reg | output_rst_sync1_reg;
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output_rst_sync3_reg <= output_rst_sync2_reg;
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end
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end
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@ -128,7 +128,7 @@ always @(posedge output_clk or posedge async_rst) begin
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output_rst_sync3_reg <= 1'b1;
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end else begin
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output_rst_sync1_reg <= 1'b0;
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output_rst_sync2_reg <= output_rst_sync1_reg;
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output_rst_sync2_reg <= input_rst_sync1_reg | output_rst_sync1_reg;
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output_rst_sync3_reg <= output_rst_sync2_reg;
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end
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end
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@ -165,7 +165,7 @@ always @(posedge output_clk or posedge async_rst) begin
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output_rst_sync3_reg <= 1'b1;
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end else begin
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output_rst_sync1_reg <= 1'b0;
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output_rst_sync2_reg <= output_rst_sync1_reg;
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output_rst_sync2_reg <= input_rst_sync1_reg | output_rst_sync1_reg;
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output_rst_sync3_reg <= output_rst_sync2_reg;
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end
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end
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@ -168,7 +168,7 @@ always @(posedge output_clk or posedge async_rst) begin
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output_rst_sync3_reg <= 1'b1;
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end else begin
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output_rst_sync1_reg <= 1'b0;
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output_rst_sync2_reg <= output_rst_sync1_reg;
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output_rst_sync2_reg <= input_rst_sync1_reg | output_rst_sync1_reg;
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output_rst_sync3_reg <= output_rst_sync2_reg;
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end
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end
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