From 733044b0df9320999b2e74db110164998819ed24 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Tue, 30 Oct 2018 11:59:09 -0700 Subject: [PATCH] Work around MyHDL sync race condition --- tb/test_eth_axis_rx_64.py | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tb/test_eth_axis_rx_64.py b/tb/test_eth_axis_rx_64.py index 32439a89..0ae6ebff 100755 --- a/tb/test_eth_axis_rx_64.py +++ b/tb/test_eth_axis_rx_64.py @@ -206,6 +206,7 @@ def bench(): yield wait() + yield clk.posedge yield sink.wait() rx_frame = sink.recv() @@ -241,11 +242,13 @@ def bench(): yield wait() + yield clk.posedge yield sink.wait() rx_frame = sink.recv() assert rx_frame == test_frame1 + yield clk.posedge yield sink.wait() rx_frame = sink.recv() @@ -283,12 +286,14 @@ def bench(): yield wait() + yield clk.posedge yield sink.wait() rx_frame = sink.recv() assert rx_frame == test_frame1 assert rx_frame.payload.user[-1] + yield clk.posedge yield sink.wait() rx_frame = sink.recv() @@ -329,6 +334,7 @@ def bench(): yield wait() + yield clk.posedge yield sink.wait() rx_frame = sink.recv()