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Work around MyHDL sync race condition

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This commit is contained in:
Alex Forencich 2018-10-30 11:59:09 -07:00
parent 20017c04b9
commit 733044b0df
1 changed files with 6 additions and 0 deletions
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6
tb/test_eth_axis_rx_64.py
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@ -206,6 +206,7 @@ def bench():
yield wait()
yield clk.posedge
yield sink.wait()
rx_frame = sink.recv()
@ -241,11 +242,13 @@ def bench():
yield wait()
yield clk.posedge
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame1
yield clk.posedge
yield sink.wait()
rx_frame = sink.recv()
@ -283,12 +286,14 @@ def bench():
yield wait()
yield clk.posedge
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame1
assert rx_frame.payload.user[-1]
yield clk.posedge
yield sink.wait()
rx_frame = sink.recv()
@ -329,6 +334,7 @@ def bench():
yield wait()
yield clk.posedge
yield sink.wait()
rx_frame = sink.recv()