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https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-28 07:03:08 +08:00
Fail outgoing frames on tvalid deassert
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parent
475f897a31
commit
73e0a1cff4
@ -71,7 +71,8 @@ localparam [2:0]
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STATE_PAD = 3'd2,
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STATE_FCS_1 = 3'd3,
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STATE_FCS_2 = 3'd4,
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STATE_IFG = 3'd5;
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STATE_IFG = 3'd5,
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STATE_WAIT_END = 3'd6;
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reg [2:0] state_reg = STATE_IDLE, state_next;
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@ -394,11 +395,12 @@ always @* begin
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state_next = STATE_PAYLOAD;
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end
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end else begin
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// tvalid deassert, fail frame
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xgmii_txd_next = 64'h070707fdfefefefe;
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xgmii_txc_next = 8'b11111111;
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frame_ptr_next = 0;
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ifg_count_next = 8;
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state_next = STATE_IFG;
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state_next = STATE_WAIT_END;
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end
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end
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STATE_PAD: begin
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@ -501,6 +503,46 @@ always @* begin
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end
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end
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end
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STATE_WAIT_END: begin
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// wait for end of frame
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if (ifg_count_reg > 8) begin
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ifg_count_next = ifg_count_reg - 8;
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end else begin
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ifg_count_next = 0;
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end
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reset_crc = 1;
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if (input_axis_tvalid) begin
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if (input_axis_tlast) begin
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if (ENABLE_DIC) begin
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if (ifg_count_next > 7) begin
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state_next = STATE_IFG;
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end else begin
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if (ifg_count_next >= 4) begin
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deficit_idle_count_next = ifg_count_next - 4;
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end else begin
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deficit_idle_count_next = ifg_count_next;
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ifg_count_next = 0;
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end
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input_axis_tready_next = 1;
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state_next = STATE_IDLE;
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end
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end else begin
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if (ifg_count_next > 4) begin
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state_next = STATE_IFG;
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end else begin
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input_axis_tready_next = 1;
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state_next = STATE_IDLE;
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end
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end
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end else begin
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state_next = STATE_WAIT_END;
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end
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end else begin
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state_next = STATE_WAIT_END;
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end
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end
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endcase
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end
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@ -66,7 +66,8 @@ localparam [2:0]
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STATE_PAYLOAD = 3'd2,
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STATE_PAD = 3'd3,
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STATE_FCS = 3'd4,
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STATE_IFG = 3'd5;
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STATE_IFG = 3'd5,
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STATE_WAIT_END = 3'd6;
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reg [2:0] state_reg = STATE_IDLE, state_next;
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@ -173,9 +174,10 @@ always @* begin
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state_next = STATE_PAYLOAD;
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end
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end else begin
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// tvalid deassert, fail frame
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gmii_tx_er_next = 1;
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frame_ptr_next = 0;
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state_next = STATE_IFG;
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state_next = STATE_WAIT_END;
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end
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end
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STATE_PAD: begin
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@ -223,6 +225,25 @@ always @* begin
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state_next = STATE_IDLE;
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end
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end
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STATE_WAIT_END: begin
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// wait for end of frame
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frame_ptr_next = frame_ptr_reg + 1;
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reset_crc = 1;
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if (input_axis_tvalid) begin
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if (input_axis_tlast) begin
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if (frame_ptr_reg < ifg_delay-1) begin
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state_next = STATE_IFG;
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end else begin
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state_next = STATE_IDLE;
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end
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end else begin
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state_next = STATE_WAIT_END;
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end
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end else begin
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state_next = STATE_WAIT_END;
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end
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end
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endcase
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end
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