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Reorganize timing constraints

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This commit is contained in:
Alex Forencich 2021-05-18 16:15:41 -07:00
parent f236e7dff1
commit 7751aba8da
38 changed files with 86 additions and 86 deletions
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6
example/ADM_PCIE_9V3/fpga_10g/fpga/Makefile
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@ -49,9 +49,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl
# IP
IP_TCL_FILES += ip/gtwizard_ultrascale_0.tcl

6
example/ADM_PCIE_9V3/fpga_25g/fpga/Makefile
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@ -49,9 +49,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl
# IP
IP_TCL_FILES += ip/gtwizard_ultrascale_0.tcl

6
example/AU200/fpga_10g/fpga/Makefile
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@ -50,9 +50,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl
# IP
IP_TCL_FILES = ip/gtwizard_ultrascale_0.tcl

6
example/AU250/fpga_10g/fpga/Makefile
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@ -50,9 +50,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl
# IP
IP_TCL_FILES = ip/gtwizard_ultrascale_0.tcl

6
example/AU280/fpga_10g/fpga/Makefile
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@ -49,9 +49,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl
# IP
IP_TCL_FILES = ip/gtwizard_ultrascale_0.tcl

6
example/AU50/fpga_10g/fpga/Makefile
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@ -49,9 +49,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl
# IP
IP_TCL_FILES = ip/gtwizard_ultrascale_0.tcl

8
example/Arty/fpga/fpga/Makefile
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@ -43,10 +43,10 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += lib/eth/syn/mii_phy_if.tcl
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/mii_phy_if.tcl
XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl
include ../common/vivado.mk

10
example/C10LP/fpga/fpga.sdc
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@ -41,11 +41,11 @@ derive_pll_clocks
derive_clock_uncertainty
source ../lib/eth/syn/eth_mac_1g_rgmii.sdc
source ../lib/eth/syn/rgmii_phy_if.sdc
source ../lib/eth/syn/rgmii_io.sdc
source ../lib/eth/lib/axis/syn/sync_reset.sdc
source ../lib/eth/lib/axis/syn/axis_async_fifo.sdc
source ../lib/eth/syn/quartus/eth_mac_1g_rgmii.sdc
source ../lib/eth/syn/quartus/rgmii_phy_if.sdc
source ../lib/eth/syn/quartus/rgmii_io.sdc
source ../lib/eth/lib/axis/syn/quartus/sync_reset.sdc
source ../lib/eth/lib/axis/syn/quartus/axis_async_fifo.sdc
# clocking infrastructure
constrain_sync_reset_inst "sync_reset_inst"

10
example/DE2-115/fpga/fpga.sdc
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@ -51,11 +51,11 @@ derive_pll_clocks
derive_clock_uncertainty
source ../lib/eth/syn/eth_mac_1g_rgmii.sdc
source ../lib/eth/syn/rgmii_phy_if.sdc
source ../lib/eth/syn/rgmii_io.sdc
source ../lib/eth/lib/axis/syn/sync_reset.sdc
source ../lib/eth/lib/axis/syn/axis_async_fifo.sdc
source ../lib/eth/syn/quartus/eth_mac_1g_rgmii.sdc
source ../lib/eth/syn/quartus/rgmii_phy_if.sdc
source ../lib/eth/syn/quartus/rgmii_io.sdc
source ../lib/eth/lib/axis/syn/quartus/sync_reset.sdc
source ../lib/eth/lib/axis/syn/quartus/axis_async_fifo.sdc
# clocking infrastructure
constrain_sync_reset_inst "sync_reset_inst"

6
example/ExaNIC_X10/fpga/fpga/Makefile
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@ -48,9 +48,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl
# IP
IP_TCL_FILES = ip/gtwizard_ultrascale_0.tcl

6
example/ExaNIC_X25/fpga_10g/fpga/Makefile
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@ -48,9 +48,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl
# IP
IP_TCL_FILES = ip/gtwizard_ultrascale_0.tcl

10
example/KC705/fpga_gmii/fpga/Makefile
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@ -46,11 +46,11 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += clock.xdc
XDC_FILES += lib/eth/syn/gmii_phy_if.tcl
XDC_FILES += lib/eth/syn/eth_mac_1g_gmii.tcl
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/gmii_phy_if.tcl
XDC_FILES += lib/eth/syn/vivado/eth_mac_1g_gmii.tcl
XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl
include ../common/vivado.mk

10
example/KC705/fpga_rgmii/fpga/Makefile
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@ -46,11 +46,11 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += eth.xdc
XDC_FILES += lib/eth/syn/rgmii_phy_if.tcl
XDC_FILES += lib/eth/syn/eth_mac_1g_rgmii.tcl
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/rgmii_phy_if.tcl
XDC_FILES += lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl
XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl
include ../common/vivado.mk

6
example/KC705/fpga_sgmii/fpga/Makefile
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@ -40,9 +40,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl
# IP
IP_TCL_FILES = ip/gig_ethernet_pcs_pma_0.tcl

6
example/NetFPGA_SUME/fpga/fpga/Makefile
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@ -50,9 +50,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl
# IP
IP_TCL_FILES = ip/ten_gig_eth_pcs_pma_0.tcl

10
example/NexysVideo/fpga/fpga/Makefile
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@ -47,11 +47,11 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += eth.xdc
XDC_FILES += lib/eth/syn/rgmii_phy_if.tcl
XDC_FILES += lib/eth/syn/eth_mac_1g_rgmii.tcl
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/rgmii_phy_if.tcl
XDC_FILES += lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl
XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl
include ../common/vivado.mk

6
example/VCU108/fpga_10g/fpga/Makefile
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@ -57,9 +57,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += eth.xdc
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl
# IP
IP_TCL_FILES = ip/gig_ethernet_pcs_pma_0.tcl

6
example/VCU108/fpga_1g/fpga/Makefile
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@ -41,9 +41,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += eth.xdc
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl
# IP
IP_TCL_FILES = ip/gig_ethernet_pcs_pma_0.tcl

6
example/VCU118/fpga_10g/fpga/Makefile
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@ -57,9 +57,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl
# IP
IP_TCL_FILES = ip/gig_ethernet_pcs_pma_0.tcl

6
example/VCU118/fpga_1g/fpga/Makefile
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@ -41,9 +41,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl
# IP
IP_TCL_FILES = ip/gig_ethernet_pcs_pma_0.tcl

6
example/VCU118/fpga_25g/fpga/Makefile
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@ -57,9 +57,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl
# IP
IP_TCL_FILES = ip/gig_ethernet_pcs_pma_0.tcl

6
example/VCU1525/fpga_10g/fpga/Makefile
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@ -50,9 +50,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl
# IP
IP_TCL_FILES = ip/gtwizard_ultrascale_0.tcl

6
example/ZCU102/fpga/fpga/Makefile
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@ -49,9 +49,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl
# IP
IP_TCL_FILES = ip/gtwizard_ultrascale_0.tcl

6
example/ZCU106/fpga/fpga/Makefile
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@ -49,9 +49,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl
# IP
IP_TCL_FILES = ip/gtwizard_ultrascale_0.tcl

6
example/fb2CG/fpga_10g/fpga/Makefile
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@ -50,9 +50,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += led.tcl
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl
# IP
IP_TCL_FILES += ip/gtwizard_ultrascale_0.tcl

0
syn/eth_mac_1g_gmii.sdc → syn/quartus/eth_mac_1g_gmii.sdc
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0
syn/eth_mac_1g_rgmii.sdc → syn/quartus/eth_mac_1g_rgmii.sdc
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0
syn/gmii_phy_if.sdc → syn/quartus/gmii_phy_if.sdc
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0
syn/mii_phy_if.sdc → syn/quartus/mii_phy_if.sdc
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0
syn/rgmii_io.sdc → syn/quartus/rgmii_io.sdc
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0
syn/rgmii_phy_if.sdc → syn/quartus/rgmii_phy_if.sdc
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0
syn/eth_mac_1g_gmii.tcl → syn/vivado/eth_mac_1g_gmii.tcl
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0
syn/eth_mac_1g_rgmii.tcl → syn/vivado/eth_mac_1g_rgmii.tcl
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0
syn/eth_mac_fifo.tcl → syn/vivado/eth_mac_fifo.tcl
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0
syn/gmii_phy_if.tcl → syn/vivado/gmii_phy_if.tcl
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0
syn/mii_phy_if.tcl → syn/vivado/mii_phy_if.tcl
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0
syn/ptp_clock_cdc.tcl → syn/vivado/ptp_clock_cdc.tcl
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0
syn/rgmii_phy_if.tcl → syn/vivado/rgmii_phy_if.tcl
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