From 7751aba8daf67388071e156ef1613927daffb947 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Tue, 18 May 2021 16:15:41 -0700 Subject: [PATCH] Reorganize timing constraints --- example/ADM_PCIE_9V3/fpga_10g/fpga/Makefile | 6 +++--- example/ADM_PCIE_9V3/fpga_25g/fpga/Makefile | 6 +++--- example/AU200/fpga_10g/fpga/Makefile | 6 +++--- example/AU250/fpga_10g/fpga/Makefile | 6 +++--- example/AU280/fpga_10g/fpga/Makefile | 6 +++--- example/AU50/fpga_10g/fpga/Makefile | 6 +++--- example/Arty/fpga/fpga/Makefile | 8 ++++---- example/C10LP/fpga/fpga.sdc | 10 +++++----- example/DE2-115/fpga/fpga.sdc | 10 +++++----- example/ExaNIC_X10/fpga/fpga/Makefile | 6 +++--- example/ExaNIC_X25/fpga_10g/fpga/Makefile | 6 +++--- example/KC705/fpga_gmii/fpga/Makefile | 10 +++++----- example/KC705/fpga_rgmii/fpga/Makefile | 10 +++++----- example/KC705/fpga_sgmii/fpga/Makefile | 6 +++--- example/NetFPGA_SUME/fpga/fpga/Makefile | 6 +++--- example/NexysVideo/fpga/fpga/Makefile | 10 +++++----- example/VCU108/fpga_10g/fpga/Makefile | 6 +++--- example/VCU108/fpga_1g/fpga/Makefile | 6 +++--- example/VCU118/fpga_10g/fpga/Makefile | 6 +++--- example/VCU118/fpga_1g/fpga/Makefile | 6 +++--- example/VCU118/fpga_25g/fpga/Makefile | 6 +++--- example/VCU1525/fpga_10g/fpga/Makefile | 6 +++--- example/ZCU102/fpga/fpga/Makefile | 6 +++--- example/ZCU106/fpga/fpga/Makefile | 6 +++--- example/fb2CG/fpga_10g/fpga/Makefile | 6 +++--- syn/{ => quartus}/eth_mac_1g_gmii.sdc | 0 syn/{ => quartus}/eth_mac_1g_rgmii.sdc | 0 syn/{ => quartus}/gmii_phy_if.sdc | 0 syn/{ => quartus}/mii_phy_if.sdc | 0 syn/{ => quartus}/rgmii_io.sdc | 0 syn/{ => quartus}/rgmii_phy_if.sdc | 0 syn/{ => vivado}/eth_mac_1g_gmii.tcl | 0 syn/{ => vivado}/eth_mac_1g_rgmii.tcl | 0 syn/{ => vivado}/eth_mac_fifo.tcl | 0 syn/{ => vivado}/gmii_phy_if.tcl | 0 syn/{ => vivado}/mii_phy_if.tcl | 0 syn/{ => vivado}/ptp_clock_cdc.tcl | 0 syn/{ => vivado}/rgmii_phy_if.tcl | 0 38 files changed, 86 insertions(+), 86 deletions(-) rename syn/{ => quartus}/eth_mac_1g_gmii.sdc (100%) rename syn/{ => quartus}/eth_mac_1g_rgmii.sdc (100%) rename syn/{ => quartus}/gmii_phy_if.sdc (100%) rename syn/{ => quartus}/mii_phy_if.sdc (100%) rename syn/{ => quartus}/rgmii_io.sdc (100%) rename syn/{ => quartus}/rgmii_phy_if.sdc (100%) rename syn/{ => vivado}/eth_mac_1g_gmii.tcl (100%) rename syn/{ => vivado}/eth_mac_1g_rgmii.tcl (100%) rename syn/{ => vivado}/eth_mac_fifo.tcl (100%) rename syn/{ => vivado}/gmii_phy_if.tcl (100%) rename syn/{ => vivado}/mii_phy_if.tcl (100%) rename syn/{ => vivado}/ptp_clock_cdc.tcl (100%) rename syn/{ => vivado}/rgmii_phy_if.tcl (100%) diff --git a/example/ADM_PCIE_9V3/fpga_10g/fpga/Makefile b/example/ADM_PCIE_9V3/fpga_10g/fpga/Makefile index 114a80de..1fe8b992 100644 --- a/example/ADM_PCIE_9V3/fpga_10g/fpga/Makefile +++ b/example/ADM_PCIE_9V3/fpga_10g/fpga/Makefile @@ -49,9 +49,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v # XDC files XDC_FILES = fpga.xdc -XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl # IP IP_TCL_FILES += ip/gtwizard_ultrascale_0.tcl diff --git a/example/ADM_PCIE_9V3/fpga_25g/fpga/Makefile b/example/ADM_PCIE_9V3/fpga_25g/fpga/Makefile index 114a80de..1fe8b992 100644 --- a/example/ADM_PCIE_9V3/fpga_25g/fpga/Makefile +++ b/example/ADM_PCIE_9V3/fpga_25g/fpga/Makefile @@ -49,9 +49,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v # XDC files XDC_FILES = fpga.xdc -XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl # IP IP_TCL_FILES += ip/gtwizard_ultrascale_0.tcl diff --git a/example/AU200/fpga_10g/fpga/Makefile b/example/AU200/fpga_10g/fpga/Makefile index 149a2480..240a1110 100644 --- a/example/AU200/fpga_10g/fpga/Makefile +++ b/example/AU200/fpga_10g/fpga/Makefile @@ -50,9 +50,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v # XDC files XDC_FILES = fpga.xdc -XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl # IP IP_TCL_FILES = ip/gtwizard_ultrascale_0.tcl diff --git a/example/AU250/fpga_10g/fpga/Makefile b/example/AU250/fpga_10g/fpga/Makefile index 56564740..ba7e0137 100644 --- a/example/AU250/fpga_10g/fpga/Makefile +++ b/example/AU250/fpga_10g/fpga/Makefile @@ -50,9 +50,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v # XDC files XDC_FILES = fpga.xdc -XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl # IP IP_TCL_FILES = ip/gtwizard_ultrascale_0.tcl diff --git a/example/AU280/fpga_10g/fpga/Makefile b/example/AU280/fpga_10g/fpga/Makefile index 78988829..fbb41e49 100644 --- a/example/AU280/fpga_10g/fpga/Makefile +++ b/example/AU280/fpga_10g/fpga/Makefile @@ -49,9 +49,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v # XDC files XDC_FILES = fpga.xdc -XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl # IP IP_TCL_FILES = ip/gtwizard_ultrascale_0.tcl diff --git a/example/AU50/fpga_10g/fpga/Makefile b/example/AU50/fpga_10g/fpga/Makefile index 0cd5f999..57912cd9 100644 --- a/example/AU50/fpga_10g/fpga/Makefile +++ b/example/AU50/fpga_10g/fpga/Makefile @@ -49,9 +49,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v # XDC files XDC_FILES = fpga.xdc -XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl # IP IP_TCL_FILES = ip/gtwizard_ultrascale_0.tcl diff --git a/example/Arty/fpga/fpga/Makefile b/example/Arty/fpga/fpga/Makefile index 06002699..8d7fa523 100644 --- a/example/Arty/fpga/fpga/Makefile +++ b/example/Arty/fpga/fpga/Makefile @@ -43,10 +43,10 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v # XDC files XDC_FILES = fpga.xdc -XDC_FILES += lib/eth/syn/mii_phy_if.tcl -XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl +XDC_FILES += lib/eth/syn/vivado/mii_phy_if.tcl +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl include ../common/vivado.mk diff --git a/example/C10LP/fpga/fpga.sdc b/example/C10LP/fpga/fpga.sdc index c920e83e..546ffff9 100644 --- a/example/C10LP/fpga/fpga.sdc +++ b/example/C10LP/fpga/fpga.sdc @@ -41,11 +41,11 @@ derive_pll_clocks derive_clock_uncertainty -source ../lib/eth/syn/eth_mac_1g_rgmii.sdc -source ../lib/eth/syn/rgmii_phy_if.sdc -source ../lib/eth/syn/rgmii_io.sdc -source ../lib/eth/lib/axis/syn/sync_reset.sdc -source ../lib/eth/lib/axis/syn/axis_async_fifo.sdc +source ../lib/eth/syn/quartus/eth_mac_1g_rgmii.sdc +source ../lib/eth/syn/quartus/rgmii_phy_if.sdc +source ../lib/eth/syn/quartus/rgmii_io.sdc +source ../lib/eth/lib/axis/syn/quartus/sync_reset.sdc +source ../lib/eth/lib/axis/syn/quartus/axis_async_fifo.sdc # clocking infrastructure constrain_sync_reset_inst "sync_reset_inst" diff --git a/example/DE2-115/fpga/fpga.sdc b/example/DE2-115/fpga/fpga.sdc index 68cddb96..65005394 100644 --- a/example/DE2-115/fpga/fpga.sdc +++ b/example/DE2-115/fpga/fpga.sdc @@ -51,11 +51,11 @@ derive_pll_clocks derive_clock_uncertainty -source ../lib/eth/syn/eth_mac_1g_rgmii.sdc -source ../lib/eth/syn/rgmii_phy_if.sdc -source ../lib/eth/syn/rgmii_io.sdc -source ../lib/eth/lib/axis/syn/sync_reset.sdc -source ../lib/eth/lib/axis/syn/axis_async_fifo.sdc +source ../lib/eth/syn/quartus/eth_mac_1g_rgmii.sdc +source ../lib/eth/syn/quartus/rgmii_phy_if.sdc +source ../lib/eth/syn/quartus/rgmii_io.sdc +source ../lib/eth/lib/axis/syn/quartus/sync_reset.sdc +source ../lib/eth/lib/axis/syn/quartus/axis_async_fifo.sdc # clocking infrastructure constrain_sync_reset_inst "sync_reset_inst" diff --git a/example/ExaNIC_X10/fpga/fpga/Makefile b/example/ExaNIC_X10/fpga/fpga/Makefile index 7ca4147d..0c18de02 100644 --- a/example/ExaNIC_X10/fpga/fpga/Makefile +++ b/example/ExaNIC_X10/fpga/fpga/Makefile @@ -48,9 +48,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v # XDC files XDC_FILES = fpga.xdc -XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl # IP IP_TCL_FILES = ip/gtwizard_ultrascale_0.tcl diff --git a/example/ExaNIC_X25/fpga_10g/fpga/Makefile b/example/ExaNIC_X25/fpga_10g/fpga/Makefile index c824d0ed..2df67a1c 100644 --- a/example/ExaNIC_X25/fpga_10g/fpga/Makefile +++ b/example/ExaNIC_X25/fpga_10g/fpga/Makefile @@ -48,9 +48,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v # XDC files XDC_FILES = fpga.xdc -XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl # IP IP_TCL_FILES = ip/gtwizard_ultrascale_0.tcl diff --git a/example/KC705/fpga_gmii/fpga/Makefile b/example/KC705/fpga_gmii/fpga/Makefile index 32b2acb8..de262c0b 100644 --- a/example/KC705/fpga_gmii/fpga/Makefile +++ b/example/KC705/fpga_gmii/fpga/Makefile @@ -46,11 +46,11 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v # XDC files XDC_FILES = fpga.xdc XDC_FILES += clock.xdc -XDC_FILES += lib/eth/syn/gmii_phy_if.tcl -XDC_FILES += lib/eth/syn/eth_mac_1g_gmii.tcl -XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl +XDC_FILES += lib/eth/syn/vivado/gmii_phy_if.tcl +XDC_FILES += lib/eth/syn/vivado/eth_mac_1g_gmii.tcl +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl include ../common/vivado.mk diff --git a/example/KC705/fpga_rgmii/fpga/Makefile b/example/KC705/fpga_rgmii/fpga/Makefile index 0f1faf64..17ba63b2 100644 --- a/example/KC705/fpga_rgmii/fpga/Makefile +++ b/example/KC705/fpga_rgmii/fpga/Makefile @@ -46,11 +46,11 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v # XDC files XDC_FILES = fpga.xdc XDC_FILES += eth.xdc -XDC_FILES += lib/eth/syn/rgmii_phy_if.tcl -XDC_FILES += lib/eth/syn/eth_mac_1g_rgmii.tcl -XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl +XDC_FILES += lib/eth/syn/vivado/rgmii_phy_if.tcl +XDC_FILES += lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl include ../common/vivado.mk diff --git a/example/KC705/fpga_sgmii/fpga/Makefile b/example/KC705/fpga_sgmii/fpga/Makefile index 75ae3902..8713beb5 100644 --- a/example/KC705/fpga_sgmii/fpga/Makefile +++ b/example/KC705/fpga_sgmii/fpga/Makefile @@ -40,9 +40,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v # XDC files XDC_FILES = fpga.xdc -XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl # IP IP_TCL_FILES = ip/gig_ethernet_pcs_pma_0.tcl diff --git a/example/NetFPGA_SUME/fpga/fpga/Makefile b/example/NetFPGA_SUME/fpga/fpga/Makefile index 6f8ad6cb..b2936564 100644 --- a/example/NetFPGA_SUME/fpga/fpga/Makefile +++ b/example/NetFPGA_SUME/fpga/fpga/Makefile @@ -50,9 +50,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v # XDC files XDC_FILES = fpga.xdc -XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl # IP IP_TCL_FILES = ip/ten_gig_eth_pcs_pma_0.tcl diff --git a/example/NexysVideo/fpga/fpga/Makefile b/example/NexysVideo/fpga/fpga/Makefile index 61146e75..be5207ad 100644 --- a/example/NexysVideo/fpga/fpga/Makefile +++ b/example/NexysVideo/fpga/fpga/Makefile @@ -47,11 +47,11 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v # XDC files XDC_FILES = fpga.xdc XDC_FILES += eth.xdc -XDC_FILES += lib/eth/syn/rgmii_phy_if.tcl -XDC_FILES += lib/eth/syn/eth_mac_1g_rgmii.tcl -XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl +XDC_FILES += lib/eth/syn/vivado/rgmii_phy_if.tcl +XDC_FILES += lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl include ../common/vivado.mk diff --git a/example/VCU108/fpga_10g/fpga/Makefile b/example/VCU108/fpga_10g/fpga/Makefile index fbb18736..e1663378 100644 --- a/example/VCU108/fpga_10g/fpga/Makefile +++ b/example/VCU108/fpga_10g/fpga/Makefile @@ -57,9 +57,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v # XDC files XDC_FILES = fpga.xdc XDC_FILES += eth.xdc -XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl # IP IP_TCL_FILES = ip/gig_ethernet_pcs_pma_0.tcl diff --git a/example/VCU108/fpga_1g/fpga/Makefile b/example/VCU108/fpga_1g/fpga/Makefile index d4cab008..d807b1b9 100644 --- a/example/VCU108/fpga_1g/fpga/Makefile +++ b/example/VCU108/fpga_1g/fpga/Makefile @@ -41,9 +41,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v # XDC files XDC_FILES = fpga.xdc XDC_FILES += eth.xdc -XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl # IP IP_TCL_FILES = ip/gig_ethernet_pcs_pma_0.tcl diff --git a/example/VCU118/fpga_10g/fpga/Makefile b/example/VCU118/fpga_10g/fpga/Makefile index 20889e81..a9a7377a 100644 --- a/example/VCU118/fpga_10g/fpga/Makefile +++ b/example/VCU118/fpga_10g/fpga/Makefile @@ -57,9 +57,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v # XDC files XDC_FILES = fpga.xdc -XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl # IP IP_TCL_FILES = ip/gig_ethernet_pcs_pma_0.tcl diff --git a/example/VCU118/fpga_1g/fpga/Makefile b/example/VCU118/fpga_1g/fpga/Makefile index 6a22bdae..9269e226 100644 --- a/example/VCU118/fpga_1g/fpga/Makefile +++ b/example/VCU118/fpga_1g/fpga/Makefile @@ -41,9 +41,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v # XDC files XDC_FILES = fpga.xdc -XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl # IP IP_TCL_FILES = ip/gig_ethernet_pcs_pma_0.tcl diff --git a/example/VCU118/fpga_25g/fpga/Makefile b/example/VCU118/fpga_25g/fpga/Makefile index 20889e81..a9a7377a 100644 --- a/example/VCU118/fpga_25g/fpga/Makefile +++ b/example/VCU118/fpga_25g/fpga/Makefile @@ -57,9 +57,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v # XDC files XDC_FILES = fpga.xdc -XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl # IP IP_TCL_FILES = ip/gig_ethernet_pcs_pma_0.tcl diff --git a/example/VCU1525/fpga_10g/fpga/Makefile b/example/VCU1525/fpga_10g/fpga/Makefile index 3a8fc202..91f90a07 100644 --- a/example/VCU1525/fpga_10g/fpga/Makefile +++ b/example/VCU1525/fpga_10g/fpga/Makefile @@ -50,9 +50,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v # XDC files XDC_FILES = fpga.xdc -XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl # IP IP_TCL_FILES = ip/gtwizard_ultrascale_0.tcl diff --git a/example/ZCU102/fpga/fpga/Makefile b/example/ZCU102/fpga/fpga/Makefile index 7e68dca2..316ca06e 100644 --- a/example/ZCU102/fpga/fpga/Makefile +++ b/example/ZCU102/fpga/fpga/Makefile @@ -49,9 +49,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v # XDC files XDC_FILES = fpga.xdc -XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl # IP IP_TCL_FILES = ip/gtwizard_ultrascale_0.tcl diff --git a/example/ZCU106/fpga/fpga/Makefile b/example/ZCU106/fpga/fpga/Makefile index 9fe7e4ac..71af5134 100644 --- a/example/ZCU106/fpga/fpga/Makefile +++ b/example/ZCU106/fpga/fpga/Makefile @@ -49,9 +49,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v # XDC files XDC_FILES = fpga.xdc -XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl # IP IP_TCL_FILES = ip/gtwizard_ultrascale_0.tcl diff --git a/example/fb2CG/fpga_10g/fpga/Makefile b/example/fb2CG/fpga_10g/fpga/Makefile index 32e884d8..881ae2fd 100644 --- a/example/fb2CG/fpga_10g/fpga/Makefile +++ b/example/fb2CG/fpga_10g/fpga/Makefile @@ -50,9 +50,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v # XDC files XDC_FILES = fpga.xdc XDC_FILES += led.tcl -XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl -XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl # IP IP_TCL_FILES += ip/gtwizard_ultrascale_0.tcl diff --git a/syn/eth_mac_1g_gmii.sdc b/syn/quartus/eth_mac_1g_gmii.sdc similarity index 100% rename from syn/eth_mac_1g_gmii.sdc rename to syn/quartus/eth_mac_1g_gmii.sdc diff --git a/syn/eth_mac_1g_rgmii.sdc b/syn/quartus/eth_mac_1g_rgmii.sdc similarity index 100% rename from syn/eth_mac_1g_rgmii.sdc rename to syn/quartus/eth_mac_1g_rgmii.sdc diff --git a/syn/gmii_phy_if.sdc b/syn/quartus/gmii_phy_if.sdc similarity index 100% rename from syn/gmii_phy_if.sdc rename to syn/quartus/gmii_phy_if.sdc diff --git a/syn/mii_phy_if.sdc b/syn/quartus/mii_phy_if.sdc similarity index 100% rename from syn/mii_phy_if.sdc rename to syn/quartus/mii_phy_if.sdc diff --git a/syn/rgmii_io.sdc b/syn/quartus/rgmii_io.sdc similarity index 100% rename from syn/rgmii_io.sdc rename to syn/quartus/rgmii_io.sdc diff --git a/syn/rgmii_phy_if.sdc b/syn/quartus/rgmii_phy_if.sdc similarity index 100% rename from syn/rgmii_phy_if.sdc rename to syn/quartus/rgmii_phy_if.sdc diff --git a/syn/eth_mac_1g_gmii.tcl b/syn/vivado/eth_mac_1g_gmii.tcl similarity index 100% rename from syn/eth_mac_1g_gmii.tcl rename to syn/vivado/eth_mac_1g_gmii.tcl diff --git a/syn/eth_mac_1g_rgmii.tcl b/syn/vivado/eth_mac_1g_rgmii.tcl similarity index 100% rename from syn/eth_mac_1g_rgmii.tcl rename to syn/vivado/eth_mac_1g_rgmii.tcl diff --git a/syn/eth_mac_fifo.tcl b/syn/vivado/eth_mac_fifo.tcl similarity index 100% rename from syn/eth_mac_fifo.tcl rename to syn/vivado/eth_mac_fifo.tcl diff --git a/syn/gmii_phy_if.tcl b/syn/vivado/gmii_phy_if.tcl similarity index 100% rename from syn/gmii_phy_if.tcl rename to syn/vivado/gmii_phy_if.tcl diff --git a/syn/mii_phy_if.tcl b/syn/vivado/mii_phy_if.tcl similarity index 100% rename from syn/mii_phy_if.tcl rename to syn/vivado/mii_phy_if.tcl diff --git a/syn/ptp_clock_cdc.tcl b/syn/vivado/ptp_clock_cdc.tcl similarity index 100% rename from syn/ptp_clock_cdc.tcl rename to syn/vivado/ptp_clock_cdc.tcl diff --git a/syn/rgmii_phy_if.tcl b/syn/vivado/rgmii_phy_if.tcl similarity index 100% rename from syn/rgmii_phy_if.tcl rename to syn/vivado/rgmii_phy_if.tcl