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Add missing wires

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Alex Forencich 2021-10-20 02:01:33 -07:00
parent 9f6f388a3c
commit 786eabac4b
1 changed files with 3 additions and 0 deletions
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rtl/eth_mac_phy_10g_fifo.v
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@ -201,6 +201,9 @@ end
wire rx_error_bad_frame_int;
wire rx_error_bad_fcs_int;
wire rx_bad_block_int;
wire rx_block_lock_int;
wire rx_high_ber_int;
reg [4:0] rx_sync_reg_1 = 5'd0;
reg [4:0] rx_sync_reg_2 = 5'd0;