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Add bus width checks

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This commit is contained in:
Alex Forencich 2016-07-19 16:21:15 -07:00
parent 5afe1d7e1e
commit 7d7cba0838
2 changed files with 8 additions and 0 deletions
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4
tb/gmii_ep.py
View File

@ -88,6 +88,8 @@ def GMIISource(clk, rst,
fifo=None,
name=None):
assert len(txd) == 8
@instance
def logic():
frame = None
@ -141,6 +143,8 @@ def GMIISink(clk, rst,
fifo=None,
name=None):
assert len(rxd) == 8
@instance
def logic():
frame = None

4
tb/xgmii_ep.py
View File

@ -109,6 +109,8 @@ def XGMIISource(clk, rst,
fifo=None,
name=None):
assert len(txd) == 64
@instance
def logic():
frame = None
@ -210,6 +212,8 @@ def XGMIISink(clk, rst,
fifo=None,
name=None):
assert len(rxd) == 64
@instance
def logic():
frame = None