mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-14 06:43:18 +08:00
Remove extraneous code
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
parent
4676296c49
commit
7e5f6a2589
@ -376,7 +376,6 @@ always @(posedge output_clk) begin
|
||||
sample_acc_reg <= $signed({1'b0, edge_2_reg}) - $signed({1'b0, edge_1_reg});
|
||||
sample_acc_sync_reg <= sample_acc_reg;
|
||||
if (active_reg != 0) begin
|
||||
sample_update_reg <= !sample_update_reg;
|
||||
sample_acc_sync_valid_reg <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
Loading…
x
Reference in New Issue
Block a user